[linux.git] / arch / powerpc / sysdev / fsl_rio.h

/*
 * Freescale MPC85xx/MPC86xx RapidIO support
 *
 * Copyright 2009 Sysgo AG
 * Thomas Moll <[email protected]>
 * - fixed maintenance access routines, check for aligned access
 *
 * Copyright 2009 Integrated Device Technology, Inc.
 * Alex Bounine <[email protected]>
 * - Added Port-Write message handling
 * - Added Machine Check exception handling
 *
 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
 * Zhang Wei <[email protected]>
 * Lian Minghuan-B31939 <[email protected]>
 * Liu Gang <[email protected]>
 *
 * Copyright 2005 MontaVista Software, Inc.
 * Matt Porter <[email protected]>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __FSL_RIO_H
#define __FSL_RIO_H

#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <linux/kfifo.h>

#define RIO_REGS_WIN(mport)	(((struct rio_priv *)(mport->priv))->regs_win)

#define RIO_MAINT_WIN_SIZE	0x400000
#define RIO_LTLEDCSR		0x0608

#define DOORBELL_ROWAR_EN	0x80000000
#define DOORBELL_ROWAR_TFLOWLV	0x08000000 /* highest priority level */
#define DOORBELL_ROWAR_PCI	0x02000000 /* PCI window */
#define DOORBELL_ROWAR_NREAD	0x00040000 /* NREAD */
#define DOORBELL_ROWAR_MAINTRD	0x00070000  /* maintenance read */
#define DOORBELL_ROWAR_RES	0x00002000 /* wrtpy: reserverd */
#define DOORBELL_ROWAR_MAINTWD	0x00007000
#define DOORBELL_ROWAR_SIZE	0x0000000b /* window size is 4k */

#define RIO_ATMU_REGS_PORT1_OFFSET	0x10c00
#define RIO_ATMU_REGS_PORT2_OFFSET	0x10e00
#define RIO_S_DBELL_REGS_OFFSET	0x13400
#define RIO_S_PW_REGS_OFFSET	0x134e0
#define RIO_ATMU_REGS_DBELL_OFFSET	0x10C40
#define RIO_INB_ATMU_REGS_PORT1_OFFSET 0x10d60
#define RIO_INB_ATMU_REGS_PORT2_OFFSET 0x10f60

#define MAX_MSG_UNIT_NUM	2
#define MAX_PORT_NUM		4
#define RIO_INB_ATMU_COUNT	4

struct rio_atmu_regs {
	 u32 rowtar;
	 u32 rowtear;
	 u32 rowbar;
	 u32 pad1;
	 u32 rowar;
	 u32 pad2[3];
};

struct rio_inb_atmu_regs {
	u32 riwtar;
	u32 pad1;
	u32 riwbar;
	u32 pad2;
	u32 riwar;
	u32 pad3[3];
};

struct rio_dbell_ring {
	void *virt;
	dma_addr_t phys;
};

struct rio_port_write_msg {
	 void *virt;
	 dma_addr_t phys;
	 u32 msg_count;
	 u32 err_count;
	 u32 discard_count;
};

struct fsl_rio_dbell {
	struct rio_mport *mport[MAX_PORT_NUM];
	struct device *dev;
	struct rio_dbell_regs __iomem *dbell_regs;
	struct rio_dbell_ring dbell_ring;
	int bellirq;
};

struct fsl_rio_pw {
	struct rio_mport *mport[MAX_PORT_NUM];
	struct device *dev;
	struct rio_pw_regs __iomem *pw_regs;
	struct rio_port_write_msg port_write_msg;
	int pwirq;
	struct work_struct pw_work;
	struct kfifo pw_fifo;
	spinlock_t pw_fifo_lock;
};

struct rio_priv {
	struct device *dev;
	void __iomem *regs_win;
	struct rio_atmu_regs __iomem *atmu_regs;
	struct rio_atmu_regs __iomem *maint_atmu_regs;
	struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
	void __iomem *maint_win;
	void *rmm_handle; /* RapidIO message manager(unit) Handle */
};

extern void __iomem *rio_regs_win;
extern void __iomem *rmu_regs_win;

extern resource_size_t rio_law_start;

extern struct fsl_rio_dbell *dbell;
extern struct fsl_rio_pw *pw;

extern int fsl_rio_setup_rmu(struct rio_mport *mport,
	struct device_node *node);
extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
extern void fsl_rio_port_error_handler(int offset);
extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);

extern int fsl_rio_doorbell_send(struct rio_mport *mport,
				int index, u16 destid, u16 data);
extern int fsl_add_outb_message(struct rio_mport *mport,
	struct rio_dev *rdev,
	int mbox, void *buffer, size_t len);
extern int fsl_open_outb_mbox(struct rio_mport *mport,
	void *dev_id, int mbox, int entries);
extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
extern int fsl_open_inb_mbox(struct rio_mport *mport,
	void *dev_id, int mbox, int entries);
extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);

#endif
Commit	Line	Data
6ec4bedb LG	1	/*
	2	* Freescale MPC85xx/MPC86xx RapidIO support
	3	*
	4	* Copyright 2009 Sysgo AG
	5	* Thomas Moll <[email protected]>
	6	* - fixed maintenance access routines, check for aligned access
	7	*
	8	* Copyright 2009 Integrated Device Technology, Inc.
	9	* Alex Bounine <[email protected]>
	10	* - Added Port-Write message handling
	11	* - Added Machine Check exception handling
	12	*
	13	* Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
	14	* Zhang Wei <[email protected]>
	15	* Lian Minghuan-B31939 <[email protected]>
	16	* Liu Gang <[email protected]>
	17	*
	18	* Copyright 2005 MontaVista Software, Inc.
	19	* Matt Porter <[email protected]>
	20	*
	21	* This program is free software; you can redistribute it and/or modify it
	22	* under the terms of the GNU General Public License as published by the
	23	* Free Software Foundation; either version 2 of the License, or (at your
	24	* option) any later version.
	25	*/
	26
	27	#ifndef __FSL_RIO_H
	28	#define __FSL_RIO_H
	29
	30	#include <linux/rio.h>
	31	#include <linux/rio_drv.h>
	32	#include <linux/kfifo.h>
	33
	34	#define RIO_REGS_WIN(mport) (((struct rio_priv *)(mport->priv))->regs_win)
	35
	36	#define RIO_MAINT_WIN_SIZE 0x400000
	37	#define RIO_LTLEDCSR 0x0608
	38
abc3aeae LG	39	#define DOORBELL_ROWAR_EN 0x80000000
	40	#define DOORBELL_ROWAR_TFLOWLV 0x08000000 /* highest priority level */
	41	#define DOORBELL_ROWAR_PCI 0x02000000 /* PCI window */
	42	#define DOORBELL_ROWAR_NREAD 0x00040000 /* NREAD */
	43	#define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
	44	#define DOORBELL_ROWAR_RES 0x00002000 /* wrtpy: reserverd */
	45	#define DOORBELL_ROWAR_MAINTWD 0x00007000
	46	#define DOORBELL_ROWAR_SIZE 0x0000000b /* window size is 4k */
	47
	48	#define RIO_ATMU_REGS_PORT1_OFFSET 0x10c00
	49	#define RIO_ATMU_REGS_PORT2_OFFSET 0x10e00
	50	#define RIO_S_DBELL_REGS_OFFSET 0x13400
	51	#define RIO_S_PW_REGS_OFFSET 0x134e0
	52	#define RIO_ATMU_REGS_DBELL_OFFSET 0x10C40
e6a546fd MG	53	#define RIO_INB_ATMU_REGS_PORT1_OFFSET 0x10d60
e6a546fd MG	54	#define RIO_INB_ATMU_REGS_PORT2_OFFSET 0x10f60
abc3aeae LG	55
	56	#define MAX_MSG_UNIT_NUM 2
	57	#define MAX_PORT_NUM 4
e6a546fd	58	#define RIO_INB_ATMU_COUNT 4
abc3aeae	59
6ec4bedb LG	60	struct rio_atmu_regs {
	61	u32 rowtar;
	62	u32 rowtear;
	63	u32 rowbar;
abc3aeae	64	u32 pad1;
6ec4bedb	65	u32 rowar;
abc3aeae LG	66	u32 pad2[3];
	67	};
	68
e6a546fd MG	69	struct rio_inb_atmu_regs {
	70	u32 riwtar;
	71	u32 pad1;
	72	u32 riwbar;
	73	u32 pad2;
	74	u32 riwar;
	75	u32 pad3[3];
	76	};
	77
abc3aeae LG	78	struct rio_dbell_ring {
	79	void *virt;
	80	dma_addr_t phys;
6ec4bedb LG	81	};
	82
	83	struct rio_port_write_msg {
	84	void *virt;
	85	dma_addr_t phys;
	86	u32 msg_count;
	87	u32 err_count;
	88	u32 discard_count;
	89	};
	90
abc3aeae LG	91	struct fsl_rio_dbell {
abc3aeae LG	92	struct rio_mport *mport[MAX_PORT_NUM];
6ec4bedb	93	struct device *dev;
abc3aeae LG	94	struct rio_dbell_regs __iomem *dbell_regs;
	95	struct rio_dbell_ring dbell_ring;
	96	int bellirq;
	97	};
	98
	99	struct fsl_rio_pw {
9a0b0627	100	struct rio_mport *mport[MAX_PORT_NUM];
abc3aeae LG	101	struct device *dev;
abc3aeae LG	102	struct rio_pw_regs __iomem *pw_regs;
6ec4bedb LG	103	struct rio_port_write_msg port_write_msg;
	104	int pwirq;
	105	struct work_struct pw_work;
	106	struct kfifo pw_fifo;
	107	spinlock_t pw_fifo_lock;
abc3aeae LG	108	};
	109
	110	struct rio_priv {
	111	struct device *dev;
	112	void __iomem *regs_win;
	113	struct rio_atmu_regs __iomem *atmu_regs;
	114	struct rio_atmu_regs __iomem *maint_atmu_regs;
e6a546fd	115	struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
abc3aeae	116	void __iomem *maint_win;
6ec4bedb LG	117	void rmm_handle; / RapidIO message manager(unit) Handle */
	118	};
	119
	120	extern void __iomem *rio_regs_win;
abc3aeae LG	121	extern void __iomem *rmu_regs_win;
	122
	123	extern resource_size_t rio_law_start;
	124
	125	extern struct fsl_rio_dbell *dbell;
	126	extern struct fsl_rio_pw *pw;
6ec4bedb LG	127
	128	extern int fsl_rio_setup_rmu(struct rio_mport *mport,
	129	struct device_node *node);
abc3aeae	130	extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
6ec4bedb	131	extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
abc3aeae LG	132	extern void fsl_rio_port_error_handler(int offset);
	133	extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
	134
	135	extern int fsl_rio_doorbell_send(struct rio_mport *mport,
	136	int index, u16 destid, u16 data);
	137	extern int fsl_add_outb_message(struct rio_mport *mport,
	138	struct rio_dev *rdev,
	139	int mbox, void *buffer, size_t len);
	140	extern int fsl_open_outb_mbox(struct rio_mport *mport,
	141	void *dev_id, int mbox, int entries);
	142	extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
	143	extern int fsl_open_inb_mbox(struct rio_mport *mport,
	144	void *dev_id, int mbox, int entries);
	145	extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
	146	extern int fsl_add_inb_buffer(struct rio_mport mport, int mbox, void buf);
	147	extern void fsl_get_inb_message(struct rio_mport mport, int mbox);
6ec4bedb LG	148
6ec4bedb LG	149	#endif