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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2010-2011 Canonical Ltd <[email protected]> | |
3 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Fixed rate clock implementation | |
10 | */ | |
11 | ||
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/err.h> | |
015ba402 | 17 | #include <linux/of.h> |
435779fe | 18 | #include <linux/platform_device.h> |
9d9f78ed MT |
19 | |
20 | /* | |
21 | * DOC: basic fixed-rate clock that cannot gate | |
22 | * | |
23 | * Traits of this clock: | |
24 | * prepare - clk_(un)prepare only ensures parents are prepared | |
25 | * enable - clk_enable only ensures parents are enabled | |
26 | * rate - rate is always a fixed value. No clk_set_rate support | |
27 | * parent - fixed parent. No clk_set_parent support | |
28 | */ | |
29 | ||
9d9f78ed MT |
30 | static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw, |
31 | unsigned long parent_rate) | |
32 | { | |
33 | return to_clk_fixed_rate(hw)->fixed_rate; | |
34 | } | |
9d9f78ed | 35 | |
0903ea60 BB |
36 | static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw, |
37 | unsigned long parent_accuracy) | |
38 | { | |
39 | return to_clk_fixed_rate(hw)->fixed_accuracy; | |
40 | } | |
41 | ||
822c250e | 42 | const struct clk_ops clk_fixed_rate_ops = { |
9d9f78ed | 43 | .recalc_rate = clk_fixed_rate_recalc_rate, |
0903ea60 | 44 | .recalc_accuracy = clk_fixed_rate_recalc_accuracy, |
9d9f78ed MT |
45 | }; |
46 | EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); | |
47 | ||
27d54591 | 48 | /** |
26ef56be SB |
49 | * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with |
50 | * the clock framework | |
27d54591 MT |
51 | * @dev: device that is registering this clock |
52 | * @name: name of this clock | |
53 | * @parent_name: name of clock's parent | |
54 | * @flags: framework-specific flags | |
55 | * @fixed_rate: non-adjustable clock rate | |
0903ea60 | 56 | * @fixed_accuracy: non-adjustable clock rate |
27d54591 | 57 | */ |
26ef56be | 58 | struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, |
0903ea60 BB |
59 | const char *name, const char *parent_name, unsigned long flags, |
60 | unsigned long fixed_rate, unsigned long fixed_accuracy) | |
9d9f78ed MT |
61 | { |
62 | struct clk_fixed_rate *fixed; | |
26ef56be | 63 | struct clk_hw *hw; |
0197b3ea | 64 | struct clk_init_data init; |
26ef56be | 65 | int ret; |
9d9f78ed | 66 | |
27d54591 | 67 | /* allocate fixed-rate clock */ |
d122db7e SB |
68 | fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); |
69 | if (!fixed) | |
9d9f78ed | 70 | return ERR_PTR(-ENOMEM); |
9d9f78ed | 71 | |
0197b3ea SK |
72 | init.name = name; |
73 | init.ops = &clk_fixed_rate_ops; | |
f7d8caad | 74 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
75 | init.parent_names = (parent_name ? &parent_name: NULL); |
76 | init.num_parents = (parent_name ? 1 : 0); | |
77 | ||
9d9f78ed MT |
78 | /* struct clk_fixed_rate assignments */ |
79 | fixed->fixed_rate = fixed_rate; | |
0903ea60 | 80 | fixed->fixed_accuracy = fixed_accuracy; |
0197b3ea | 81 | fixed->hw.init = &init; |
9d9f78ed | 82 | |
27d54591 | 83 | /* register the clock */ |
26ef56be SB |
84 | hw = &fixed->hw; |
85 | ret = clk_hw_register(dev, hw); | |
86 | if (ret) { | |
27d54591 | 87 | kfree(fixed); |
26ef56be SB |
88 | hw = ERR_PTR(ret); |
89 | } | |
27d54591 | 90 | |
26ef56be SB |
91 | return hw; |
92 | } | |
93 | EXPORT_SYMBOL_GPL(clk_hw_register_fixed_rate_with_accuracy); | |
94 | ||
95 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, | |
96 | const char *name, const char *parent_name, unsigned long flags, | |
97 | unsigned long fixed_rate, unsigned long fixed_accuracy) | |
98 | { | |
99 | struct clk_hw *hw; | |
100 | ||
101 | hw = clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, | |
102 | flags, fixed_rate, fixed_accuracy); | |
103 | if (IS_ERR(hw)) | |
104 | return ERR_CAST(hw); | |
105 | return hw->clk; | |
9d9f78ed | 106 | } |
0903ea60 BB |
107 | EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy); |
108 | ||
109 | /** | |
26ef56be SB |
110 | * clk_hw_register_fixed_rate - register fixed-rate clock with the clock |
111 | * framework | |
0903ea60 BB |
112 | * @dev: device that is registering this clock |
113 | * @name: name of this clock | |
114 | * @parent_name: name of clock's parent | |
115 | * @flags: framework-specific flags | |
116 | * @fixed_rate: non-adjustable clock rate | |
117 | */ | |
26ef56be SB |
118 | struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, |
119 | const char *parent_name, unsigned long flags, | |
120 | unsigned long fixed_rate) | |
121 | { | |
122 | return clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, | |
123 | flags, fixed_rate, 0); | |
124 | } | |
125 | EXPORT_SYMBOL_GPL(clk_hw_register_fixed_rate); | |
126 | ||
0903ea60 BB |
127 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
128 | const char *parent_name, unsigned long flags, | |
129 | unsigned long fixed_rate) | |
130 | { | |
131 | return clk_register_fixed_rate_with_accuracy(dev, name, parent_name, | |
132 | flags, fixed_rate, 0); | |
133 | } | |
389ae05f | 134 | EXPORT_SYMBOL_GPL(clk_register_fixed_rate); |
015ba402 | 135 | |
0b225e41 MY |
136 | void clk_unregister_fixed_rate(struct clk *clk) |
137 | { | |
138 | struct clk_hw *hw; | |
139 | ||
140 | hw = __clk_get_hw(clk); | |
141 | if (!hw) | |
142 | return; | |
143 | ||
144 | clk_unregister(clk); | |
145 | kfree(to_clk_fixed_rate(hw)); | |
146 | } | |
147 | EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate); | |
148 | ||
52445637 MY |
149 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw) |
150 | { | |
151 | struct clk_fixed_rate *fixed; | |
152 | ||
153 | fixed = to_clk_fixed_rate(hw); | |
154 | ||
155 | clk_hw_unregister(hw); | |
156 | kfree(fixed); | |
157 | } | |
158 | EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_rate); | |
159 | ||
015ba402 | 160 | #ifdef CONFIG_OF |
435779fe | 161 | static struct clk *_of_fixed_clk_setup(struct device_node *node) |
015ba402 GL |
162 | { |
163 | struct clk *clk; | |
164 | const char *clk_name = node->name; | |
165 | u32 rate; | |
0903ea60 | 166 | u32 accuracy = 0; |
435779fe | 167 | int ret; |
015ba402 GL |
168 | |
169 | if (of_property_read_u32(node, "clock-frequency", &rate)) | |
435779fe | 170 | return ERR_PTR(-EIO); |
015ba402 | 171 | |
0903ea60 BB |
172 | of_property_read_u32(node, "clock-accuracy", &accuracy); |
173 | ||
015ba402 GL |
174 | of_property_read_string(node, "clock-output-names", &clk_name); |
175 | ||
0903ea60 | 176 | clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL, |
d3781a74 | 177 | 0, rate, accuracy); |
435779fe RR |
178 | if (IS_ERR(clk)) |
179 | return clk; | |
180 | ||
181 | ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
182 | if (ret) { | |
183 | clk_unregister(clk); | |
184 | return ERR_PTR(ret); | |
185 | } | |
186 | ||
187 | return clk; | |
188 | } | |
189 | ||
190 | /** | |
191 | * of_fixed_clk_setup() - Setup function for simple fixed rate clock | |
192 | */ | |
d336e9a7 | 193 | void __init of_fixed_clk_setup(struct device_node *node) |
435779fe RR |
194 | { |
195 | _of_fixed_clk_setup(node); | |
015ba402 | 196 | } |
f2f6c255 | 197 | CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup); |
435779fe RR |
198 | |
199 | static int of_fixed_clk_remove(struct platform_device *pdev) | |
200 | { | |
201 | struct clk *clk = platform_get_drvdata(pdev); | |
202 | ||
52091c25 | 203 | of_clk_del_provider(pdev->dev.of_node); |
435779fe RR |
204 | clk_unregister_fixed_rate(clk); |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | static int of_fixed_clk_probe(struct platform_device *pdev) | |
210 | { | |
211 | struct clk *clk; | |
212 | ||
213 | /* | |
214 | * This function is not executed when of_fixed_clk_setup | |
215 | * succeeded. | |
216 | */ | |
217 | clk = _of_fixed_clk_setup(pdev->dev.of_node); | |
218 | if (IS_ERR(clk)) | |
219 | return PTR_ERR(clk); | |
220 | ||
221 | platform_set_drvdata(pdev, clk); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static const struct of_device_id of_fixed_clk_ids[] = { | |
227 | { .compatible = "fixed-clock" }, | |
228 | { } | |
229 | }; | |
230 | MODULE_DEVICE_TABLE(of, of_fixed_clk_ids); | |
231 | ||
232 | static struct platform_driver of_fixed_clk_driver = { | |
233 | .driver = { | |
234 | .name = "of_fixed_clk", | |
235 | .of_match_table = of_fixed_clk_ids, | |
236 | }, | |
237 | .probe = of_fixed_clk_probe, | |
238 | .remove = of_fixed_clk_remove, | |
239 | }; | |
240 | builtin_platform_driver(of_fixed_clk_driver); | |
015ba402 | 241 | #endif |