[linux.git] / drivers / nvmem / meson-mx-efuse.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
 *
 * Copyright (c) 2017 Martin Blumenstingl <[email protected]>
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/sizes.h>
#include <linux/slab.h>

#define MESON_MX_EFUSE_CNTL1					0x04
#define MESON_MX_EFUSE_CNTL1_PD_ENABLE				BIT(27)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY			BIT(26)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START			BIT(25)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE			BIT(24)
#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA			GENMASK(23, 16)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY			BIT(14)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START			BIT(13)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE			BIT(12)
#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET			BIT(11)
#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK			GENMASK(10, 0)

#define MESON_MX_EFUSE_CNTL2					0x08

#define MESON_MX_EFUSE_CNTL4					0x10
#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE			BIT(10)

struct meson_mx_efuse_platform_data {
	const char *name;
	unsigned int word_size;
};

struct meson_mx_efuse {
	void __iomem *base;
	struct clk *core_clk;
	struct nvmem_config config;
};

static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
				     u32 mask, u32 set)
{
	u32 data;

	data = readl(efuse->base + reg);
	data &= ~mask;
	data |= (set & mask);

	writel(data, efuse->base + reg);
}

static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
{
	int err;

	err = clk_prepare_enable(efuse->core_clk);
	if (err)
		return err;

	/* power up the efuse */
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);

	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
				 MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);

	return 0;
}

static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
{
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_PD_ENABLE,
				 MESON_MX_EFUSE_CNTL1_PD_ENABLE);

	clk_disable_unprepare(efuse->core_clk);
}

static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
				    unsigned int addr, u32 *value)
{
	int err;
	u32 regval;

	/* write the address to read */
	regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);

	/* inform the hardware that we changed the address */
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);

	/* start the read process */
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);

	/*
	 * perform a dummy read to ensure that the HW has the RD_BUSY bit set
	 * when polling for the status below.
	 */
	readl(efuse->base + MESON_MX_EFUSE_CNTL1);

	err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
			regval,
			(!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
			1, 1000);
	if (err) {
		dev_err(efuse->config.dev,
			"Timeout while reading efuse address %u\n", addr);
		return err;
	}

	*value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);

	return 0;
}

static int meson_mx_efuse_read(void *context, unsigned int offset,
			       void *buf, size_t bytes)
{
	struct meson_mx_efuse *efuse = context;
	u32 tmp;
	int err, i, addr;

	err = meson_mx_efuse_hw_enable(efuse);
	if (err)
		return err;

	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);

	for (i = 0; i < bytes; i += efuse->config.word_size) {
		addr = (offset + i) / efuse->config.word_size;

		err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
		if (err)
			break;

		memcpy(buf + i, &tmp,
		       min_t(size_t, bytes - i, efuse->config.word_size));
	}

	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);

	meson_mx_efuse_hw_disable(efuse);

	return err;
}

static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
	.name = "meson6-efuse",
	.word_size = 1,
};

static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
	.name = "meson8-efuse",
	.word_size = 4,
};

static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
	.name = "meson8b-efuse",
	.word_size = 4,
};

static const struct of_device_id meson_mx_efuse_match[] = {
	{ .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
	{ .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
	{ .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);

static int meson_mx_efuse_probe(struct platform_device *pdev)
{
	const struct meson_mx_efuse_platform_data *drvdata;
	struct meson_mx_efuse *efuse;
	struct nvmem_device *nvmem;

	drvdata = of_device_get_match_data(&pdev->dev);
	if (!drvdata)
		return -EINVAL;

	efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
	if (!efuse)
		return -ENOMEM;

	efuse->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(efuse->base))
		return PTR_ERR(efuse->base);

	efuse->config.name = drvdata->name;
	efuse->config.owner = THIS_MODULE;
	efuse->config.dev = &pdev->dev;
	efuse->config.priv = efuse;
	efuse->config.add_legacy_fixed_of_cells = true;
	efuse->config.stride = drvdata->word_size;
	efuse->config.word_size = drvdata->word_size;
	efuse->config.size = SZ_512;
	efuse->config.read_only = true;
	efuse->config.reg_read = meson_mx_efuse_read;

	efuse->core_clk = devm_clk_get(&pdev->dev, "core");
	if (IS_ERR(efuse->core_clk)) {
		dev_err(&pdev->dev, "Failed to get core clock\n");
		return PTR_ERR(efuse->core_clk);
	}

	nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);

	return PTR_ERR_OR_ZERO(nvmem);
}

static struct platform_driver meson_mx_efuse_driver = {
	.probe = meson_mx_efuse_probe,
	.driver = {
		.name = "meson-mx-efuse",
		.of_match_table = meson_mx_efuse_match,
	},
};

module_platform_driver(meson_mx_efuse_driver);

MODULE_AUTHOR("Martin Blumenstingl <[email protected]>");
MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5b497af4	1	// SPDX-License-Identifier: GPL-2.0-only
8caef1fa MB	2	/*
	3	* Amlogic Meson6, Meson8 and Meson8b eFuse Driver
	4	*
	5	* Copyright (c) 2017 Martin Blumenstingl <[email protected]>
8caef1fa MB	6	*/
	7
	8	#include <linux/bitfield.h>
	9	#include <linux/bitops.h>
	10	#include <linux/clk.h>
	11	#include <linux/delay.h>
	12	#include <linux/io.h>
	13	#include <linux/iopoll.h>
	14	#include <linux/module.h>
	15	#include <linux/nvmem-provider.h>
	16	#include <linux/of.h>
8caef1fa MB	17	#include <linux/platform_device.h>
	18	#include <linux/sizes.h>
	19	#include <linux/slab.h>
	20
	21	#define MESON_MX_EFUSE_CNTL1 0x04
	22	#define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27)
	23	#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26)
	24	#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25)
	25	#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24)
	26	#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)
	27	#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14)
	28	#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13)
	29	#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12)
	30	#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11)
	31	#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)
	32
	33	#define MESON_MX_EFUSE_CNTL2 0x08
	34
	35	#define MESON_MX_EFUSE_CNTL4 0x10
	36	#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10)
	37
	38	struct meson_mx_efuse_platform_data {
	39	const char *name;
	40	unsigned int word_size;
	41	};
	42
	43	struct meson_mx_efuse {
	44	void __iomem *base;
	45	struct clk *core_clk;
8caef1fa MB	46	struct nvmem_config config;
	47	};
	48
	49	static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
	50	u32 mask, u32 set)
	51	{
	52	u32 data;
	53
	54	data = readl(efuse->base + reg);
	55	data &= ~mask;
	56	data \|= (set & mask);
	57
	58	writel(data, efuse->base + reg);
	59	}
	60
	61	static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
	62	{
	63	int err;
	64
	65	err = clk_prepare_enable(efuse->core_clk);
	66	if (err)
	67	return err;
	68
	69	/* power up the efuse */
	70	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	71	MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);
	72
	73	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
	74	MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);
	75
	76	return 0;
	77	}
	78
	79	static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
	80	{
	81	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	82	MESON_MX_EFUSE_CNTL1_PD_ENABLE,
	83	MESON_MX_EFUSE_CNTL1_PD_ENABLE);
	84
	85	clk_disable_unprepare(efuse->core_clk);
	86	}
	87
	88	static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
	89	unsigned int addr, u32 *value)
	90	{
	91	int err;
	92	u32 regval;
	93
	94	/* write the address to read */
	95	regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
	96	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	97	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);
	98
	99	/* inform the hardware that we changed the address */
	100	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	101	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
	102	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
	103	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	104	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);
	105
	106	/* start the read process */
	107	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	108	MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
	109	MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
110	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
111	MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);
112
113	/*
114	* perform a dummy read to ensure that the HW has the RD_BUSY bit set
115	* when polling for the status below.
116	*/
117	readl(efuse->base + MESON_MX_EFUSE_CNTL1);
118
119	err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
120	regval,
121	(!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
122	1, 1000);
123	if (err) {
124	dev_err(efuse->config.dev,
125	"Timeout while reading efuse address %u\n", addr);
126	return err;
127	}
128
129	*value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
130
131	return 0;
132	}
133
134	static int meson_mx_efuse_read(void *context, unsigned int offset,
135	void *buf, size_t bytes)
136	{
137	struct meson_mx_efuse *efuse = context;
138	u32 tmp;
139	int err, i, addr;
140
141	err = meson_mx_efuse_hw_enable(efuse);
142	if (err)
143	return err;
144
145	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
146	MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
147	MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);
148
8a42d3fc MB	149	for (i = 0; i < bytes; i += efuse->config.word_size) {
8a42d3fc MB	150	addr = (offset + i) / efuse->config.word_size;
8caef1fa MB	151
	152	err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
	153	if (err)
	154	break;
	155
cb6b0a39 MB	156	memcpy(buf + i, &tmp,
cb6b0a39 MB	157	min_t(size_t, bytes - i, efuse->config.word_size));
8caef1fa MB	158	}
	159
	160	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	161	MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);
	162
	163	meson_mx_efuse_hw_disable(efuse);
	164
	165	return err;
	166	}
	167
	168	static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
	169	.name = "meson6-efuse",
	170	.word_size = 1,
	171	};
	172
	173	static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
	174	.name = "meson8-efuse",
	175	.word_size = 4,
	176	};
	177
	178	static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
	179	.name = "meson8b-efuse",
	180	.word_size = 4,
	181	};
	182
	183	static const struct of_device_id meson_mx_efuse_match[] = {
	184	{ .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
	185	{ .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
	186	{ .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
	187	{ /* sentinel */ },
	188	};
	189	MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);
	190
	191	static int meson_mx_efuse_probe(struct platform_device *pdev)
	192	{
	193	const struct meson_mx_efuse_platform_data *drvdata;
	194	struct meson_mx_efuse *efuse;
2a1ad6b7	195	struct nvmem_device *nvmem;
8caef1fa MB	196
	197	drvdata = of_device_get_match_data(&pdev->dev);
	198	if (!drvdata)
	199	return -EINVAL;
	200
	201	efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
	202	if (!efuse)
	203	return -ENOMEM;
	204
0a223a09	205	efuse->base = devm_platform_ioremap_resource(pdev, 0);
8caef1fa MB	206	if (IS_ERR(efuse->base))
	207	return PTR_ERR(efuse->base);
	208
4dc8d89f	209	efuse->config.name = drvdata->name;
8caef1fa MB	210	efuse->config.owner = THIS_MODULE;
	211	efuse->config.dev = &pdev->dev;
	212	efuse->config.priv = efuse;
2cc3b37f	213	efuse->config.add_legacy_fixed_of_cells = true;
8caef1fa MB	214	efuse->config.stride = drvdata->word_size;
	215	efuse->config.word_size = drvdata->word_size;
	216	efuse->config.size = SZ_512;
	217	efuse->config.read_only = true;
	218	efuse->config.reg_read = meson_mx_efuse_read;
	219
	220	efuse->core_clk = devm_clk_get(&pdev->dev, "core");
	221	if (IS_ERR(efuse->core_clk)) {
	222	dev_err(&pdev->dev, "Failed to get core clock\n");
	223	return PTR_ERR(efuse->core_clk);
	224	}
	225
2a1ad6b7	226	nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
8caef1fa	227
2a1ad6b7	228	return PTR_ERR_OR_ZERO(nvmem);
8caef1fa MB	229	}
	230
	231	static struct platform_driver meson_mx_efuse_driver = {
	232	.probe = meson_mx_efuse_probe,
8caef1fa MB	233	.driver = {
	234	.name = "meson-mx-efuse",
	235	.of_match_table = meson_mx_efuse_match,
	236	},
	237	};
	238
	239	module_platform_driver(meson_mx_efuse_driver);
	240
	241	MODULE_AUTHOR("Martin Blumenstingl <[email protected]>");
	242	MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
	243	MODULE_LICENSE("GPL v2");