[linux.git] / drivers / edac / i82875p_edac.c

/*
 * Intel D82875P Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Contributors:
 *	Wang Zhenyu at intel.com
 *
 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define EDAC_MOD_STR		"i82875p_edac"

#define i82875p_printk(level, fmt, arg...) \
	edac_printk(level, "i82875p", fmt, ##arg)

#define i82875p_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_82875_0
#define PCI_DEVICE_ID_INTEL_82875_0	0x2578
#endif				/* PCI_DEVICE_ID_INTEL_82875_0 */

#ifndef PCI_DEVICE_ID_INTEL_82875_6
#define PCI_DEVICE_ID_INTEL_82875_6	0x257e
#endif				/* PCI_DEVICE_ID_INTEL_82875_6 */

/* four csrows in dual channel, eight in single channel */
#define I82875P_NR_DIMMS		8
#define I82875P_NR_CSROWS(nr_chans)	(I82875P_NR_DIMMS / (nr_chans))

/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
#define I82875P_EAP		0x58	/* Error Address Pointer (32b)
					 *
					 * 31:12 block address
					 * 11:0  reserved
					 */

#define I82875P_DERRSYN		0x5c	/* DRAM Error Syndrome (8b)
					 *
					 *  7:0  DRAM ECC Syndrome
					 */

#define I82875P_DES		0x5d	/* DRAM Error Status (8b)
					 *
					 *  7:1  reserved
					 *  0    Error channel 0/1
					 */

#define I82875P_ERRSTS		0xc8	/* Error Status Register (16b)
					 *
					 * 15:10 reserved
					 *  9    non-DRAM lock error (ndlock)
					 *  8    Sftwr Generated SMI
					 *  7    ECC UE
					 *  6    reserved
					 *  5    MCH detects unimplemented cycle
					 *  4    AGP access outside GA
					 *  3    Invalid AGP access
					 *  2    Invalid GA translation table
					 *  1    Unsupported AGP command
					 *  0    ECC CE
					 */

#define I82875P_ERRCMD		0xca	/* Error Command (16b)
					 *
					 * 15:10 reserved
					 *  9    SERR on non-DRAM lock
					 *  8    SERR on ECC UE
					 *  7    SERR on ECC CE
					 *  6    target abort on high exception
					 *  5    detect unimplemented cyc
					 *  4    AGP access outside of GA
					 *  3    SERR on invalid AGP access
					 *  2    invalid translation table
					 *  1    SERR on unsupported AGP command
					 *  0    reserved
					 */

/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
#define I82875P_PCICMD6		0x04	/* PCI Command Register (16b)
					 *
					 * 15:10 reserved
					 *  9    fast back-to-back - ro 0
					 *  8    SERR enable - ro 0
					 *  7    addr/data stepping - ro 0
					 *  6    parity err enable - ro 0
					 *  5    VGA palette snoop - ro 0
					 *  4    mem wr & invalidate - ro 0
					 *  3    special cycle - ro 0
					 *  2    bus master - ro 0
					 *  1    mem access dev6 - 0(dis),1(en)
					 *  0    IO access dev3 - 0(dis),1(en)
					 */

#define I82875P_BAR6		0x10	/* Mem Delays Base ADDR Reg (32b)
					 *
					 * 31:12 mem base addr [31:12]
					 * 11:4  address mask - ro 0
					 *  3    prefetchable - ro 0(non),1(pre)
					 *  2:1  mem type - ro 0
					 *  0    mem space - ro 0
					 */

/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */

#define I82875P_DRB_SHIFT 26	/* 64MiB grain */
#define I82875P_DRB		0x00	/* DRAM Row Boundary (8b x 8)
					 *
					 *  7    reserved
					 *  6:0  64MiB row boundary addr
					 */

#define I82875P_DRA		0x10	/* DRAM Row Attribute (4b x 8)
					 *
					 *  7    reserved
					 *  6:4  row attr row 1
					 *  3    reserved
					 *  2:0  row attr row 0
					 *
					 * 000 =  4KiB
					 * 001 =  8KiB
					 * 010 = 16KiB
					 * 011 = 32KiB
					 */

#define I82875P_DRC		0x68	/* DRAM Controller Mode (32b)
					 *
					 * 31:30 reserved
					 * 29    init complete
					 * 28:23 reserved
					 * 22:21 nr chan 00=1,01=2
					 * 20    reserved
					 * 19:18 Data Integ Mode 00=none,01=ecc
					 * 17:11 reserved
					 * 10:8  refresh mode
					 *  7    reserved
					 *  6:4  mode select
					 *  3:2  reserved
					 *  1:0  DRAM type 01=DDR
					 */

enum i82875p_chips {
	I82875P = 0,
};

struct i82875p_pvt {
	struct pci_dev *ovrfl_pdev;
	void __iomem *ovrfl_window;
};

struct i82875p_dev_info {
	const char *ctl_name;
};

struct i82875p_error_info {
	u16 errsts;
	u32 eap;
	u8 des;
	u8 derrsyn;
	u16 errsts2;
};

static const struct i82875p_dev_info i82875p_devs[] = {
	[I82875P] = {
		.ctl_name = "i82875p"},
};

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
					 * already registered driver
					 */

static struct edac_pci_ctl_info *i82875p_pci;

static void i82875p_get_error_info(struct mem_ctl_info *mci,
				struct i82875p_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);

	if (!(info->errsts & 0x0081))
		return;

	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
	pci_read_config_byte(pdev, I82875P_DES, &info->des);
	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same then we can for both reads then
	 * the first set of reads is valid.  If there is a change then
	 * there is a CE no info and the second set of reads is valid
	 * and should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & 0x0081) {
		pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
		pci_read_config_byte(pdev, I82875P_DES, &info->des);
		pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
	}

	pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
}

static int i82875p_process_error_info(struct mem_ctl_info *mci,
				struct i82875p_error_info *info,
				int handle_errors)
{
	int row, multi_chan;

	multi_chan = mci->csrows[0]->nr_channels - 1;

	if (!(info->errsts & 0x0081))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0081) {
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
				     -1, -1, -1,
				     "UE overwrote CE", "");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0080)
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     info->eap, 0, 0,
				     row, -1, -1,
				     "i82875p UE", "");
	else
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     info->eap, 0, info->derrsyn,
				     row, multi_chan ? (info->des & 0x1) : 0,
				     -1, "i82875p CE", "");

	return 1;
}

static void i82875p_check(struct mem_ctl_info *mci)
{
	struct i82875p_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i82875p_get_error_info(mci, &info);
	i82875p_process_error_info(mci, &info, 1);
}

/* Return 0 on success or 1 on failure. */
static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
				struct pci_dev **ovrfl_pdev,
				void __iomem **ovrfl_window)
{
	struct pci_dev *dev;
	void __iomem *window;

	*ovrfl_pdev = NULL;
	*ovrfl_window = NULL;
	dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);

	if (dev == NULL) {
		/* Intel tells BIOS developers to hide device 6 which
		 * configures the overflow device access containing
		 * the DRBs - this is where we expose device 6.
		 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
		 */
		pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
		dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));

		if (dev == NULL)
			return 1;

		pci_bus_assign_resources(dev->bus);
		pci_bus_add_device(dev);
	}

	*ovrfl_pdev = dev;

	if (pci_enable_device(dev)) {
		i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
			"device\n", __func__);
		return 1;
	}

	if (pci_request_regions(dev, pci_name(dev))) {
#ifdef CORRECT_BIOS
		goto fail0;
#endif
	}

	/* cache is irrelevant for PCI bus reads/writes */
	window = pci_ioremap_bar(dev, 0);
	if (window == NULL) {
		i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
			__func__);
		goto fail1;
	}

	*ovrfl_window = window;
	return 0;

fail1:
	pci_release_regions(dev);

#ifdef CORRECT_BIOS
fail0:
	pci_disable_device(dev);
#endif
	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	return 1;
}

/* Return 1 if dual channel mode is active.  Else return 0. */
static inline int dual_channel_active(u32 drc)
{
	return (drc >> 21) & 0x1;
}

static void i82875p_init_csrows(struct mem_ctl_info *mci,
				struct pci_dev *pdev,
				void __iomem * ovrfl_window, u32 drc)
{
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	unsigned nr_chans = dual_channel_active(drc) + 1;
	unsigned long last_cumul_size;
	u8 value;
	u32 drc_ddim;		/* DRAM Data Integrity Mode 0=none,2=edac */
	u32 cumul_size, nr_pages;
	int index, j;

	drc_ddim = (drc >> 18) & 0x1;
	last_cumul_size = 0;

	/* The dram row boundary (DRB) reg values are boundary address
	 * for each DRAM row with a granularity of 32 or 64MB (single/dual
	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
	 * contain the total memory contained in all eight rows.
	 */

	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];

		value = readb(ovrfl_window + I82875P_DRB + index);
		cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;

		for (j = 0; j < nr_chans; j++) {
			dimm = csrow->channels[j]->dimm;

			dimm->nr_pages = nr_pages / nr_chans;
			dimm->grain = 1 << 12;	/* I82875P_EAP has 4KiB reolution */
			dimm->mtype = MEM_DDR;
			dimm->dtype = DEV_UNKNOWN;
			dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
		}
	}
}

static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	struct i82875p_pvt *pvt;
	struct pci_dev *ovrfl_pdev;
	void __iomem *ovrfl_window;
	u32 drc;
	u32 nr_chans;
	struct i82875p_error_info discard;

	edac_dbg(0, "\n");

	if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
		return -ENODEV;
	drc = readl(ovrfl_window + I82875P_DRC);
	nr_chans = dual_channel_active(drc) + 1;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = I82875P_NR_CSROWS(nr_chans);
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = nr_chans;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
	if (!mci) {
		rc = -ENOMEM;
		goto fail0;
	}

	edac_dbg(3, "init mci\n");
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_UNKNOWN;
	mci->mod_name = EDAC_MOD_STR;
	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82875p_check;
	mci->ctl_page_to_phys = NULL;
	edac_dbg(3, "init pvt\n");
	pvt = (struct i82875p_pvt *)mci->pvt_info;
	pvt->ovrfl_pdev = ovrfl_pdev;
	pvt->ovrfl_window = ovrfl_window;
	i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
	i82875p_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail1;
	}

	/* allocating generic PCI control info */
	i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82875p_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "success\n");
	return 0;

fail1:
	edac_mc_free(mci);

fail0:
	iounmap(ovrfl_window);
	pci_release_regions(ovrfl_pdev);

	pci_disable_device(ovrfl_pdev);
	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	return rc;
}

/* returns count (>= 0), or negative on error */
static int i82875p_init_one(struct pci_dev *pdev,
			    const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "\n");
	i82875p_printk(KERN_INFO, "i82875p init one\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i82875p_probe1(pdev, ent->driver_data);

	if (mci_pdev == NULL)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i82875p_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct i82875p_pvt *pvt = NULL;

	edac_dbg(0, "\n");

	if (i82875p_pci)
		edac_pci_release_generic_ctl(i82875p_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	pvt = (struct i82875p_pvt *)mci->pvt_info;

	if (pvt->ovrfl_window)
		iounmap(pvt->ovrfl_window);

	if (pvt->ovrfl_pdev) {
#ifdef CORRECT_BIOS
		pci_release_regions(pvt->ovrfl_pdev);
#endif				/*CORRECT_BIOS */
		pci_disable_device(pvt->ovrfl_pdev);
		pci_dev_put(pvt->ovrfl_pdev);
	}

	edac_mc_free(mci);
}

static const struct pci_device_id i82875p_pci_tbl[] = {
	{
	 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82875P},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);

static struct pci_driver i82875p_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82875p_init_one,
	.remove = i82875p_remove_one,
	.id_table = i82875p_pci_tbl,
};

static int __init i82875p_init(void)
{
	int pci_rc;

	edac_dbg(3, "\n");

       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	pci_rc = pci_register_driver(&i82875p_driver);

	if (pci_rc < 0)
		goto fail0;

	if (mci_pdev == NULL) {
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_82875_0, NULL);

		if (!mci_pdev) {
			edac_dbg(0, "875p pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);

		if (pci_rc < 0) {
			edac_dbg(0, "875p init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82875p_driver);

fail0:
	pci_dev_put(mci_pdev);
	return pci_rc;
}

static void __exit i82875p_exit(void)
{
	edac_dbg(3, "\n");

	i82875p_remove_one(mci_pdev);
	pci_dev_put(mci_pdev);

	pci_unregister_driver(&i82875p_driver);

}

module_init(i82875p_init);
module_exit(i82875p_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel D82875P Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Contributors:
	9	* Wang Zhenyu at intel.com
	10	*
	11	* $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
	12	*
	13	* Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
	14	*/
	15
0d88a10e AC	16	#include <linux/module.h>
0d88a10e AC	17	#include <linux/init.h>
0d88a10e AC	18	#include <linux/pci.h>
0d88a10e AC	19	#include <linux/pci_ids.h>
c3c52bce	20	#include <linux/edac.h>
78d88e8a	21	#include "edac_module.h"
0d88a10e	22
929a40ec	23	#define EDAC_MOD_STR "i82875p_edac"
37f04581	24
537fba28	25	#define i82875p_printk(level, fmt, arg...) \
e7ecd891	26	edac_printk(level, "i82875p", fmt, ##arg)
537fba28 DP	27
537fba28 DP	28	#define i82875p_mc_printk(mci, level, fmt, arg...) \
e7ecd891	29	edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
537fba28	30
0d88a10e AC	31	#ifndef PCI_DEVICE_ID_INTEL_82875_0
	32	#define PCI_DEVICE_ID_INTEL_82875_0 0x2578
	33	#endif /* PCI_DEVICE_ID_INTEL_82875_0 */
	34
	35	#ifndef PCI_DEVICE_ID_INTEL_82875_6
	36	#define PCI_DEVICE_ID_INTEL_82875_6 0x257e
	37	#endif /* PCI_DEVICE_ID_INTEL_82875_6 */
	38
0d88a10e	39	/* four csrows in dual channel, eight in single channel */
0a8a9ac9 MCC	40	#define I82875P_NR_DIMMS 8
0a8a9ac9 MCC	41	#define I82875P_NR_CSROWS(nr_chans) (I82875P_NR_DIMMS / (nr_chans))
0d88a10e	42
0d88a10e AC	43	/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
	44	#define I82875P_EAP 0x58 /* Error Address Pointer (32b)
	45	*
	46	* 31:12 block address
	47	* 11:0 reserved
	48	*/
	49
	50	#define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
	51	*
	52	* 7:0 DRAM ECC Syndrome
	53	*/
	54
	55	#define I82875P_DES 0x5d /* DRAM Error Status (8b)
	56	*
	57	* 7:1 reserved
	58	* 0 Error channel 0/1
	59	*/
	60
	61	#define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
	62	*
	63	* 15:10 reserved
	64	* 9 non-DRAM lock error (ndlock)
	65	* 8 Sftwr Generated SMI
	66	* 7 ECC UE
	67	* 6 reserved
	68	* 5 MCH detects unimplemented cycle
	69	* 4 AGP access outside GA
	70	* 3 Invalid AGP access
	71	* 2 Invalid GA translation table
	72	* 1 Unsupported AGP command
	73	* 0 ECC CE
	74	*/
	75
	76	#define I82875P_ERRCMD 0xca /* Error Command (16b)
	77	*
	78	* 15:10 reserved
	79	* 9 SERR on non-DRAM lock
	80	* 8 SERR on ECC UE
	81	* 7 SERR on ECC CE
	82	* 6 target abort on high exception
	83	* 5 detect unimplemented cyc
	84	* 4 AGP access outside of GA
	85	* 3 SERR on invalid AGP access
	86	* 2 invalid translation table
	87	* 1 SERR on unsupported AGP command
	88	* 0 reserved
	89	*/
	90
0d88a10e AC	91	/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
	92	#define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
	93	*
	94	* 15:10 reserved
	95	* 9 fast back-to-back - ro 0
	96	* 8 SERR enable - ro 0
	97	* 7 addr/data stepping - ro 0
	98	* 6 parity err enable - ro 0
	99	* 5 VGA palette snoop - ro 0
	100	* 4 mem wr & invalidate - ro 0
	101	* 3 special cycle - ro 0
	102	* 2 bus master - ro 0
	103	* 1 mem access dev6 - 0(dis),1(en)
	104	* 0 IO access dev3 - 0(dis),1(en)
	105	*/
	106
	107	#define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
	108	*
	109	* 31:12 mem base addr [31:12]
	110	* 11:4 address mask - ro 0
	111	* 3 prefetchable - ro 0(non),1(pre)
	112	* 2:1 mem type - ro 0
	113	* 0 mem space - ro 0
	114	*/
	115
	116	/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
	117
	118	#define I82875P_DRB_SHIFT 26 /* 64MiB grain */
	119	#define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
	120	*
	121	* 7 reserved
	122	* 6:0 64MiB row boundary addr
	123	*/
	124
	125	#define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
	126	*
	127	* 7 reserved
	128	* 6:4 row attr row 1
	129	* 3 reserved
	130	* 2:0 row attr row 0
	131	*
	132	* 000 = 4KiB
	133	* 001 = 8KiB
	134	* 010 = 16KiB
	135	* 011 = 32KiB
	136	*/
	137
	138	#define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
	139	*
	140	* 31:30 reserved
	141	* 29 init complete
	142	* 28:23 reserved
	143	* 22:21 nr chan 00=1,01=2
	144	* 20 reserved
	145	* 19:18 Data Integ Mode 00=none,01=ecc
	146	* 17:11 reserved
	147	* 10:8 refresh mode
	148	* 7 reserved
	149	* 6:4 mode select
	150	* 3:2 reserved
	151	* 1:0 DRAM type 01=DDR
	152	*/
	153
0d88a10e AC	154	enum i82875p_chips {
	155	I82875P = 0,
	156	};
	157
0d88a10e AC	158	struct i82875p_pvt {
0d88a10e AC	159	struct pci_dev *ovrfl_pdev;
6d57348d	160	void __iomem *ovrfl_window;
0d88a10e AC	161	};
0d88a10e AC	162
0d88a10e AC	163	struct i82875p_dev_info {
	164	const char *ctl_name;
	165	};
	166
0d88a10e AC	167	struct i82875p_error_info {
	168	u16 errsts;
	169	u32 eap;
	170	u8 des;
	171	u8 derrsyn;
	172	u16 errsts2;
	173	};
	174
0d88a10e AC	175	static const struct i82875p_dev_info i82875p_devs[] = {
0d88a10e AC	176	[I82875P] = {
052dfb45	177	.ctl_name = "i82875p"},
0d88a10e AC	178	};
0d88a10e AC	179
f044091c	180	static struct pci_dev mci_pdev; / init dev: in case that AGP code has
e7ecd891 DP	181	* already registered driver
	182	*/
	183
456a2f95 DJ	184	static struct edac_pci_ctl_info *i82875p_pci;
456a2f95 DJ	185
e7ecd891	186	static void i82875p_get_error_info(struct mem_ctl_info *mci,
052dfb45	187	struct i82875p_error_info *info)
0d88a10e	188	{
37f04581 DT	189	struct pci_dev *pdev;
37f04581 DT	190
fd687502	191	pdev = to_pci_dev(mci->pdev);
37f04581	192
0d88a10e AC	193	/*
	194	* This is a mess because there is no atomic way to read all the
	195	* registers at once and the registers can transition from CE being
	196	* overwritten by UE.
	197	*/
37f04581	198	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
654ede20 JU	199
	200	if (!(info->errsts & 0x0081))
	201	return;
	202
37f04581 DT	203	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
	204	pci_read_config_byte(pdev, I82875P_DES, &info->des);
	205	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
	206	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
0d88a10e	207
0d88a10e AC	208	/*
	209	* If the error is the same then we can for both reads then
	210	* the first set of reads is valid. If there is a change then
	211	* there is a CE no info and the second set of reads is valid
	212	* and should be UE info.
	213	*/
0d88a10e	214	if ((info->errsts ^ info->errsts2) & 0x0081) {
37f04581 DT	215	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
37f04581 DT	216	pci_read_config_byte(pdev, I82875P_DES, &info->des);
466b71d5	217	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
0d88a10e	218	}
654ede20 JU	219
654ede20 JU	220	pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
0d88a10e AC	221	}
0d88a10e AC	222
e7ecd891	223	static int i82875p_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	224	struct i82875p_error_info *info,
052dfb45 DT	225	int handle_errors)
0d88a10e AC	226	{
	227	int row, multi_chan;
	228
de3910eb	229	multi_chan = mci->csrows[0]->nr_channels - 1;
0d88a10e	230
654ede20	231	if (!(info->errsts & 0x0081))
0d88a10e AC	232	return 0;
	233
	234	if (!handle_errors)
	235	return 1;
	236
	237	if ((info->errsts ^ info->errsts2) & 0x0081) {
9eb07a7f	238	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0a8a9ac9	239	-1, -1, -1,
03f7eae8	240	"UE overwrote CE", "");
0d88a10e AC	241	info->errsts = info->errsts2;
	242	}
	243
	244	info->eap >>= PAGE_SHIFT;
	245	row = edac_mc_find_csrow_by_page(mci, info->eap);
	246
	247	if (info->errsts & 0x0080)
9eb07a7f	248	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0a8a9ac9 MCC	249	info->eap, 0, 0,
0a8a9ac9 MCC	250	row, -1, -1,
03f7eae8	251	"i82875p UE", "");
0d88a10e	252	else
9eb07a7f	253	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0a8a9ac9 MCC	254	info->eap, 0, info->derrsyn,
0a8a9ac9 MCC	255	row, multi_chan ? (info->des & 0x1) : 0,
03f7eae8	256	-1, "i82875p CE", "");
0d88a10e AC	257
	258	return 1;
	259	}
	260
0d88a10e AC	261	static void i82875p_check(struct mem_ctl_info *mci)
	262	{
	263	struct i82875p_error_info info;
	264
956b9ba1	265	edac_dbg(1, "MC%d\n", mci->mc_idx);
0d88a10e AC	266	i82875p_get_error_info(mci, &info);
	267	i82875p_process_error_info(mci, &info, 1);
	268	}
	269
13189525 DT	270	/* Return 0 on success or 1 on failure. */
13189525 DT	271	static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
052dfb45 DT	272	struct pci_dev **ovrfl_pdev,
052dfb45 DT	273	void __iomem **ovrfl_window)
0d88a10e	274	{
13189525 DT	275	struct pci_dev *dev;
13189525 DT	276	void __iomem *window;
0d88a10e	277
13189525 DT	278	*ovrfl_pdev = NULL;
	279	*ovrfl_window = NULL;
	280	dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
0d88a10e	281
13189525 DT	282	if (dev == NULL) {
13189525 DT	283	/* Intel tells BIOS developers to hide device 6 which
0d88a10e AC	284	* configures the overflow device access containing
	285	* the DRBs - this is where we expose device 6.
	286	* http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
	287	*/
	288	pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
13189525	289	dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
e7ecd891	290
13189525 DT	291	if (dev == NULL)
13189525 DT	292	return 1;
62456726	293
307d1144	294	pci_bus_assign_resources(dev->bus);
617b4157	295	pci_bus_add_device(dev);
0d88a10e	296	}
e7ecd891	297
13189525 DT	298	*ovrfl_pdev = dev;
13189525 DT	299
13189525 DT	300	if (pci_enable_device(dev)) {
13189525 DT	301	i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
052dfb45	302	"device\n", __func__);
13189525	303	return 1;
0d88a10e AC	304	}
0d88a10e AC	305
13189525	306	if (pci_request_regions(dev, pci_name(dev))) {
0d88a10e	307	#ifdef CORRECT_BIOS
637beb69	308	goto fail0;
0d88a10e AC	309	#endif
0d88a10e AC	310	}
e7ecd891	311
0d88a10e	312	/* cache is irrelevant for PCI bus reads/writes */
1dca00bd	313	window = pci_ioremap_bar(dev, 0);
13189525	314	if (window == NULL) {
537fba28	315	i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
052dfb45	316	__func__);
637beb69	317	goto fail1;
0d88a10e AC	318	}
0d88a10e AC	319
13189525 DT	320	*ovrfl_window = window;
13189525 DT	321	return 0;
0d88a10e	322
052dfb45	323	fail1:
13189525	324	pci_release_regions(dev);
0d88a10e	325
13189525	326	#ifdef CORRECT_BIOS
052dfb45	327	fail0:
13189525 DT	328	pci_disable_device(dev);
	329	#endif
	330	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	331	return 1;
	332	}
0d88a10e	333
13189525 DT	334	/* Return 1 if dual channel mode is active. Else return 0. */
	335	static inline int dual_channel_active(u32 drc)
	336	{
	337	return (drc >> 21) & 0x1;
	338	}
0d88a10e	339
13189525	340	static void i82875p_init_csrows(struct mem_ctl_info *mci,
466b71d5 DJ	341	struct pci_dev *pdev,
466b71d5 DJ	342	void __iomem * ovrfl_window, u32 drc)
13189525 DT	343	{
13189525 DT	344	struct csrow_info *csrow;
084a4fcc MCC	345	struct dimm_info *dimm;
084a4fcc MCC	346	unsigned nr_chans = dual_channel_active(drc) + 1;
13189525 DT	347	unsigned long last_cumul_size;
13189525 DT	348	u8 value;
466b71d5	349	u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
a895bf8b	350	u32 cumul_size, nr_pages;
084a4fcc	351	int index, j;
13189525 DT	352
	353	drc_ddim = (drc >> 18) & 0x1;
	354	last_cumul_size = 0;
	355
	356	/* The dram row boundary (DRB) reg values are boundary address
0d88a10e AC	357	* for each DRAM row with a granularity of 32 or 64MB (single/dual
	358	* channel operation). DRB regs are cumulative; therefore DRB7 will
	359	* contain the total memory contained in all eight rows.
	360	*/
13189525 DT	361
13189525 DT	362	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb	363	csrow = mci->csrows[index];
0d88a10e AC	364
	365	value = readb(ovrfl_window + I82875P_DRB + index);
	366	cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
956b9ba1	367	edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
0d88a10e AC	368	if (cumul_size == last_cumul_size)
	369	continue; /* not populated */
	370
	371	csrow->first_page = last_cumul_size;
	372	csrow->last_page = cumul_size - 1;
a895bf8b	373	nr_pages = cumul_size - last_cumul_size;
0d88a10e	374	last_cumul_size = cumul_size;
084a4fcc MCC	375
084a4fcc MCC	376	for (j = 0; j < nr_chans; j++) {
de3910eb	377	dimm = csrow->channels[j]->dimm;
084a4fcc	378
a895bf8b	379	dimm->nr_pages = nr_pages / nr_chans;
084a4fcc MCC	380	dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
	381	dimm->mtype = MEM_DDR;
	382	dimm->dtype = DEV_UNKNOWN;
	383	dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
	384	}
0d88a10e	385	}
13189525 DT	386	}
	387
	388	static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
	389	{
	390	int rc = -ENODEV;
	391	struct mem_ctl_info *mci;
0a8a9ac9	392	struct edac_mc_layer layers[2];
13189525 DT	393	struct i82875p_pvt *pvt;
	394	struct pci_dev *ovrfl_pdev;
	395	void __iomem *ovrfl_window;
	396	u32 drc;
	397	u32 nr_chans;
	398	struct i82875p_error_info discard;
0d88a10e	399
956b9ba1	400	edac_dbg(0, "\n");
c3c52bce	401
13189525 DT	402	if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
	403	return -ENODEV;
	404	drc = readl(ovrfl_window + I82875P_DRC);
	405	nr_chans = dual_channel_active(drc) + 1;
13189525	406
0a8a9ac9 MCC	407	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	408	layers[0].size = I82875P_NR_CSROWS(nr_chans);
	409	layers[0].is_virt_csrow = true;
	410	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	411	layers[1].size = nr_chans;
	412	layers[1].is_virt_csrow = false;
ca0907b9	413	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
13189525 DT	414	if (!mci) {
	415	rc = -ENOMEM;
	416	goto fail0;
	417	}
	418
956b9ba1	419	edac_dbg(3, "init mci\n");
fd687502	420	mci->pdev = &pdev->dev;
13189525 DT	421	mci->mtype_cap = MEM_FLAG_DDR;
	422	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	423	mci->edac_cap = EDAC_FLAG_UNKNOWN;
	424	mci->mod_name = EDAC_MOD_STR;
13189525	425	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
c4192705	426	mci->dev_name = pci_name(pdev);
13189525 DT	427	mci->edac_check = i82875p_check;
13189525 DT	428	mci->ctl_page_to_phys = NULL;
956b9ba1	429	edac_dbg(3, "init pvt\n");
466b71d5	430	pvt = (struct i82875p_pvt *)mci->pvt_info;
13189525 DT	431	pvt->ovrfl_pdev = ovrfl_pdev;
	432	pvt->ovrfl_window = ovrfl_window;
	433	i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
466b71d5	434	i82875p_get_error_info(mci, &discard); /* clear counters */
0d88a10e	435
2d7bbb91 DT	436	/* Here we assume that we will never see multiple instances of this
	437	* type of memory controller. The ID is therefore hardcoded to 0.
	438	*/
b8f6f975	439	if (edac_mc_add_mc(mci)) {
956b9ba1	440	edac_dbg(3, "failed edac_mc_add_mc()\n");
13189525	441	goto fail1;
0d88a10e AC	442	}
0d88a10e AC	443
456a2f95 DJ	444	/* allocating generic PCI control info */
	445	i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	446	if (!i82875p_pci) {
	447	printk(KERN_WARNING
	448	"%s(): Unable to create PCI control\n",
	449	__func__);
	450	printk(KERN_WARNING
	451	"%s(): PCI error report via EDAC not setup\n",
	452	__func__);
	453	}
	454
0d88a10e	455	/* get this far and it's successful */
956b9ba1	456	edac_dbg(3, "success\n");
0d88a10e AC	457	return 0;
0d88a10e AC	458
052dfb45	459	fail1:
637beb69	460	edac_mc_free(mci);
0d88a10e	461
052dfb45	462	fail0:
637beb69	463	iounmap(ovrfl_window);
637beb69	464	pci_release_regions(ovrfl_pdev);
0d88a10e	465
637beb69	466	pci_disable_device(ovrfl_pdev);
0d88a10e AC	467	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	468	return rc;
	469	}
	470
0d88a10e	471	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	472	static int i82875p_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	473	const struct pci_device_id *ent)
0d88a10e AC	474	{
	475	int rc;
	476
956b9ba1	477	edac_dbg(0, "\n");
537fba28	478	i82875p_printk(KERN_INFO, "i82875p init one\n");
e7ecd891 DP	479
e7ecd891 DP	480	if (pci_enable_device(pdev) < 0)
0d88a10e	481	return -EIO;
e7ecd891	482
0d88a10e	483	rc = i82875p_probe1(pdev, ent->driver_data);
e7ecd891	484
0d88a10e AC	485	if (mci_pdev == NULL)
0d88a10e AC	486	mci_pdev = pci_dev_get(pdev);
e7ecd891	487
0d88a10e AC	488	return rc;
	489	}
	490
9b3c6e85	491	static void i82875p_remove_one(struct pci_dev *pdev)
0d88a10e AC	492	{
	493	struct mem_ctl_info *mci;
	494	struct i82875p_pvt *pvt = NULL;
	495
956b9ba1	496	edac_dbg(0, "\n");
0d88a10e	497
456a2f95 DJ	498	if (i82875p_pci)
	499	edac_pci_release_generic_ctl(i82875p_pci);
	500
37f04581	501	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
0d88a10e AC	502	return;
0d88a10e AC	503
466b71d5	504	pvt = (struct i82875p_pvt *)mci->pvt_info;
e7ecd891	505
0d88a10e AC	506	if (pvt->ovrfl_window)
	507	iounmap(pvt->ovrfl_window);
	508
	509	if (pvt->ovrfl_pdev) {
	510	#ifdef CORRECT_BIOS
	511	pci_release_regions(pvt->ovrfl_pdev);
	512	#endif /CORRECT_BIOS /
	513	pci_disable_device(pvt->ovrfl_pdev);
	514	pci_dev_put(pvt->ovrfl_pdev);
	515	}
	516
0d88a10e AC	517	edac_mc_free(mci);
	518	}
	519
ba935f40	520	static const struct pci_device_id i82875p_pci_tbl[] = {
e7ecd891	521	{
466b71d5 DJ	522	PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
466b71d5 DJ	523	I82875P},
e7ecd891	524	{
466b71d5 DJ	525	0,
466b71d5 DJ	526	} /* 0 terminated list. */
0d88a10e AC	527	};
	528
	529	MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
	530
0d88a10e	531	static struct pci_driver i82875p_driver = {
680cbbbb	532	.name = EDAC_MOD_STR,
0d88a10e	533	.probe = i82875p_init_one,
9b3c6e85	534	.remove = i82875p_remove_one,
0d88a10e AC	535	.id_table = i82875p_pci_tbl,
	536	};
	537
da9bb1d2	538	static int __init i82875p_init(void)
0d88a10e AC	539	{
	540	int pci_rc;
	541
956b9ba1	542	edac_dbg(3, "\n");
c3c52bce HM	543
	544	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	545	opstate_init();
	546
0d88a10e	547	pci_rc = pci_register_driver(&i82875p_driver);
e7ecd891	548
0d88a10e	549	if (pci_rc < 0)
637beb69	550	goto fail0;
e7ecd891	551
0d88a10e	552	if (mci_pdev == NULL) {
e7ecd891	553	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	554	PCI_DEVICE_ID_INTEL_82875_0, NULL);
e7ecd891	555
0d88a10e	556	if (!mci_pdev) {
956b9ba1	557	edac_dbg(0, "875p pci_get_device fail\n");
637beb69 DP	558	pci_rc = -ENODEV;
637beb69 DP	559	goto fail1;
0d88a10e	560	}
e7ecd891	561
0d88a10e	562	pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
e7ecd891	563
0d88a10e	564	if (pci_rc < 0) {
956b9ba1	565	edac_dbg(0, "875p init fail\n");
637beb69 DP	566	pci_rc = -ENODEV;
637beb69 DP	567	goto fail1;
0d88a10e AC	568	}
0d88a10e AC	569	}
e7ecd891	570
0d88a10e	571	return 0;
637beb69	572
052dfb45	573	fail1:
637beb69 DP	574	pci_unregister_driver(&i82875p_driver);
637beb69 DP	575
052dfb45	576	fail0:
72601945	577	pci_dev_put(mci_pdev);
637beb69	578	return pci_rc;
0d88a10e AC	579	}
0d88a10e AC	580
0d88a10e AC	581	static void __exit i82875p_exit(void)
0d88a10e AC	582	{
956b9ba1	583	edac_dbg(3, "\n");
0d88a10e	584
09a81269 JL	585	i82875p_remove_one(mci_pdev);
	586	pci_dev_put(mci_pdev);
	587
0d88a10e	588	pci_unregister_driver(&i82875p_driver);
e7ecd891	589
0d88a10e AC	590	}
0d88a10e AC	591
0d88a10e AC	592	module_init(i82875p_init);
	593	module_exit(i82875p_exit);
	594
0d88a10e AC	595	MODULE_LICENSE("GPL");
	596	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
	597	MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
c3c52bce HM	598
	599	module_param(edac_op_state, int, 0444);
	600	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");