[linux.git] / drivers / edac / amd64_edac_dbg.c

// SPDX-License-Identifier: GPL-2.0
#include "amd64_edac.h"

#define EDAC_DCT_ATTR_SHOW(reg)						\
static ssize_t amd64_##reg##_show(struct device *dev,			\
			       struct device_attribute *mattr,		\
			       char *data)				\
{									\
	struct mem_ctl_info *mci = to_mci(dev);				\
	struct amd64_pvt *pvt = mci->pvt_info;				\
		return sprintf(data, "0x%016llx\n", (u64)pvt->reg);	\
}

EDAC_DCT_ATTR_SHOW(dhar);
EDAC_DCT_ATTR_SHOW(dbam0);
EDAC_DCT_ATTR_SHOW(top_mem);
EDAC_DCT_ATTR_SHOW(top_mem2);

static ssize_t amd64_hole_show(struct device *dev,
			       struct device_attribute *mattr,
			       char *data)
{
	struct mem_ctl_info *mci = to_mci(dev);

	u64 hole_base = 0;
	u64 hole_offset = 0;
	u64 hole_size = 0;

	amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);

	return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
						 hole_size);
}

/*
 * update NUM_DBG_ATTRS in case you add new members
 */
static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);

static struct attribute *amd64_edac_dbg_attrs[] = {
	&dev_attr_dhar.attr,
	&dev_attr_dbam.attr,
	&dev_attr_topmem.attr,
	&dev_attr_topmem2.attr,
	&dev_attr_dram_hole.attr,
	NULL
};

const struct attribute_group amd64_edac_dbg_group = {
	.attrs = amd64_edac_dbg_attrs,
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
fd3d6780 DT	2	#include "amd64_edac.h"
fd3d6780 DT	3
9cdeb404	4	#define EDAC_DCT_ATTR_SHOW(reg) \
c5608759 MCC	5	static ssize_t amd64_##reg##_show(struct device *dev, \
	6	struct device_attribute *mattr, \
	7	char *data) \
9cdeb404	8	{ \
c5608759	9	struct mem_ctl_info *mci = to_mci(dev); \
9cdeb404 BP	10	struct amd64_pvt *pvt = mci->pvt_info; \
9cdeb404 BP	11	return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
fd3d6780 DT	12	}
fd3d6780 DT	13
9cdeb404 BP	14	EDAC_DCT_ATTR_SHOW(dhar);
	15	EDAC_DCT_ATTR_SHOW(dbam0);
	16	EDAC_DCT_ATTR_SHOW(top_mem);
	17	EDAC_DCT_ATTR_SHOW(top_mem2);
fd3d6780	18
c5608759 MCC	19	static ssize_t amd64_hole_show(struct device *dev,
	20	struct device_attribute *mattr,
	21	char *data)
fd3d6780	22	{
c5608759 MCC	23	struct mem_ctl_info *mci = to_mci(dev);
c5608759 MCC	24
fd3d6780 DT	25	u64 hole_base = 0;
	26	u64 hole_offset = 0;
	27	u64 hole_size = 0;
	28
	29	amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
	30
	31	return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
	32	hole_size);
	33	}
	34
	35	/*
	36	* update NUM_DBG_ATTRS in case you add new members
	37	*/
c5608759 MCC	38	static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
	39	static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
	40	static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
	41	static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
	42	static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);
	43
e339f1ec TI	44	static struct attribute *amd64_edac_dbg_attrs[] = {
	45	&dev_attr_dhar.attr,
	46	&dev_attr_dbam.attr,
	47	&dev_attr_topmem.attr,
	48	&dev_attr_topmem2.attr,
	49	&dev_attr_dram_hole.attr,
	50	NULL
	51	};
	52
	53	const struct attribute_group amd64_edac_dbg_group = {
	54	.attrs = amd64_edac_dbg_attrs,
	55	};