[linux.git] / drivers / mfd / stmpe.h

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <[email protected]> for ST-Ericsson
 */

#ifndef __STMPE_H
#define __STMPE_H

#include <linux/device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/stmpe.h>
#include <linux/printk.h>
#include <linux/types.h>

extern const struct dev_pm_ops stmpe_dev_pm_ops;

#ifdef STMPE_DUMP_BYTES
static inline void stmpe_dump_bytes(const char *str, const void *buf,
				    size_t len)
{
	print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
}
#else
static inline void stmpe_dump_bytes(const char *str, const void *buf,
				    size_t len)
{
}
#endif

/**
 * struct stmpe_variant_block - information about block
 * @cell:	base mfd cell
 * @irq:	interrupt number to be added to each IORESOURCE_IRQ
 *		in the cell
 * @block:	block id; used for identification with platform data and for
 *		enable and altfunc callbacks
 */
struct stmpe_variant_block {
	const struct mfd_cell	*cell;
	int			irq;
	enum stmpe_block	block;
};

/**
 * struct stmpe_variant_info - variant-specific information
 * @name:	part name
 * @id_val:	content of CHIPID register
 * @id_mask:	bits valid in CHIPID register for comparison with id_val
 * @num_gpios:	number of GPIOS
 * @af_bits:	number of bits used to specify the alternate function
 * @regs: variant specific registers.
 * @blocks:	list of blocks present on this device
 * @num_blocks:	number of blocks present on this device
 * @num_irqs:	number of internal IRQs available on this device
 * @enable:	callback to enable the specified blocks.
 *		Called with the I/O lock held.
 * @get_altfunc: callback to get the alternate function number for the
 *		 specific block
 * @enable_autosleep: callback to configure autosleep with specified timeout
 */
struct stmpe_variant_info {
	const char *name;
	u16 id_val;
	u16 id_mask;
	int num_gpios;
	int af_bits;
	const u8 *regs;
	struct stmpe_variant_block *blocks;
	int num_blocks;
	int num_irqs;
	int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
	int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
	int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
};

/**
 * struct stmpe_client_info - i2c or spi specific routines/info
 * @data: client specific data
 * @read_byte: read single byte
 * @write_byte: write single byte
 * @read_block: read block or multiple bytes
 * @write_block: write block or multiple bytes
 * @init: client init routine, called during probe
 */
struct stmpe_client_info {
	void *data;
	int irq;
	void *client;
	struct device *dev;
	int (*read_byte)(struct stmpe *stmpe, u8 reg);
	int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);
	int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);
	int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,
			const u8 *values);
	void (*init)(struct stmpe *stmpe);
};

int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
int stmpe_remove(struct stmpe *stmpe);

#define STMPE_ICR_LSB_HIGH	(1 << 2)
#define STMPE_ICR_LSB_EDGE	(1 << 1)
#define STMPE_ICR_LSB_GIM	(1 << 0)

#define STMPE_SYS_CTRL_RESET	(1 << 7)
#define STMPE_SYS_CTRL_INT_EN	(1 << 2)
#define STMPE_SYS_CTRL_INT_HI	(1 << 0)

/*
 * STMPE801
 */
#define STMPE801_ID			0x0108
#define STMPE801_NR_INTERNAL_IRQS	1

#define STMPE801_REG_CHIP_ID		0x00
#define STMPE801_REG_VERSION_ID		0x02
#define STMPE801_REG_SYS_CTRL		0x04
#define STMPE801_REG_GPIO_INT_EN	0x08
#define STMPE801_REG_GPIO_INT_STA	0x09
#define STMPE801_REG_GPIO_MP_STA	0x10
#define STMPE801_REG_GPIO_SET_PIN	0x11
#define STMPE801_REG_GPIO_DIR		0x12

/*
 * STMPE811
 */
#define STMPE811_ID			0x0811

#define STMPE811_IRQ_TOUCH_DET		0
#define STMPE811_IRQ_FIFO_TH		1
#define STMPE811_IRQ_FIFO_OFLOW		2
#define STMPE811_IRQ_FIFO_FULL		3
#define STMPE811_IRQ_FIFO_EMPTY		4
#define STMPE811_IRQ_TEMP_SENS		5
#define STMPE811_IRQ_ADC		6
#define STMPE811_IRQ_GPIOC		7
#define STMPE811_NR_INTERNAL_IRQS	8

#define STMPE811_REG_CHIP_ID		0x00
#define STMPE811_REG_SYS_CTRL		0x03
#define STMPE811_REG_SYS_CTRL2		0x04
#define STMPE811_REG_SPI_CFG		0x08
#define STMPE811_REG_INT_CTRL		0x09
#define STMPE811_REG_INT_EN		0x0A
#define STMPE811_REG_INT_STA		0x0B
#define STMPE811_REG_GPIO_INT_EN	0x0C
#define STMPE811_REG_GPIO_INT_STA	0x0D
#define STMPE811_REG_GPIO_SET_PIN	0x10
#define STMPE811_REG_GPIO_CLR_PIN	0x11
#define STMPE811_REG_GPIO_MP_STA	0x12
#define STMPE811_REG_GPIO_DIR		0x13
#define STMPE811_REG_GPIO_ED		0x14
#define STMPE811_REG_GPIO_RE		0x15
#define STMPE811_REG_GPIO_FE		0x16
#define STMPE811_REG_GPIO_AF		0x17

#define STMPE811_SYS_CTRL_RESET		(1 << 1)

#define STMPE811_SYS_CTRL2_ADC_OFF	(1 << 0)
#define STMPE811_SYS_CTRL2_TSC_OFF	(1 << 1)
#define STMPE811_SYS_CTRL2_GPIO_OFF	(1 << 2)
#define STMPE811_SYS_CTRL2_TS_OFF	(1 << 3)

/*
 * STMPE1600
 */
#define STMPE1600_ID			0x0016
#define STMPE1600_NR_INTERNAL_IRQS	16

#define STMPE1600_REG_CHIP_ID		0x00
#define STMPE1600_REG_SYS_CTRL		0x03
#define STMPE1600_REG_IEGPIOR_LSB	0x08
#define STMPE1600_REG_IEGPIOR_MSB	0x09
#define STMPE1600_REG_ISGPIOR_LSB	0x0A
#define STMPE1600_REG_ISGPIOR_MSB	0x0B
#define STMPE1600_REG_GPMR_LSB		0x10
#define STMPE1600_REG_GPMR_MSB		0x11
#define STMPE1600_REG_GPSR_LSB		0x12
#define STMPE1600_REG_GPSR_MSB		0x13
#define STMPE1600_REG_GPDR_LSB		0x14
#define STMPE1600_REG_GPDR_MSB		0x15
#define STMPE1600_REG_GPPIR_LSB		0x16
#define STMPE1600_REG_GPPIR_MSB		0x17

/*
 * STMPE1601
 */

#define STMPE1601_IRQ_GPIOC		8
#define STMPE1601_IRQ_PWM3		7
#define STMPE1601_IRQ_PWM2		6
#define STMPE1601_IRQ_PWM1		5
#define STMPE1601_IRQ_PWM0		4
#define STMPE1601_IRQ_KEYPAD_OVER	2
#define STMPE1601_IRQ_KEYPAD		1
#define STMPE1601_IRQ_WAKEUP		0
#define STMPE1601_NR_INTERNAL_IRQS	9

#define STMPE1601_REG_SYS_CTRL			0x02
#define STMPE1601_REG_SYS_CTRL2			0x03
#define STMPE1601_REG_ICR_MSB			0x10
#define STMPE1601_REG_ICR_LSB			0x11
#define STMPE1601_REG_IER_MSB			0x12
#define STMPE1601_REG_IER_LSB			0x13
#define STMPE1601_REG_ISR_MSB			0x14
#define STMPE1601_REG_ISR_LSB			0x15
#define STMPE1601_REG_INT_EN_GPIO_MASK_MSB	0x16
#define STMPE1601_REG_INT_EN_GPIO_MASK_LSB	0x17
#define STMPE1601_REG_INT_STA_GPIO_MSB		0x18
#define STMPE1601_REG_INT_STA_GPIO_LSB		0x19
#define STMPE1601_REG_CHIP_ID			0x80
#define STMPE1601_REG_GPIO_SET_MSB		0x82
#define STMPE1601_REG_GPIO_SET_LSB		0x83
#define STMPE1601_REG_GPIO_CLR_MSB		0x84
#define STMPE1601_REG_GPIO_CLR_LSB		0x85
#define STMPE1601_REG_GPIO_MP_MSB		0x86
#define STMPE1601_REG_GPIO_MP_LSB		0x87
#define STMPE1601_REG_GPIO_SET_DIR_MSB		0x88
#define STMPE1601_REG_GPIO_SET_DIR_LSB		0x89
#define STMPE1601_REG_GPIO_ED_MSB		0x8A
#define STMPE1601_REG_GPIO_ED_LSB		0x8B
#define STMPE1601_REG_GPIO_RE_MSB		0x8C
#define STMPE1601_REG_GPIO_RE_LSB		0x8D
#define STMPE1601_REG_GPIO_FE_MSB		0x8E
#define STMPE1601_REG_GPIO_FE_LSB		0x8F
#define STMPE1601_REG_GPIO_PU_MSB		0x90
#define STMPE1601_REG_GPIO_PU_LSB		0x91
#define STMPE1601_REG_GPIO_AF_U_MSB		0x92

#define STMPE1601_SYS_CTRL_ENABLE_GPIO		(1 << 3)
#define STMPE1601_SYS_CTRL_ENABLE_KPC		(1 << 1)
#define STMPE1601_SYS_CTRL_ENABLE_SPWM		(1 << 0)

/* The 1601/2403 share the same masks */
#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK	(0x7)
#define STPME1601_AUTOSLEEP_ENABLE		(1 << 3)

/*
 * STMPE1801
 */
#define STMPE1801_ID			0xc110
#define STMPE1801_NR_INTERNAL_IRQS	5
#define STMPE1801_IRQ_KEYPAD_COMBI	4
#define STMPE1801_IRQ_GPIOC		3
#define STMPE1801_IRQ_KEYPAD_OVER	2
#define STMPE1801_IRQ_KEYPAD		1
#define STMPE1801_IRQ_WAKEUP		0

#define STMPE1801_REG_CHIP_ID			0x00
#define STMPE1801_REG_SYS_CTRL			0x02
#define STMPE1801_REG_INT_CTRL_LOW		0x04
#define STMPE1801_REG_INT_EN_MASK_LOW		0x06
#define STMPE1801_REG_INT_STA_LOW		0x08
#define STMPE1801_REG_INT_EN_GPIO_MASK_LOW	0x0A
#define STMPE1801_REG_INT_EN_GPIO_MASK_MID	0x0B
#define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH	0x0C
#define STMPE1801_REG_INT_STA_GPIO_LOW		0x0D
#define STMPE1801_REG_INT_STA_GPIO_MID		0x0E
#define STMPE1801_REG_INT_STA_GPIO_HIGH		0x0F
#define STMPE1801_REG_GPIO_SET_LOW		0x10
#define STMPE1801_REG_GPIO_SET_MID		0x11
#define STMPE1801_REG_GPIO_SET_HIGH		0x12
#define STMPE1801_REG_GPIO_CLR_LOW		0x13
#define STMPE1801_REG_GPIO_CLR_MID		0x14
#define STMPE1801_REG_GPIO_CLR_HIGH		0x15
#define STMPE1801_REG_GPIO_MP_LOW		0x16
#define STMPE1801_REG_GPIO_MP_MID		0x17
#define STMPE1801_REG_GPIO_MP_HIGH		0x18
#define STMPE1801_REG_GPIO_SET_DIR_LOW		0x19
#define STMPE1801_REG_GPIO_SET_DIR_MID		0x1A
#define STMPE1801_REG_GPIO_SET_DIR_HIGH		0x1B
#define STMPE1801_REG_GPIO_RE_LOW		0x1C
#define STMPE1801_REG_GPIO_RE_MID		0x1D
#define STMPE1801_REG_GPIO_RE_HIGH		0x1E
#define STMPE1801_REG_GPIO_FE_LOW		0x1F
#define STMPE1801_REG_GPIO_FE_MID		0x20
#define STMPE1801_REG_GPIO_FE_HIGH		0x21
#define STMPE1801_REG_GPIO_PULL_UP_LOW		0x22
#define STMPE1801_REG_GPIO_PULL_UP_MID		0x23
#define STMPE1801_REG_GPIO_PULL_UP_HIGH		0x24

#define STMPE1801_MSK_INT_EN_KPC		(1 << 1)
#define STMPE1801_MSK_INT_EN_GPIO		(1 << 3)

/*
 * STMPE24xx
 */

#define STMPE24XX_IRQ_GPIOC		8
#define STMPE24XX_IRQ_PWM2		7
#define STMPE24XX_IRQ_PWM1		6
#define STMPE24XX_IRQ_PWM0		5
#define STMPE24XX_IRQ_ROT_OVER		4
#define STMPE24XX_IRQ_ROT		3
#define STMPE24XX_IRQ_KEYPAD_OVER	2
#define STMPE24XX_IRQ_KEYPAD		1
#define STMPE24XX_IRQ_WAKEUP		0
#define STMPE24XX_NR_INTERNAL_IRQS	9

#define STMPE24XX_REG_SYS_CTRL		0x02
#define STMPE24XX_REG_SYS_CTRL2		0x03
#define STMPE24XX_REG_ICR_MSB		0x10
#define STMPE24XX_REG_ICR_LSB		0x11
#define STMPE24XX_REG_IER_MSB		0x12
#define STMPE24XX_REG_IER_LSB		0x13
#define STMPE24XX_REG_ISR_MSB		0x14
#define STMPE24XX_REG_ISR_LSB		0x15
#define STMPE24XX_REG_IEGPIOR_MSB	0x16
#define STMPE24XX_REG_IEGPIOR_CSB	0x17
#define STMPE24XX_REG_IEGPIOR_LSB	0x18
#define STMPE24XX_REG_ISGPIOR_MSB	0x19
#define STMPE24XX_REG_ISGPIOR_CSB	0x1A
#define STMPE24XX_REG_ISGPIOR_LSB	0x1B
#define STMPE24XX_REG_CHIP_ID		0x80
#define STMPE24XX_REG_GPSR_MSB		0x83
#define STMPE24XX_REG_GPSR_CSB		0x84
#define STMPE24XX_REG_GPSR_LSB		0x85
#define STMPE24XX_REG_GPCR_MSB		0x86
#define STMPE24XX_REG_GPCR_CSB		0x87
#define STMPE24XX_REG_GPCR_LSB		0x88
#define STMPE24XX_REG_GPDR_MSB		0x89
#define STMPE24XX_REG_GPDR_CSB		0x8A
#define STMPE24XX_REG_GPDR_LSB		0x8B
#define STMPE24XX_REG_GPEDR_MSB		0x8C
#define STMPE24XX_REG_GPEDR_CSB		0x8D
#define STMPE24XX_REG_GPEDR_LSB		0x8E
#define STMPE24XX_REG_GPRER_MSB		0x8F
#define STMPE24XX_REG_GPRER_CSB		0x90
#define STMPE24XX_REG_GPRER_LSB		0x91
#define STMPE24XX_REG_GPFER_MSB		0x92
#define STMPE24XX_REG_GPFER_CSB		0x93
#define STMPE24XX_REG_GPFER_LSB		0x94
#define STMPE24XX_REG_GPPUR_MSB		0x95
#define STMPE24XX_REG_GPPUR_CSB		0x96
#define STMPE24XX_REG_GPPUR_LSB		0x97
#define STMPE24XX_REG_GPPDR_MSB		0x98
#define STMPE24XX_REG_GPPDR_CSB		0x99
#define STMPE24XX_REG_GPPDR_LSB		0x9A
#define STMPE24XX_REG_GPAFR_U_MSB	0x9B
#define STMPE24XX_REG_GPMR_MSB		0xA2
#define STMPE24XX_REG_GPMR_CSB		0xA3
#define STMPE24XX_REG_GPMR_LSB		0xA4
#define STMPE24XX_SYS_CTRL_ENABLE_GPIO		(1 << 3)
#define STMPE24XX_SYSCON_ENABLE_PWM		(1 << 2)
#define STMPE24XX_SYS_CTRL_ENABLE_KPC		(1 << 1)
#define STMPE24XX_SYSCON_ENABLE_ROT		(1 << 0)

#endif
Commit	Line	Data
27e34995 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <[email protected]> for ST-Ericsson
	6	*/
	7
	8	#ifndef __STMPE_H
	9	#define __STMPE_H
	10
1a6e4b74 VK	11	#include <linux/device.h>
	12	#include <linux/mfd/core.h>
	13	#include <linux/mfd/stmpe.h>
	14	#include <linux/printk.h>
	15	#include <linux/types.h>
	16
	17	extern const struct dev_pm_ops stmpe_dev_pm_ops;
	18
27e34995 RV	19	#ifdef STMPE_DUMP_BYTES
	20	static inline void stmpe_dump_bytes(const char str, const void buf,
	21	size_t len)
	22	{
	23	print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
	24	}
	25	#else
	26	static inline void stmpe_dump_bytes(const char str, const void buf,
	27	size_t len)
	28	{
	29	}
	30	#endif
	31
	32	/**
	33	* struct stmpe_variant_block - information about block
	34	* @cell: base mfd cell
	35	* @irq: interrupt number to be added to each IORESOURCE_IRQ
	36	* in the cell
	37	* @block: block id; used for identification with platform data and for
	38	* enable and altfunc callbacks
	39	*/
	40	struct stmpe_variant_block {
6bbb3c4c	41	const struct mfd_cell *cell;
27e34995 RV	42	int irq;
	43	enum stmpe_block block;
	44	};
	45
	46	/**
	47	* struct stmpe_variant_info - variant-specific information
	48	* @name: part name
	49	* @id_val: content of CHIPID register
	50	* @id_mask: bits valid in CHIPID register for comparison with id_val
	51	* @num_gpios: number of GPIOS
	52	* @af_bits: number of bits used to specify the alternate function
4dcaa6b6	53	* @regs: variant specific registers.
27e34995 RV	54	* @blocks: list of blocks present on this device
	55	* @num_blocks: number of blocks present on this device
	56	* @num_irqs: number of internal IRQs available on this device
	57	* @enable: callback to enable the specified blocks.
	58	* Called with the I/O lock held.
	59	* @get_altfunc: callback to get the alternate function number for the
	60	* specific block
5981f4e6	61	* @enable_autosleep: callback to configure autosleep with specified timeout
27e34995 RV	62	*/
	63	struct stmpe_variant_info {
	64	const char *name;
	65	u16 id_val;
	66	u16 id_mask;
	67	int num_gpios;
	68	int af_bits;
	69	const u8 *regs;
	70	struct stmpe_variant_block *blocks;
	71	int num_blocks;
	72	int num_irqs;
	73	int (enable)(struct stmpe stmpe, unsigned int blocks, bool enable);
	74	int (get_altfunc)(struct stmpe stmpe, enum stmpe_block block);
5981f4e6	75	int (enable_autosleep)(struct stmpe stmpe, int autosleep_timeout);
27e34995 RV	76	};
27e34995 RV	77
1a6e4b74 VK	78	/**
	79	* struct stmpe_client_info - i2c or spi specific routines/info
	80	* @data: client specific data
	81	* @read_byte: read single byte
	82	* @write_byte: write single byte
	83	* @read_block: read block or multiple bytes
	84	* @write_block: write block or multiple bytes
	85	* @init: client init routine, called during probe
	86	*/
	87	struct stmpe_client_info {
	88	void *data;
	89	int irq;
	90	void *client;
	91	struct device *dev;
	92	int (read_byte)(struct stmpe stmpe, u8 reg);
	93	int (write_byte)(struct stmpe stmpe, u8 reg, u8 val);
	94	int (read_block)(struct stmpe stmpe, u8 reg, u8 len, u8 *values);
	95	int (write_block)(struct stmpe stmpe, u8 reg, u8 len,
	96	const u8 *values);
	97	void (init)(struct stmpe stmpe);
	98	};
	99
c00572bc	100	int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
1a6e4b74 VK	101	int stmpe_remove(struct stmpe *stmpe);
1a6e4b74 VK	102
27e34995 RV	103	#define STMPE_ICR_LSB_HIGH (1 << 2)
	104	#define STMPE_ICR_LSB_EDGE (1 << 1)
	105	#define STMPE_ICR_LSB_GIM (1 << 0)
	106
c4dd1ba3	107	#define STMPE_SYS_CTRL_RESET (1 << 7)
c16bee78 PC	108	#define STMPE_SYS_CTRL_INT_EN (1 << 2)
c16bee78 PC	109	#define STMPE_SYS_CTRL_INT_HI (1 << 0)
c4dd1ba3	110
7f7f4ea1 VK	111	/*
	112	* STMPE801
	113	*/
	114	#define STMPE801_ID 0x0108
	115	#define STMPE801_NR_INTERNAL_IRQS 1
	116
	117	#define STMPE801_REG_CHIP_ID 0x00
	118	#define STMPE801_REG_VERSION_ID 0x02
	119	#define STMPE801_REG_SYS_CTRL 0x04
	120	#define STMPE801_REG_GPIO_INT_EN 0x08
	121	#define STMPE801_REG_GPIO_INT_STA 0x09
	122	#define STMPE801_REG_GPIO_MP_STA 0x10
	123	#define STMPE801_REG_GPIO_SET_PIN 0x11
	124	#define STMPE801_REG_GPIO_DIR 0x12
	125
27e34995 RV	126	/*
	127	* STMPE811
	128	*/
c4dd1ba3	129	#define STMPE811_ID 0x0811
27e34995 RV	130
	131	#define STMPE811_IRQ_TOUCH_DET 0
	132	#define STMPE811_IRQ_FIFO_TH 1
	133	#define STMPE811_IRQ_FIFO_OFLOW 2
	134	#define STMPE811_IRQ_FIFO_FULL 3
	135	#define STMPE811_IRQ_FIFO_EMPTY 4
	136	#define STMPE811_IRQ_TEMP_SENS 5
	137	#define STMPE811_IRQ_ADC 6
	138	#define STMPE811_IRQ_GPIOC 7
	139	#define STMPE811_NR_INTERNAL_IRQS 8
	140
	141	#define STMPE811_REG_CHIP_ID 0x00
0f4be8cf	142	#define STMPE811_REG_SYS_CTRL 0x03
27e34995	143	#define STMPE811_REG_SYS_CTRL2 0x04
e789995d	144	#define STMPE811_REG_SPI_CFG 0x08
27e34995 RV	145	#define STMPE811_REG_INT_CTRL 0x09
	146	#define STMPE811_REG_INT_EN 0x0A
	147	#define STMPE811_REG_INT_STA 0x0B
	148	#define STMPE811_REG_GPIO_INT_EN 0x0C
	149	#define STMPE811_REG_GPIO_INT_STA 0x0D
	150	#define STMPE811_REG_GPIO_SET_PIN 0x10
	151	#define STMPE811_REG_GPIO_CLR_PIN 0x11
	152	#define STMPE811_REG_GPIO_MP_STA 0x12
	153	#define STMPE811_REG_GPIO_DIR 0x13
	154	#define STMPE811_REG_GPIO_ED 0x14
	155	#define STMPE811_REG_GPIO_RE 0x15
	156	#define STMPE811_REG_GPIO_FE 0x16
	157	#define STMPE811_REG_GPIO_AF 0x17
	158
c4dd1ba3 PC	159	#define STMPE811_SYS_CTRL_RESET (1 << 1)
c4dd1ba3 PC	160
27e34995 RV	161	#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
	162	#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
	163	#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
	164	#define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
	165
6bb9f0d9 PC	166	/*
	167	* STMPE1600
	168	*/
	169	#define STMPE1600_ID 0x0016
	170	#define STMPE1600_NR_INTERNAL_IRQS 16
	171
	172	#define STMPE1600_REG_CHIP_ID 0x00
	173	#define STMPE1600_REG_SYS_CTRL 0x03
	174	#define STMPE1600_REG_IEGPIOR_LSB 0x08
	175	#define STMPE1600_REG_IEGPIOR_MSB 0x09
	176	#define STMPE1600_REG_ISGPIOR_LSB 0x0A
	177	#define STMPE1600_REG_ISGPIOR_MSB 0x0B
	178	#define STMPE1600_REG_GPMR_LSB 0x10
	179	#define STMPE1600_REG_GPMR_MSB 0x11
	180	#define STMPE1600_REG_GPSR_LSB 0x12
	181	#define STMPE1600_REG_GPSR_MSB 0x13
	182	#define STMPE1600_REG_GPDR_LSB 0x14
	183	#define STMPE1600_REG_GPDR_MSB 0x15
	184	#define STMPE1600_REG_GPPIR_LSB 0x16
	185	#define STMPE1600_REG_GPPIR_MSB 0x17
	186
27e34995 RV	187	/*
	188	* STMPE1601
	189	*/
	190
	191	#define STMPE1601_IRQ_GPIOC 8
	192	#define STMPE1601_IRQ_PWM3 7
	193	#define STMPE1601_IRQ_PWM2 6
	194	#define STMPE1601_IRQ_PWM1 5
	195	#define STMPE1601_IRQ_PWM0 4
	196	#define STMPE1601_IRQ_KEYPAD_OVER 2
	197	#define STMPE1601_IRQ_KEYPAD 1
	198	#define STMPE1601_IRQ_WAKEUP 0
	199	#define STMPE1601_NR_INTERNAL_IRQS 9
	200
	201	#define STMPE1601_REG_SYS_CTRL 0x02
5981f4e6	202	#define STMPE1601_REG_SYS_CTRL2 0x03
897ac667	203	#define STMPE1601_REG_ICR_MSB 0x10
27e34995	204	#define STMPE1601_REG_ICR_LSB 0x11
897ac667	205	#define STMPE1601_REG_IER_MSB 0x12
27e34995 RV	206	#define STMPE1601_REG_IER_LSB 0x13
27e34995 RV	207	#define STMPE1601_REG_ISR_MSB 0x14
897ac667 PC	208	#define STMPE1601_REG_ISR_LSB 0x15
897ac667 PC	209	#define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
27e34995 RV	210	#define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
27e34995 RV	211	#define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
897ac667 PC	212	#define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
	213	#define STMPE1601_REG_CHIP_ID 0x80
	214	#define STMPE1601_REG_GPIO_SET_MSB 0x82
27e34995	215	#define STMPE1601_REG_GPIO_SET_LSB 0x83
897ac667	216	#define STMPE1601_REG_GPIO_CLR_MSB 0x84
27e34995	217	#define STMPE1601_REG_GPIO_CLR_LSB 0x85
897ac667 PC	218	#define STMPE1601_REG_GPIO_MP_MSB 0x86
	219	#define STMPE1601_REG_GPIO_MP_LSB 0x87
	220	#define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
27e34995 RV	221	#define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
27e34995 RV	222	#define STMPE1601_REG_GPIO_ED_MSB 0x8A
897ac667 PC	223	#define STMPE1601_REG_GPIO_ED_LSB 0x8B
897ac667 PC	224	#define STMPE1601_REG_GPIO_RE_MSB 0x8C
27e34995	225	#define STMPE1601_REG_GPIO_RE_LSB 0x8D
897ac667	226	#define STMPE1601_REG_GPIO_FE_MSB 0x8E
27e34995	227	#define STMPE1601_REG_GPIO_FE_LSB 0x8F
897ac667	228	#define STMPE1601_REG_GPIO_PU_MSB 0x90
80e1dd82	229	#define STMPE1601_REG_GPIO_PU_LSB 0x91
27e34995 RV	230	#define STMPE1601_REG_GPIO_AF_U_MSB 0x92
	231
	232	#define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
	233	#define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
b69d2ad6	234	#define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
27e34995	235
5981f4e6 SI	236	/* The 1601/2403 share the same masks */
	237	#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
	238	#define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
	239
230f13a5 JNG	240	/*
	241	* STMPE1801
	242	*/
	243	#define STMPE1801_ID 0xc110
	244	#define STMPE1801_NR_INTERNAL_IRQS 5
	245	#define STMPE1801_IRQ_KEYPAD_COMBI 4
	246	#define STMPE1801_IRQ_GPIOC 3
	247	#define STMPE1801_IRQ_KEYPAD_OVER 2
	248	#define STMPE1801_IRQ_KEYPAD 1
	249	#define STMPE1801_IRQ_WAKEUP 0
	250
	251	#define STMPE1801_REG_CHIP_ID 0x00
	252	#define STMPE1801_REG_SYS_CTRL 0x02
	253	#define STMPE1801_REG_INT_CTRL_LOW 0x04
	254	#define STMPE1801_REG_INT_EN_MASK_LOW 0x06
	255	#define STMPE1801_REG_INT_STA_LOW 0x08
	256	#define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
	257	#define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
	258	#define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
	259	#define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
	260	#define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
	261	#define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
	262	#define STMPE1801_REG_GPIO_SET_LOW 0x10
	263	#define STMPE1801_REG_GPIO_SET_MID 0x11
	264	#define STMPE1801_REG_GPIO_SET_HIGH 0x12
	265	#define STMPE1801_REG_GPIO_CLR_LOW 0x13
	266	#define STMPE1801_REG_GPIO_CLR_MID 0x14
	267	#define STMPE1801_REG_GPIO_CLR_HIGH 0x15
	268	#define STMPE1801_REG_GPIO_MP_LOW 0x16
	269	#define STMPE1801_REG_GPIO_MP_MID 0x17
	270	#define STMPE1801_REG_GPIO_MP_HIGH 0x18
	271	#define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
	272	#define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
	273	#define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
	274	#define STMPE1801_REG_GPIO_RE_LOW 0x1C
	275	#define STMPE1801_REG_GPIO_RE_MID 0x1D
	276	#define STMPE1801_REG_GPIO_RE_HIGH 0x1E
	277	#define STMPE1801_REG_GPIO_FE_LOW 0x1F
	278	#define STMPE1801_REG_GPIO_FE_MID 0x20
	279	#define STMPE1801_REG_GPIO_FE_HIGH 0x21
	280	#define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
	281	#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
	282	#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
	283
230f13a5 JNG	284	#define STMPE1801_MSK_INT_EN_KPC (1 << 1)
	285	#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
	286
27e34995 RV	287	/*
	288	* STMPE24xx
	289	*/
	290
	291	#define STMPE24XX_IRQ_GPIOC 8
	292	#define STMPE24XX_IRQ_PWM2 7
	293	#define STMPE24XX_IRQ_PWM1 6
	294	#define STMPE24XX_IRQ_PWM0 5
	295	#define STMPE24XX_IRQ_ROT_OVER 4
	296	#define STMPE24XX_IRQ_ROT 3
	297	#define STMPE24XX_IRQ_KEYPAD_OVER 2
	298	#define STMPE24XX_IRQ_KEYPAD 1
	299	#define STMPE24XX_IRQ_WAKEUP 0
	300	#define STMPE24XX_NR_INTERNAL_IRQS 9
	301
	302	#define STMPE24XX_REG_SYS_CTRL 0x02
0f4be8cf	303	#define STMPE24XX_REG_SYS_CTRL2 0x03
897ac667	304	#define STMPE24XX_REG_ICR_MSB 0x10
27e34995	305	#define STMPE24XX_REG_ICR_LSB 0x11
897ac667	306	#define STMPE24XX_REG_IER_MSB 0x12
27e34995 RV	307	#define STMPE24XX_REG_IER_LSB 0x13
27e34995 RV	308	#define STMPE24XX_REG_ISR_MSB 0x14
897ac667 PC	309	#define STMPE24XX_REG_ISR_LSB 0x15
	310	#define STMPE24XX_REG_IEGPIOR_MSB 0x16
	311	#define STMPE24XX_REG_IEGPIOR_CSB 0x17
27e34995 RV	312	#define STMPE24XX_REG_IEGPIOR_LSB 0x18
27e34995 RV	313	#define STMPE24XX_REG_ISGPIOR_MSB 0x19
897ac667 PC	314	#define STMPE24XX_REG_ISGPIOR_CSB 0x1A
	315	#define STMPE24XX_REG_ISGPIOR_LSB 0x1B
	316	#define STMPE24XX_REG_CHIP_ID 0x80
	317	#define STMPE24XX_REG_GPSR_MSB 0x83
	318	#define STMPE24XX_REG_GPSR_CSB 0x84
27e34995	319	#define STMPE24XX_REG_GPSR_LSB 0x85
897ac667 PC	320	#define STMPE24XX_REG_GPCR_MSB 0x86
897ac667 PC	321	#define STMPE24XX_REG_GPCR_CSB 0x87
27e34995	322	#define STMPE24XX_REG_GPCR_LSB 0x88
897ac667 PC	323	#define STMPE24XX_REG_GPDR_MSB 0x89
897ac667 PC	324	#define STMPE24XX_REG_GPDR_CSB 0x8A
27e34995 RV	325	#define STMPE24XX_REG_GPDR_LSB 0x8B
27e34995 RV	326	#define STMPE24XX_REG_GPEDR_MSB 0x8C
897ac667 PC	327	#define STMPE24XX_REG_GPEDR_CSB 0x8D
	328	#define STMPE24XX_REG_GPEDR_LSB 0x8E
	329	#define STMPE24XX_REG_GPRER_MSB 0x8F
	330	#define STMPE24XX_REG_GPRER_CSB 0x90
27e34995	331	#define STMPE24XX_REG_GPRER_LSB 0x91
897ac667 PC	332	#define STMPE24XX_REG_GPFER_MSB 0x92
897ac667 PC	333	#define STMPE24XX_REG_GPFER_CSB 0x93
27e34995	334	#define STMPE24XX_REG_GPFER_LSB 0x94
897ac667 PC	335	#define STMPE24XX_REG_GPPUR_MSB 0x95
897ac667 PC	336	#define STMPE24XX_REG_GPPUR_CSB 0x96
80e1dd82	337	#define STMPE24XX_REG_GPPUR_LSB 0x97
897ac667 PC	338	#define STMPE24XX_REG_GPPDR_MSB 0x98
	339	#define STMPE24XX_REG_GPPDR_CSB 0x99
	340	#define STMPE24XX_REG_GPPDR_LSB 0x9A
27e34995	341	#define STMPE24XX_REG_GPAFR_U_MSB 0x9B
897ac667 PC	342	#define STMPE24XX_REG_GPMR_MSB 0xA2
	343	#define STMPE24XX_REG_GPMR_CSB 0xA3
	344	#define STMPE24XX_REG_GPMR_LSB 0xA4
27e34995 RV	345	#define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
	346	#define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
	347	#define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
	348	#define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)
	349
	350	#endif