[linux.git] / include / linux / mbus.h

/*
 * Marvell MBUS common definitions.
 *
 * Copyright (C) 2008 Marvell Semiconductor
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __LINUX_MBUS_H
#define __LINUX_MBUS_H

struct resource;

struct mbus_dram_target_info
{
	/*
	 * The 4-bit MBUS target ID of the DRAM controller.
	 */
	u8		mbus_dram_target_id;

	/*
	 * The base address, size, and MBUS attribute ID for each
	 * of the possible DRAM chip selects.  Peripherals are
	 * required to support at least 4 decode windows.
	 */
	int		num_cs;
	struct mbus_dram_window {
		u8	cs_index;
		u8	mbus_attr;
		u32	base;
		u32	size;
	} cs[4];
};

/* Flags for PCI/PCIe address decoding regions */
#define MVEBU_MBUS_PCI_IO  0x1
#define MVEBU_MBUS_PCI_MEM 0x2
#define MVEBU_MBUS_PCI_WA  0x3

/*
 * Magic value that explicits that we don't need a remapping-capable
 * address decoding window.
 */
#define MVEBU_MBUS_NO_REMAP (0xffffffff)

/* Maximum size of a mbus window name */
#define MVEBU_MBUS_MAX_WINNAME_SZ 32

/*
 * The Marvell mbus is to be found only on SOCs from the Orion family
 * at the moment.  Provide a dummy stub for other architectures.
 */
#ifdef CONFIG_PLAT_ORION
extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
#else
static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
{
	return NULL;
}
static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
{
	return NULL;
}
#endif

int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
			       u8 *attr);
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
				      unsigned int attribute,
				      phys_addr_t base, size_t size,
				      phys_addr_t remap);
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
				phys_addr_t base, size_t size);
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
		    size_t mbus_size, phys_addr_t sdram_phys_base,
		    size_t sdram_size);
int mvebu_mbus_dt_init(bool is_coherent);

#endif /* __LINUX_MBUS_H */
Commit	Line	Data
abc848c1 LB	1	/*
	2	* Marvell MBUS common definitions.
	3	*
	4	* Copyright (C) 2008 Marvell Semiconductor
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#ifndef __LINUX_MBUS_H
	12	#define __LINUX_MBUS_H
	13
79d94683 EG	14	struct resource;
79d94683 EG	15
abc848c1 LB	16	struct mbus_dram_target_info
	17	{
	18	/*
	19	* The 4-bit MBUS target ID of the DRAM controller.
	20	*/
	21	u8 mbus_dram_target_id;
	22
	23	/*
	24	* The base address, size, and MBUS attribute ID for each
	25	* of the possible DRAM chip selects. Peripherals are
	26	* required to support at least 4 decode windows.
	27	*/
	28	int num_cs;
	29	struct mbus_dram_window {
	30	u8 cs_index;
	31	u8 mbus_attr;
	32	u32 base;
	33	u32 size;
	34	} cs[4];
	35	};
	36
fddddb52 TP	37	/* Flags for PCI/PCIe address decoding regions */
	38	#define MVEBU_MBUS_PCI_IO 0x1
	39	#define MVEBU_MBUS_PCI_MEM 0x2
	40	#define MVEBU_MBUS_PCI_WA 0x3
	41
	42	/*
	43	* Magic value that explicits that we don't need a remapping-capable
	44	* address decoding window.
	45	*/
	46	#define MVEBU_MBUS_NO_REMAP (0xffffffff)
	47
95b80e0a TP	48	/* Maximum size of a mbus window name */
	49	#define MVEBU_MBUS_MAX_WINNAME_SZ 32
	50
63a9332b AL	51	/*
	52	* The Marvell mbus is to be found only on SOCs from the Orion family
	53	* at the moment. Provide a dummy stub for other architectures.
	54	*/
	55	#ifdef CONFIG_PLAT_ORION
	56	extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
bfa1ce5f	57	extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
63a9332b AL	58	#else
	59	static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
	60	{
	61	return NULL;
	62	}
bfa1ce5f TP	63	static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
	64	{
	65	return NULL;
	66	}
63a9332b	67	#endif
fddddb52	68
fce7b5ae	69	int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
79d94683 EG	70	void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
79d94683 EG	71	void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
f2900ace MW	72	int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 target, u8 attr);
	73	int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 size, u8 target,
	74	u8 *attr);
6a63b098 TP	75	int mvebu_mbus_add_window_remap_by_id(unsigned int target,
	76	unsigned int attribute,
	77	phys_addr_t base, size_t size,
	78	phys_addr_t remap);
6a63b098 TP	79	int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
6a63b098 TP	80	phys_addr_t base, size_t size);
fddddb52 TP	81	int mvebu_mbus_del_window(phys_addr_t base, size_t size);
	82	int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
	83	size_t mbus_size, phys_addr_t sdram_phys_base,
	84	size_t sdram_size);
5686a1e5	85	int mvebu_mbus_dt_init(bool is_coherent);
fddddb52 TP	86
fddddb52 TP	87	#endif /* __LINUX_MBUS_H */