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Linux 6.14-rc3
[linux.git] / sound / pci / rme96.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
4 * interfaces
5 *
6 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 *
8 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
9 * code.
1da177e4
LT		 10 */
11
1da177e4
LT		 12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/pci.h>
65a77217 16#include <linux/module.h>
a8cc2099 17#include <linux/vmalloc.h>
6cbbfe1c 18#include <linux/io.h>
1da177e4
LT		 19
20#include <sound/core.h>
21#include <sound/info.h>
22#include <sound/control.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/asoundef.h>
26#include <sound/initval.h>
27
1da177e4
LT		 28/* note, two last pcis should be equal, it is not a bug */
29
30MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
31MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
32 "Digi96/8 PAD");
33MODULE_LICENSE("GPL");
1da177e4
LT		 34
35static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
36static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 37static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 38
39module_param_array(index, int, NULL, 0444);
40MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
41module_param_array(id, charp, NULL, 0444);
42MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
43module_param_array(enable, bool, NULL, 0444);
44MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
45
46/*
47 * Defines for RME Digi96 series, from internal RME reference documents
48 * dated 12.01.00
49 */
50
51#define RME96_SPDIF_NCHANNELS 2
52
53/* Playback and capture buffer size */
54#define RME96_BUFFER_SIZE 0x10000
55
56/* IO area size */
57#define RME96_IO_SIZE 0x60000
58
59/* IO area offsets */
60#define RME96_IO_PLAY_BUFFER 0x0
61#define RME96_IO_REC_BUFFER 0x10000
62#define RME96_IO_CONTROL_REGISTER 0x20000
63#define RME96_IO_ADDITIONAL_REG 0x20004
64#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
65#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
66#define RME96_IO_SET_PLAY_POS 0x40000
67#define RME96_IO_RESET_PLAY_POS 0x4FFFC
68#define RME96_IO_SET_REC_POS 0x50000
69#define RME96_IO_RESET_REC_POS 0x5FFFC
70#define RME96_IO_GET_PLAY_POS 0x20000
71#define RME96_IO_GET_REC_POS 0x30000
72
73/* Write control register bits */
74#define RME96_WCR_START (1 << 0)
75#define RME96_WCR_START_2 (1 << 1)
76#define RME96_WCR_GAIN_0 (1 << 2)
77#define RME96_WCR_GAIN_1 (1 << 3)
78#define RME96_WCR_MODE24 (1 << 4)
79#define RME96_WCR_MODE24_2 (1 << 5)
80#define RME96_WCR_BM (1 << 6)
81#define RME96_WCR_BM_2 (1 << 7)
82#define RME96_WCR_ADAT (1 << 8)
83#define RME96_WCR_FREQ_0 (1 << 9)
84#define RME96_WCR_FREQ_1 (1 << 10)
85#define RME96_WCR_DS (1 << 11)
86#define RME96_WCR_PRO (1 << 12)
87#define RME96_WCR_EMP (1 << 13)
88#define RME96_WCR_SEL (1 << 14)
89#define RME96_WCR_MASTER (1 << 15)
90#define RME96_WCR_PD (1 << 16)
91#define RME96_WCR_INP_0 (1 << 17)
92#define RME96_WCR_INP_1 (1 << 18)
93#define RME96_WCR_THRU_0 (1 << 19)
94#define RME96_WCR_THRU_1 (1 << 20)
95#define RME96_WCR_THRU_2 (1 << 21)
96#define RME96_WCR_THRU_3 (1 << 22)
97#define RME96_WCR_THRU_4 (1 << 23)
98#define RME96_WCR_THRU_5 (1 << 24)
99#define RME96_WCR_THRU_6 (1 << 25)
100#define RME96_WCR_THRU_7 (1 << 26)
101#define RME96_WCR_DOLBY (1 << 27)
102#define RME96_WCR_MONITOR_0 (1 << 28)
103#define RME96_WCR_MONITOR_1 (1 << 29)
104#define RME96_WCR_ISEL (1 << 30)
105#define RME96_WCR_IDIS (1 << 31)
106
107#define RME96_WCR_BITPOS_GAIN_0 2
108#define RME96_WCR_BITPOS_GAIN_1 3
109#define RME96_WCR_BITPOS_FREQ_0 9
110#define RME96_WCR_BITPOS_FREQ_1 10
111#define RME96_WCR_BITPOS_INP_0 17
112#define RME96_WCR_BITPOS_INP_1 18
113#define RME96_WCR_BITPOS_MONITOR_0 28
114#define RME96_WCR_BITPOS_MONITOR_1 29
115
116/* Read control register bits */
117#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
118#define RME96_RCR_IRQ_2 (1 << 16)
119#define RME96_RCR_T_OUT (1 << 17)
120#define RME96_RCR_DEV_ID_0 (1 << 21)
121#define RME96_RCR_DEV_ID_1 (1 << 22)
122#define RME96_RCR_LOCK (1 << 23)
123#define RME96_RCR_VERF (1 << 26)
124#define RME96_RCR_F0 (1 << 27)
125#define RME96_RCR_F1 (1 << 28)
126#define RME96_RCR_F2 (1 << 29)
127#define RME96_RCR_AUTOSYNC (1 << 30)
128#define RME96_RCR_IRQ (1 << 31)
129
130#define RME96_RCR_BITPOS_F0 27
131#define RME96_RCR_BITPOS_F1 28
132#define RME96_RCR_BITPOS_F2 29
133
25985edc 134/* Additional register bits */
1da177e4
LT		 135#define RME96_AR_WSEL (1 << 0)
136#define RME96_AR_ANALOG (1 << 1)
137#define RME96_AR_FREQPAD_0 (1 << 2)
138#define RME96_AR_FREQPAD_1 (1 << 3)
139#define RME96_AR_FREQPAD_2 (1 << 4)
140#define RME96_AR_PD2 (1 << 5)
141#define RME96_AR_DAC_EN (1 << 6)
142#define RME96_AR_CLATCH (1 << 7)
143#define RME96_AR_CCLK (1 << 8)
144#define RME96_AR_CDATA (1 << 9)
145
146#define RME96_AR_BITPOS_F0 2
147#define RME96_AR_BITPOS_F1 3
148#define RME96_AR_BITPOS_F2 4
149
150/* Monitor tracks */
151#define RME96_MONITOR_TRACKS_1_2 0
152#define RME96_MONITOR_TRACKS_3_4 1
153#define RME96_MONITOR_TRACKS_5_6 2
154#define RME96_MONITOR_TRACKS_7_8 3
155
156/* Attenuation */
157#define RME96_ATTENUATION_0 0
158#define RME96_ATTENUATION_6 1
159#define RME96_ATTENUATION_12 2
160#define RME96_ATTENUATION_18 3
161
162/* Input types */
163#define RME96_INPUT_OPTICAL 0
164#define RME96_INPUT_COAXIAL 1
165#define RME96_INPUT_INTERNAL 2
166#define RME96_INPUT_XLR 3
167#define RME96_INPUT_ANALOG 4
168
169/* Clock modes */
170#define RME96_CLOCKMODE_SLAVE 0
171#define RME96_CLOCKMODE_MASTER 1
172#define RME96_CLOCKMODE_WORDCLOCK 2
173
174/* Block sizes in bytes */
175#define RME96_SMALL_BLOCK_SIZE 2048
176#define RME96_LARGE_BLOCK_SIZE 8192
177
178/* Volume control */
179#define RME96_AD1852_VOL_BITS 14
180#define RME96_AD1855_VOL_BITS 10
181
b892ca1c
KP		 182/* Defines for snd_rme96_trigger */
183#define RME96_TB_START_PLAYBACK 1
184#define RME96_TB_START_CAPTURE 2
185#define RME96_TB_STOP_PLAYBACK 4
186#define RME96_TB_STOP_CAPTURE 8
187#define RME96_TB_RESET_PLAYPOS 16
188#define RME96_TB_RESET_CAPTUREPOS 32
189#define RME96_TB_CLEAR_PLAYBACK_IRQ 64
190#define RME96_TB_CLEAR_CAPTURE_IRQ 128
191#define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
192#define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
193#define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
194 | RME96_RESUME_CAPTURE)
195#define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
196 | RME96_TB_RESET_PLAYPOS)
197#define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
198 | RME96_TB_RESET_CAPTUREPOS)
199#define RME96_START_BOTH (RME96_START_PLAYBACK \
200 | RME96_START_CAPTURE)
201#define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
202 | RME96_TB_CLEAR_PLAYBACK_IRQ)
203#define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
204 | RME96_TB_CLEAR_CAPTURE_IRQ)
205#define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
206 | RME96_STOP_CAPTURE)
1da177e4 207
a3aefd88 208struct rme96 {
1da177e4
LT		 209 spinlock_t lock;
210 int irq;
211 unsigned long port;
212 void __iomem *iobase;
213
214 u32 wcreg; /* cached write control register value */
215 u32 wcreg_spdif; /* S/PDIF setup */
216 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
217 u32 rcreg; /* cached read control register value */
218 u32 areg; /* cached additional register value */
219 u16 vol[2]; /* cached volume of analog output */
220
221 u8 rev; /* card revision number */
222
528ba522
KP		 223 u32 playback_pointer;
224 u32 capture_pointer;
225 void *playback_suspend_buffer;
226 void *capture_suspend_buffer;
528ba522 227
a3aefd88
TI		 228 struct snd_pcm_substream *playback_substream;
229 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 230
231 int playback_frlog; /* log2 of framesize */
232 int capture_frlog;
233
234 size_t playback_periodsize; /* in bytes, zero if not used */
235 size_t capture_periodsize; /* in bytes, zero if not used */
236
a3aefd88
TI		 237 struct snd_card *card;
238 struct snd_pcm *spdif_pcm;
239 struct snd_pcm *adat_pcm;
1da177e4 240 struct pci_dev *pci;
a3aefd88
TI		 241 struct snd_kcontrol *spdif_ctl;
242};
1da177e4 243
9baa3c34 244static const struct pci_device_id snd_rme96_ids[] = {
28d27aae
JP		 245 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
246 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
247 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
248 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
1da177e4
LT		 249 { 0, }
250};
251
252MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
253
254#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
255#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
8b7fc421
RD		 256#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
257#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
258 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
1da177e4 259#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
8b7fc421
RD		 260#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
261 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
1da177e4
LT		 262#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
263
264static int
a3aefd88 265snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 266
267static int
a3aefd88 268snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 269
270static int
a3aefd88 271snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 272 int cmd);
273
274static int
a3aefd88 275snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 276 int cmd);
277
278static snd_pcm_uframes_t
a3aefd88 279snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
1da177e4
LT		 280
281static snd_pcm_uframes_t
a3aefd88 282snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
1da177e4 283
e23e7a14 284static void snd_rme96_proc_init(struct rme96 *rme96);
1da177e4
LT		 285
286static int
a3aefd88
TI		 287snd_rme96_create_switches(struct snd_card *card,
288 struct rme96 *rme96);
1da177e4
LT		 289
290static int
a3aefd88 291snd_rme96_getinputtype(struct rme96 *rme96);
1da177e4
LT		 292
293static inline unsigned int
a3aefd88 294snd_rme96_playback_ptr(struct rme96 *rme96)
1da177e4
LT		 295{
296 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
297 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
298}
299
300static inline unsigned int
a3aefd88 301snd_rme96_capture_ptr(struct rme96 *rme96)
1da177e4
LT		 302{
303 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
304 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
305}
306
1da177e4 307static int
a3aefd88 308snd_rme96_playback_silence(struct snd_pcm_substream *substream,
53945f5b 309 int channel, unsigned long pos, unsigned long count)
1da177e4 310{
a3aefd88 311 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
53945f5b 312
1da177e4
LT		 313 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
314 0, count);
315 return 0;
316}
317
318static int
a3aefd88 319snd_rme96_playback_copy(struct snd_pcm_substream *substream,
53945f5b 320 int channel, unsigned long pos,
c3abdf06 321 struct iov_iter *src, unsigned long count)
1da177e4 322{
a3aefd88 323 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
53945f5b 324
1b2ff639
TI		 325 if (copy_from_iter_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
326 count, src) != count)
327 return -EFAULT;
328 return 0;
53945f5b
TI		 329}
330
1da177e4 331static int
a3aefd88 332snd_rme96_capture_copy(struct snd_pcm_substream *substream,
53945f5b 333 int channel, unsigned long pos,
c3abdf06 334 struct iov_iter *dst, unsigned long count)
1da177e4 335{
a3aefd88 336 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
53945f5b 337
1b2ff639
TI		 338 if (copy_to_iter_fromio(rme96->iobase + RME96_IO_REC_BUFFER + pos,
339 count, dst) != count)
340 return -EFAULT;
341 return 0;
1da177e4
LT		 342}
343
344/*
7f927fcc 345 * Digital output capabilities (S/PDIF)
1da177e4 346 */
dee49895 347static const struct snd_pcm_hardware snd_rme96_playback_spdif_info =
1da177e4
LT		 348{
349 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
350 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 351 SNDRV_PCM_INFO_SYNC_START |
528ba522 352 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 353 SNDRV_PCM_INFO_INTERLEAVED |
354 SNDRV_PCM_INFO_PAUSE),
355 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
356 SNDRV_PCM_FMTBIT_S32_LE),
357 .rates = (SNDRV_PCM_RATE_32000 |
358 SNDRV_PCM_RATE_44100 |
359 SNDRV_PCM_RATE_48000 |
360 SNDRV_PCM_RATE_64000 |
361 SNDRV_PCM_RATE_88200 |
362 SNDRV_PCM_RATE_96000),
363 .rate_min = 32000,
364 .rate_max = 96000,
365 .channels_min = 2,
366 .channels_max = 2,
367 .buffer_bytes_max = RME96_BUFFER_SIZE,
368 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
369 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
370 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
371 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
372 .fifo_size = 0,
373};
374
375/*
7f927fcc 376 * Digital input capabilities (S/PDIF)
1da177e4 377 */
dee49895 378static const struct snd_pcm_hardware snd_rme96_capture_spdif_info =
1da177e4
LT		 379{
380 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
381 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 382 SNDRV_PCM_INFO_SYNC_START |
528ba522 383 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 384 SNDRV_PCM_INFO_INTERLEAVED |
385 SNDRV_PCM_INFO_PAUSE),
386 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
387 SNDRV_PCM_FMTBIT_S32_LE),
388 .rates = (SNDRV_PCM_RATE_32000 |
389 SNDRV_PCM_RATE_44100 |
390 SNDRV_PCM_RATE_48000 |
391 SNDRV_PCM_RATE_64000 |
392 SNDRV_PCM_RATE_88200 |
393 SNDRV_PCM_RATE_96000),
394 .rate_min = 32000,
395 .rate_max = 96000,
396 .channels_min = 2,
397 .channels_max = 2,
398 .buffer_bytes_max = RME96_BUFFER_SIZE,
399 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
400 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
401 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
402 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
403 .fifo_size = 0,
404};
405
406/*
7f927fcc 407 * Digital output capabilities (ADAT)
1da177e4 408 */
dee49895 409static const struct snd_pcm_hardware snd_rme96_playback_adat_info =
1da177e4
LT		 410{
411 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
412 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 413 SNDRV_PCM_INFO_SYNC_START |
528ba522 414 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 415 SNDRV_PCM_INFO_INTERLEAVED |
416 SNDRV_PCM_INFO_PAUSE),
417 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
418 SNDRV_PCM_FMTBIT_S32_LE),
419 .rates = (SNDRV_PCM_RATE_44100 |
420 SNDRV_PCM_RATE_48000),
421 .rate_min = 44100,
422 .rate_max = 48000,
423 .channels_min = 8,
424 .channels_max = 8,
425 .buffer_bytes_max = RME96_BUFFER_SIZE,
426 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
427 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
428 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
429 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
430 .fifo_size = 0,
431};
432
433/*
7f927fcc 434 * Digital input capabilities (ADAT)
1da177e4 435 */
dee49895 436static const struct snd_pcm_hardware snd_rme96_capture_adat_info =
1da177e4
LT		 437{
438 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
439 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 440 SNDRV_PCM_INFO_SYNC_START |
528ba522 441 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 442 SNDRV_PCM_INFO_INTERLEAVED |
443 SNDRV_PCM_INFO_PAUSE),
444 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
445 SNDRV_PCM_FMTBIT_S32_LE),
446 .rates = (SNDRV_PCM_RATE_44100 |
447 SNDRV_PCM_RATE_48000),
448 .rate_min = 44100,
449 .rate_max = 48000,
450 .channels_min = 8,
451 .channels_max = 8,
452 .buffer_bytes_max = RME96_BUFFER_SIZE,
453 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
454 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
455 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
456 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
457 .fifo_size = 0,
458};
459
460/*
461 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
462 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
463 * on the falling edge of CCLK and be stable on the rising edge. The rising
464 * edge of CLATCH after the last data bit clocks in the whole data word.
465 * A fast processor could probably drive the SPI interface faster than the
466 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
467 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
468 *
469 * NOTE: increased delay from 1 to 10, since there where problems setting
470 * the volume.
471 */
472static void
a3aefd88 473snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
1da177e4
LT		 474{
475 int i;
476
477 for (i = 0; i < 16; i++) {
478 if (val & 0x8000) {
479 rme96->areg |= RME96_AR_CDATA;
480 } else {
481 rme96->areg &= ~RME96_AR_CDATA;
482 }
483 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
484 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
485 udelay(10);
486 rme96->areg |= RME96_AR_CCLK;
487 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
488 udelay(10);
489 val <<= 1;
490 }
491 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
492 rme96->areg |= RME96_AR_CLATCH;
493 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
494 udelay(10);
495 rme96->areg &= ~RME96_AR_CLATCH;
496 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
497}
498
499static void
a3aefd88 500snd_rme96_apply_dac_volume(struct rme96 *rme96)
1da177e4
LT		 501{
502 if (RME96_DAC_IS_1852(rme96)) {
503 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
504 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
505 } else if (RME96_DAC_IS_1855(rme96)) {
506 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
507 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
508 }
509}
510
511static void
a3aefd88 512snd_rme96_reset_dac(struct rme96 *rme96)
1da177e4
LT		 513{
514 writel(rme96->wcreg | RME96_WCR_PD,
515 rme96->iobase + RME96_IO_CONTROL_REGISTER);
516 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
517}
518
519static int
a3aefd88 520snd_rme96_getmontracks(struct rme96 *rme96)
1da177e4
LT		 521{
522 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
523 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
524}
525
526static int
a3aefd88 527snd_rme96_setmontracks(struct rme96 *rme96,
1da177e4
LT		 528 int montracks)
529{
530 if (montracks & 1) {
531 rme96->wcreg |= RME96_WCR_MONITOR_0;
532 } else {
533 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
534 }
535 if (montracks & 2) {
536 rme96->wcreg |= RME96_WCR_MONITOR_1;
537 } else {
538 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
539 }
540 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
541 return 0;
542}
543
544static int
a3aefd88 545snd_rme96_getattenuation(struct rme96 *rme96)
1da177e4
LT		 546{
547 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
548 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
549}
550
551static int
a3aefd88 552snd_rme96_setattenuation(struct rme96 *rme96,
1da177e4
LT		 553 int attenuation)
554{
555 switch (attenuation) {
556 case 0:
557 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
558 ~RME96_WCR_GAIN_1;
559 break;
560 case 1:
561 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
562 ~RME96_WCR_GAIN_1;
563 break;
564 case 2:
565 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
566 RME96_WCR_GAIN_1;
567 break;
568 case 3:
569 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
570 RME96_WCR_GAIN_1;
571 break;
572 default:
573 return -EINVAL;
574 }
575 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
576 return 0;
577}
578
579static int
a3aefd88 580snd_rme96_capture_getrate(struct rme96 *rme96,
1da177e4
LT		 581 int *is_adat)
582{
583 int n, rate;
584
585 *is_adat = 0;
586 if (rme96->areg & RME96_AR_ANALOG) {
587 /* Analog input, overrides S/PDIF setting */
588 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
589 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
590 switch (n) {
591 case 1:
592 rate = 32000;
593 break;
594 case 2:
595 rate = 44100;
596 break;
597 case 3:
598 rate = 48000;
599 break;
600 default:
601 return -1;
602 }
603 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
604 }
605
606 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
607 if (rme96->rcreg & RME96_RCR_LOCK) {
608 /* ADAT rate */
609 *is_adat = 1;
610 if (rme96->rcreg & RME96_RCR_T_OUT) {
611 return 48000;
612 }
613 return 44100;
614 }
615
616 if (rme96->rcreg & RME96_RCR_VERF) {
617 return -1;
618 }
619
620 /* S/PDIF rate */
621 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
622 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
623 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
624
625 switch (n) {
626 case 0:
627 if (rme96->rcreg & RME96_RCR_T_OUT) {
628 return 64000;
629 }
630 return -1;
631 case 3: return 96000;
632 case 4: return 88200;
633 case 5: return 48000;
634 case 6: return 44100;
635 case 7: return 32000;
636 default:
637 break;
638 }
639 return -1;
640}
641
642static int
a3aefd88 643snd_rme96_playback_getrate(struct rme96 *rme96)
1da177e4
LT		 644{
645 int rate, dummy;
646
647 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
da8eedb1
TI		 648 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
649 rate = snd_rme96_capture_getrate(rme96, &dummy);
650 if (rate > 0) {
651 /* slave clock */
652 return rate;
653 }
1da177e4 654 }
da8eedb1 655
1da177e4
LT		 656 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
657 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
658 switch (rate) {
659 case 1:
660 rate = 32000;
661 break;
662 case 2:
663 rate = 44100;
664 break;
665 case 3:
666 rate = 48000;
667 break;
668 default:
669 return -1;
670 }
671 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
672}
673
674static int
a3aefd88 675snd_rme96_playback_setrate(struct rme96 *rme96,
1da177e4
LT		 676 int rate)
677{
678 int ds;
679
680 ds = rme96->wcreg & RME96_WCR_DS;
681 switch (rate) {
682 case 32000:
683 rme96->wcreg &= ~RME96_WCR_DS;
684 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
685 ~RME96_WCR_FREQ_1;
686 break;
687 case 44100:
688 rme96->wcreg &= ~RME96_WCR_DS;
689 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
690 ~RME96_WCR_FREQ_0;
691 break;
692 case 48000:
693 rme96->wcreg &= ~RME96_WCR_DS;
694 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
695 RME96_WCR_FREQ_1;
696 break;
697 case 64000:
698 rme96->wcreg |= RME96_WCR_DS;
699 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
700 ~RME96_WCR_FREQ_1;
701 break;
702 case 88200:
703 rme96->wcreg |= RME96_WCR_DS;
704 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
705 ~RME96_WCR_FREQ_0;
706 break;
707 case 96000:
708 rme96->wcreg |= RME96_WCR_DS;
709 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
710 RME96_WCR_FREQ_1;
711 break;
712 default:
713 return -EINVAL;
714 }
715 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
716 (ds && !(rme96->wcreg & RME96_WCR_DS)))
717 {
718 /* change to/from double-speed: reset the DAC (if available) */
719 snd_rme96_reset_dac(rme96);
a74a8216 720 return 1; /* need to restore volume */
1da177e4
LT		 721 } else {
722 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
a74a8216 723 return 0;
1da177e4 724 }
1da177e4
LT		 725}
726
727static int
a3aefd88 728snd_rme96_capture_analog_setrate(struct rme96 *rme96,
1da177e4
LT		 729 int rate)
730{
731 switch (rate) {
732 case 32000:
733 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
734 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
735 break;
736 case 44100:
737 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
738 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
739 break;
740 case 48000:
741 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
742 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
743 break;
744 case 64000:
745 if (rme96->rev < 4) {
746 return -EINVAL;
747 }
748 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
749 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
750 break;
751 case 88200:
752 if (rme96->rev < 4) {
753 return -EINVAL;
754 }
755 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
756 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
757 break;
758 case 96000:
759 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
760 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
761 break;
762 default:
763 return -EINVAL;
764 }
765 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
766 return 0;
767}
768
769static int
a3aefd88 770snd_rme96_setclockmode(struct rme96 *rme96,
1da177e4
LT		 771 int mode)
772{
773 switch (mode) {
774 case RME96_CLOCKMODE_SLAVE:
775 /* AutoSync */
776 rme96->wcreg &= ~RME96_WCR_MASTER;
777 rme96->areg &= ~RME96_AR_WSEL;
778 break;
779 case RME96_CLOCKMODE_MASTER:
780 /* Internal */
781 rme96->wcreg |= RME96_WCR_MASTER;
782 rme96->areg &= ~RME96_AR_WSEL;
783 break;
784 case RME96_CLOCKMODE_WORDCLOCK:
785 /* Word clock is a master mode */
786 rme96->wcreg |= RME96_WCR_MASTER;
787 rme96->areg |= RME96_AR_WSEL;
788 break;
789 default:
790 return -EINVAL;
791 }
792 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
793 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
794 return 0;
795}
796
797static int
a3aefd88 798snd_rme96_getclockmode(struct rme96 *rme96)
1da177e4
LT		 799{
800 if (rme96->areg & RME96_AR_WSEL) {
801 return RME96_CLOCKMODE_WORDCLOCK;
802 }
803 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
804 RME96_CLOCKMODE_SLAVE;
805}
806
807static int
a3aefd88 808snd_rme96_setinputtype(struct rme96 *rme96,
1da177e4
LT		 809 int type)
810{
811 int n;
812
813 switch (type) {
814 case RME96_INPUT_OPTICAL:
815 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
816 ~RME96_WCR_INP_1;
817 break;
818 case RME96_INPUT_COAXIAL:
819 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
820 ~RME96_WCR_INP_1;
821 break;
822 case RME96_INPUT_INTERNAL:
823 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
824 RME96_WCR_INP_1;
825 break;
826 case RME96_INPUT_XLR:
8b7fc421
RD		 827 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
828 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
829 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
1da177e4
LT		 830 rme96->rev > 4))
831 {
832 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
833 return -EINVAL;
834 }
835 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
836 RME96_WCR_INP_1;
837 break;
838 case RME96_INPUT_ANALOG:
839 if (!RME96_HAS_ANALOG_IN(rme96)) {
840 return -EINVAL;
841 }
842 rme96->areg |= RME96_AR_ANALOG;
843 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
844 if (rme96->rev < 4) {
845 /*
846 * Revision less than 004 does not support 64 and
847 * 88.2 kHz
848 */
849 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
850 snd_rme96_capture_analog_setrate(rme96, 44100);
851 }
852 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
853 snd_rme96_capture_analog_setrate(rme96, 32000);
854 }
855 }
856 return 0;
857 default:
858 return -EINVAL;
859 }
860 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
861 rme96->areg &= ~RME96_AR_ANALOG;
862 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
863 }
864 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
865 return 0;
866}
867
868static int
a3aefd88 869snd_rme96_getinputtype(struct rme96 *rme96)
1da177e4
LT		 870{
871 if (rme96->areg & RME96_AR_ANALOG) {
872 return RME96_INPUT_ANALOG;
873 }
874 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
875 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
876}
877
878static void
a3aefd88 879snd_rme96_setframelog(struct rme96 *rme96,
1da177e4
LT		 880 int n_channels,
881 int is_playback)
882{
883 int frlog;
884
885 if (n_channels == 2) {
886 frlog = 1;
887 } else {
888 /* assume 8 channels */
889 frlog = 3;
890 }
891 if (is_playback) {
892 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
893 rme96->playback_frlog = frlog;
894 } else {
895 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
896 rme96->capture_frlog = frlog;
897 }
898}
899
900static int
6c869d30 901snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
1da177e4
LT		 902{
903 switch (format) {
904 case SNDRV_PCM_FORMAT_S16_LE:
905 rme96->wcreg &= ~RME96_WCR_MODE24;
906 break;
907 case SNDRV_PCM_FORMAT_S32_LE:
908 rme96->wcreg |= RME96_WCR_MODE24;
909 break;
910 default:
911 return -EINVAL;
912 }
913 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
914 return 0;
915}
916
917static int
6c869d30 918snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
1da177e4
LT		 919{
920 switch (format) {
921 case SNDRV_PCM_FORMAT_S16_LE:
922 rme96->wcreg &= ~RME96_WCR_MODE24_2;
923 break;
924 case SNDRV_PCM_FORMAT_S32_LE:
925 rme96->wcreg |= RME96_WCR_MODE24_2;
926 break;
927 default:
928 return -EINVAL;
929 }
930 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
931 return 0;
932}
933
934static void
a3aefd88 935snd_rme96_set_period_properties(struct rme96 *rme96,
1da177e4
LT		 936 size_t period_bytes)
937{
938 switch (period_bytes) {
939 case RME96_LARGE_BLOCK_SIZE:
940 rme96->wcreg &= ~RME96_WCR_ISEL;
941 break;
942 case RME96_SMALL_BLOCK_SIZE:
943 rme96->wcreg |= RME96_WCR_ISEL;
944 break;
945 default:
946 snd_BUG();
947 break;
948 }
949 rme96->wcreg &= ~RME96_WCR_IDIS;
950 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
951}
952
953static int
a3aefd88
TI		 954snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
955 struct snd_pcm_hw_params *params)
1da177e4 956{
a3aefd88
TI		 957 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
958 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 959 int err, rate, dummy;
a74a8216 960 bool apply_dac_volume = false;
1da177e4 961
4d23359b
CL		 962 runtime->dma_area = (void __force *)(rme96->iobase +
963 RME96_IO_PLAY_BUFFER);
1da177e4
LT		 964 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
965 runtime->dma_bytes = RME96_BUFFER_SIZE;
966
967 spin_lock_irq(&rme96->lock);
da8eedb1 968 rate = 0;
1da177e4 969 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
da8eedb1
TI		 970 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG)
971 rate = snd_rme96_capture_getrate(rme96, &dummy);
972 if (rate > 0) {
1da177e4
LT		 973 /* slave clock */
974 if ((int)params_rate(params) != rate) {
a74a8216
TI		 975 err = -EIO;
976 goto error;
977 }
978 } else {
979 err = snd_rme96_playback_setrate(rme96, params_rate(params));
980 if (err < 0)
981 goto error;
982 apply_dac_volume = err > 0; /* need to restore volume later? */
1da177e4 983 }
a74a8216
TI		 984
985 err = snd_rme96_playback_setformat(rme96, params_format(params));
986 if (err < 0)
987 goto error;
1da177e4
LT		 988 snd_rme96_setframelog(rme96, params_channels(params), 1);
989 if (rme96->capture_periodsize != 0) {
990 if (params_period_size(params) << rme96->playback_frlog !=
991 rme96->capture_periodsize)
992 {
a74a8216
TI		 993 err = -EBUSY;
994 goto error;
1da177e4
LT		 995 }
996 }
997 rme96->playback_periodsize =
998 params_period_size(params) << rme96->playback_frlog;
999 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1000 /* S/PDIF setup */
1001 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1002 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1003 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1004 }
a74a8216
TI		 1005
1006 err = 0;
1007 error:
1da177e4 1008 spin_unlock_irq(&rme96->lock);
a74a8216
TI		 1009 if (apply_dac_volume) {
1010 usleep_range(3000, 10000);
1011 snd_rme96_apply_dac_volume(rme96);
1012 }
1013
1014 return err;
1da177e4
LT		 1015}
1016
1017static int
a3aefd88
TI		 1018snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1019 struct snd_pcm_hw_params *params)
1da177e4 1020{
a3aefd88
TI		 1021 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1022 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1023 int err, isadat, rate;
1024
4d23359b
CL		 1025 runtime->dma_area = (void __force *)(rme96->iobase +
1026 RME96_IO_REC_BUFFER);
1da177e4
LT		 1027 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1028 runtime->dma_bytes = RME96_BUFFER_SIZE;
1029
1030 spin_lock_irq(&rme96->lock);
da8eedb1
TI		 1031 err = snd_rme96_capture_setformat(rme96, params_format(params));
1032 if (err < 0) {
1da177e4
LT		 1033 spin_unlock_irq(&rme96->lock);
1034 return err;
1035 }
1036 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
da8eedb1
TI		 1037 err = snd_rme96_capture_analog_setrate(rme96, params_rate(params));
1038 if (err < 0) {
1da177e4
LT		 1039 spin_unlock_irq(&rme96->lock);
1040 return err;
1041 }
da8eedb1
TI		 1042 } else {
1043 rate = snd_rme96_capture_getrate(rme96, &isadat);
1044 if (rate > 0) {
1045 if ((int)params_rate(params) != rate) {
1046 spin_unlock_irq(&rme96->lock);
1047 return -EIO;
1048 }
1049 if ((isadat && runtime->hw.channels_min == 2) ||
1050 (!isadat && runtime->hw.channels_min == 8)) {
1051 spin_unlock_irq(&rme96->lock);
1052 return -EIO;
1053 }
1054 }
1da177e4
LT		 1055 }
1056 snd_rme96_setframelog(rme96, params_channels(params), 0);
1057 if (rme96->playback_periodsize != 0) {
1058 if (params_period_size(params) << rme96->capture_frlog !=
1059 rme96->playback_periodsize)
1060 {
1061 spin_unlock_irq(&rme96->lock);
1062 return -EBUSY;
1063 }
1064 }
1065 rme96->capture_periodsize =
1066 params_period_size(params) << rme96->capture_frlog;
1067 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1068 spin_unlock_irq(&rme96->lock);
1069
1070 return 0;
1071}
1072
1073static void
b892ca1c
KP		 1074snd_rme96_trigger(struct rme96 *rme96,
1075 int op)
1da177e4 1076{
b892ca1c 1077 if (op & RME96_TB_RESET_PLAYPOS)
1da177e4 1078 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
b892ca1c 1079 if (op & RME96_TB_RESET_CAPTUREPOS)
1da177e4 1080 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
b892ca1c
KP		 1081 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1082 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1083 if (rme96->rcreg & RME96_RCR_IRQ)
1084 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1da177e4 1085 }
b892ca1c
KP		 1086 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1087 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1088 if (rme96->rcreg & RME96_RCR_IRQ_2)
1089 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1090 }
1091 if (op & RME96_TB_START_PLAYBACK)
1092 rme96->wcreg |= RME96_WCR_START;
1093 if (op & RME96_TB_STOP_PLAYBACK)
1094 rme96->wcreg &= ~RME96_WCR_START;
1095 if (op & RME96_TB_START_CAPTURE)
1096 rme96->wcreg |= RME96_WCR_START_2;
1097 if (op & RME96_TB_STOP_CAPTURE)
1098 rme96->wcreg &= ~RME96_WCR_START_2;
1da177e4
LT		 1099 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1100}
1101
1da177e4 1102
1da177e4
LT		 1103
1104static irqreturn_t
1105snd_rme96_interrupt(int irq,
7d12e780 1106 void *dev_id)
1da177e4 1107{
a3aefd88 1108 struct rme96 *rme96 = (struct rme96 *)dev_id;
1da177e4
LT		 1109
1110 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1111 /* fastpath out, to ease interrupt sharing */
1112 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1113 (rme96->rcreg & RME96_RCR_IRQ_2)))
1114 {
1115 return IRQ_NONE;
1116 }
1117
1118 if (rme96->rcreg & RME96_RCR_IRQ) {
1119 /* playback */
1120 snd_pcm_period_elapsed(rme96->playback_substream);
1121 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1122 }
1123 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1124 /* capture */
1125 snd_pcm_period_elapsed(rme96->capture_substream);
1126 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1127 }
1128 return IRQ_HANDLED;
1129}
1130
84e7b998 1131static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1da177e4 1132
84e7b998 1133static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 1134 .count = ARRAY_SIZE(period_bytes),
1135 .list = period_bytes,
1136 .mask = 0
1137};
1138
2ce7fb57
TI		 1139static void
1140rme96_set_buffer_size_constraint(struct rme96 *rme96,
1141 struct snd_pcm_runtime *runtime)
1142{
1143 unsigned int size;
1144
1a8e41ef
LPC		 1145 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1146 RME96_BUFFER_SIZE);
da8eedb1
TI		 1147 size = rme96->playback_periodsize;
1148 if (!size)
1149 size = rme96->capture_periodsize;
1150 if (size)
1a8e41ef 1151 snd_pcm_hw_constraint_single(runtime,
2ce7fb57 1152 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1a8e41ef 1153 size);
2ce7fb57
TI		 1154 else
1155 snd_pcm_hw_constraint_list(runtime, 0,
1156 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1157 &hw_constraints_period_bytes);
1158}
1159
1da177e4 1160static int
a3aefd88 1161snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1162{
1163 int rate, dummy;
a3aefd88
TI		 1164 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1165 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1166
b892ca1c 1167 snd_pcm_set_sync(substream);
1da177e4 1168 spin_lock_irq(&rme96->lock);
2cb98d01 1169 if (rme96->playback_substream) {
1da177e4
LT		 1170 spin_unlock_irq(&rme96->lock);
1171 return -EBUSY;
1172 }
1173 rme96->wcreg &= ~RME96_WCR_ADAT;
1174 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1175 rme96->playback_substream = substream;
1176 spin_unlock_irq(&rme96->lock);
1177
1178 runtime->hw = snd_rme96_playback_spdif_info;
1179 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
da8eedb1
TI		 1180 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
1181 rate = snd_rme96_capture_getrate(rme96, &dummy);
1182 if (rate > 0) {
1183 /* slave clock */
1184 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1185 runtime->hw.rate_min = rate;
1186 runtime->hw.rate_max = rate;
1187 }
1da177e4 1188 }
2ce7fb57 1189 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1190
1191 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1192 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1193 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1194 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1195 return 0;
1196}
1197
1198static int
a3aefd88 1199snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1200{
1201 int isadat, rate;
a3aefd88
TI		 1202 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1203 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1204
b892ca1c 1205 snd_pcm_set_sync(substream);
1da177e4 1206 runtime->hw = snd_rme96_capture_spdif_info;
da8eedb1
TI		 1207 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
1208 rate = snd_rme96_capture_getrate(rme96, &isadat);
1209 if (rate > 0) {
1210 if (isadat)
1211 return -EIO;
1212 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1213 runtime->hw.rate_min = rate;
1214 runtime->hw.rate_max = rate;
1215 }
1216 }
1da177e4
LT		 1217
1218 spin_lock_irq(&rme96->lock);
2cb98d01 1219 if (rme96->capture_substream) {
1da177e4
LT		 1220 spin_unlock_irq(&rme96->lock);
1221 return -EBUSY;
1222 }
1223 rme96->capture_substream = substream;
1224 spin_unlock_irq(&rme96->lock);
1225
2ce7fb57 1226 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1227 return 0;
1228}
1229
1230static int
a3aefd88 1231snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1232{
1233 int rate, dummy;
a3aefd88
TI		 1234 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1235 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1236
b892ca1c 1237 snd_pcm_set_sync(substream);
1da177e4 1238 spin_lock_irq(&rme96->lock);
2cb98d01 1239 if (rme96->playback_substream) {
1da177e4
LT		 1240 spin_unlock_irq(&rme96->lock);
1241 return -EBUSY;
1242 }
1243 rme96->wcreg |= RME96_WCR_ADAT;
1244 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1245 rme96->playback_substream = substream;
1246 spin_unlock_irq(&rme96->lock);
1247
1248 runtime->hw = snd_rme96_playback_adat_info;
1249 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
da8eedb1
TI		 1250 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
1251 rate = snd_rme96_capture_getrate(rme96, &dummy);
1252 if (rate > 0) {
1253 /* slave clock */
1254 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1255 runtime->hw.rate_min = rate;
1256 runtime->hw.rate_max = rate;
1257 }
1258 }
1259
2ce7fb57 1260 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1261 return 0;
1262}
1263
1264static int
a3aefd88 1265snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1266{
1267 int isadat, rate;
a3aefd88
TI		 1268 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1269 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1270
b892ca1c 1271 snd_pcm_set_sync(substream);
1da177e4
LT		 1272 runtime->hw = snd_rme96_capture_adat_info;
1273 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1274 /* makes no sense to use analog input. Note that analog
1275 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1276 return -EIO;
1277 }
da8eedb1
TI		 1278 rate = snd_rme96_capture_getrate(rme96, &isadat);
1279 if (rate > 0) {
1da177e4
LT		 1280 if (!isadat) {
1281 return -EIO;
1282 }
918f3a0e 1283 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1284 runtime->hw.rate_min = rate;
1285 runtime->hw.rate_max = rate;
1286 }
1287
1288 spin_lock_irq(&rme96->lock);
2cb98d01 1289 if (rme96->capture_substream) {
1da177e4
LT		 1290 spin_unlock_irq(&rme96->lock);
1291 return -EBUSY;
1292 }
1293 rme96->capture_substream = substream;
1294 spin_unlock_irq(&rme96->lock);
1295
2ce7fb57 1296 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1297 return 0;
1298}
1299
1300static int
a3aefd88 1301snd_rme96_playback_close(struct snd_pcm_substream *substream)
1da177e4 1302{
a3aefd88 1303 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1304 int spdif = 0;
1305
1306 spin_lock_irq(&rme96->lock);
1307 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1308 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1309 }
1310 rme96->playback_substream = NULL;
1311 rme96->playback_periodsize = 0;
1312 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1313 spin_unlock_irq(&rme96->lock);
1314 if (spdif) {
1315 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1316 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1317 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1318 }
1319 return 0;
1320}
1321
1322static int
a3aefd88 1323snd_rme96_capture_close(struct snd_pcm_substream *substream)
1da177e4 1324{
a3aefd88 1325 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1326
1327 spin_lock_irq(&rme96->lock);
1328 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1329 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1330 }
1331 rme96->capture_substream = NULL;
1332 rme96->capture_periodsize = 0;
1333 spin_unlock_irq(&rme96->lock);
1334 return 0;
1335}
1336
1337static int
a3aefd88 1338snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1339{
a3aefd88 1340 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1341
1342 spin_lock_irq(&rme96->lock);
1343 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1344 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1345 }
1346 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1347 spin_unlock_irq(&rme96->lock);
1348 return 0;
1349}
1350
1351static int
a3aefd88 1352snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1353{
a3aefd88 1354 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1355
1356 spin_lock_irq(&rme96->lock);
1357 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1358 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1359 }
1360 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1361 spin_unlock_irq(&rme96->lock);
1362 return 0;
1363}
1364
1365static int
a3aefd88 1366snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1367 int cmd)
1368{
a3aefd88 1369 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1370 struct snd_pcm_substream *s;
1371 bool sync;
1372
1373 snd_pcm_group_for_each_entry(s, substream) {
1374 if (snd_pcm_substream_chip(s) == rme96)
1375 snd_pcm_trigger_done(s, substream);
1376 }
1377
1378 sync = (rme96->playback_substream && rme96->capture_substream) &&
1379 (rme96->playback_substream->group ==
1380 rme96->capture_substream->group);
1da177e4
LT		 1381
1382 switch (cmd) {
1383 case SNDRV_PCM_TRIGGER_START:
1384 if (!RME96_ISPLAYING(rme96)) {
b892ca1c 1385 if (substream != rme96->playback_substream)
1da177e4 1386 return -EBUSY;
b892ca1c
KP		 1387 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1388 : RME96_START_PLAYBACK);
1da177e4
LT		 1389 }
1390 break;
1391
528ba522 1392 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1393 case SNDRV_PCM_TRIGGER_STOP:
1394 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1395 if (substream != rme96->playback_substream)
1da177e4 1396 return -EBUSY;
b892ca1c
KP		 1397 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1398 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1399 }
1400 break;
1401
1402 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1403 if (RME96_ISPLAYING(rme96))
1404 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1405 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1406 break;
1407
528ba522 1408 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1409 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1410 if (!RME96_ISPLAYING(rme96))
1411 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1412 : RME96_RESUME_PLAYBACK);
1da177e4 1413 break;
b892ca1c 1414
1da177e4
LT		 1415 default:
1416 return -EINVAL;
1417 }
b892ca1c 1418
1da177e4
LT		 1419 return 0;
1420}
1421
1422static int
a3aefd88 1423snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1424 int cmd)
1425{
a3aefd88 1426 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1427 struct snd_pcm_substream *s;
1428 bool sync;
1429
1430 snd_pcm_group_for_each_entry(s, substream) {
1431 if (snd_pcm_substream_chip(s) == rme96)
1432 snd_pcm_trigger_done(s, substream);
1433 }
1434
1435 sync = (rme96->playback_substream && rme96->capture_substream) &&
1436 (rme96->playback_substream->group ==
1437 rme96->capture_substream->group);
1da177e4
LT		 1438
1439 switch (cmd) {
1440 case SNDRV_PCM_TRIGGER_START:
1441 if (!RME96_ISRECORDING(rme96)) {
b892ca1c 1442 if (substream != rme96->capture_substream)
1da177e4 1443 return -EBUSY;
b892ca1c
KP		 1444 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1445 : RME96_START_CAPTURE);
1da177e4
LT		 1446 }
1447 break;
1448
528ba522 1449 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1450 case SNDRV_PCM_TRIGGER_STOP:
1451 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1452 if (substream != rme96->capture_substream)
1da177e4 1453 return -EBUSY;
b892ca1c
KP		 1454 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1455 : RME96_STOP_CAPTURE);
1da177e4
LT		 1456 }
1457 break;
1458
1459 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1460 if (RME96_ISRECORDING(rme96))
1461 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1462 : RME96_STOP_CAPTURE);
1da177e4
LT		 1463 break;
1464
528ba522 1465 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1466 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1467 if (!RME96_ISRECORDING(rme96))
1468 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1469 : RME96_RESUME_CAPTURE);
1da177e4 1470 break;
b892ca1c 1471
1da177e4
LT		 1472 default:
1473 return -EINVAL;
1474 }
1475
1476 return 0;
1477}
1478
1479static snd_pcm_uframes_t
a3aefd88 1480snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1481{
a3aefd88 1482 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1483 return snd_rme96_playback_ptr(rme96);
1484}
1485
1486static snd_pcm_uframes_t
a3aefd88 1487snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1488{
a3aefd88 1489 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1490 return snd_rme96_capture_ptr(rme96);
1491}
1492
6769e988 1493static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1da177e4
LT		 1494 .open = snd_rme96_playback_spdif_open,
1495 .close = snd_rme96_playback_close,
1da177e4
LT		 1496 .hw_params = snd_rme96_playback_hw_params,
1497 .prepare = snd_rme96_playback_prepare,
1498 .trigger = snd_rme96_playback_trigger,
1499 .pointer = snd_rme96_playback_pointer,
c3abdf06 1500 .copy = snd_rme96_playback_copy,
53945f5b 1501 .fill_silence = snd_rme96_playback_silence,
1da177e4
LT		 1502 .mmap = snd_pcm_lib_mmap_iomem,
1503};
1504
6769e988 1505static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1da177e4
LT		 1506 .open = snd_rme96_capture_spdif_open,
1507 .close = snd_rme96_capture_close,
1da177e4
LT		 1508 .hw_params = snd_rme96_capture_hw_params,
1509 .prepare = snd_rme96_capture_prepare,
1510 .trigger = snd_rme96_capture_trigger,
1511 .pointer = snd_rme96_capture_pointer,
c3abdf06 1512 .copy = snd_rme96_capture_copy,
1da177e4
LT		 1513 .mmap = snd_pcm_lib_mmap_iomem,
1514};
1515
6769e988 1516static const struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1da177e4
LT		 1517 .open = snd_rme96_playback_adat_open,
1518 .close = snd_rme96_playback_close,
1da177e4
LT		 1519 .hw_params = snd_rme96_playback_hw_params,
1520 .prepare = snd_rme96_playback_prepare,
1521 .trigger = snd_rme96_playback_trigger,
1522 .pointer = snd_rme96_playback_pointer,
c3abdf06 1523 .copy = snd_rme96_playback_copy,
53945f5b 1524 .fill_silence = snd_rme96_playback_silence,
1da177e4
LT		 1525 .mmap = snd_pcm_lib_mmap_iomem,
1526};
1527
6769e988 1528static const struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1da177e4
LT		 1529 .open = snd_rme96_capture_adat_open,
1530 .close = snd_rme96_capture_close,
1da177e4
LT		 1531 .hw_params = snd_rme96_capture_hw_params,
1532 .prepare = snd_rme96_capture_prepare,
1533 .trigger = snd_rme96_capture_trigger,
1534 .pointer = snd_rme96_capture_pointer,
c3abdf06 1535 .copy = snd_rme96_capture_copy,
1da177e4
LT		 1536 .mmap = snd_pcm_lib_mmap_iomem,
1537};
1538
1539static void
df06df7c 1540snd_rme96_free(struct rme96 *rme96)
1da177e4 1541{
1da177e4 1542 if (rme96->irq >= 0) {
b892ca1c 1543 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1544 rme96->areg &= ~RME96_AR_DAC_EN;
1545 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1da177e4 1546 }
528ba522
KP		 1547 vfree(rme96->playback_suspend_buffer);
1548 vfree(rme96->capture_suspend_buffer);
1da177e4
LT		 1549}
1550
1551static void
a3aefd88 1552snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1553{
9fe856e4 1554 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1555 rme96->spdif_pcm = NULL;
1556}
1557
1558static void
a3aefd88 1559snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1560{
9fe856e4 1561 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1562 rme96->adat_pcm = NULL;
1563}
1564
e23e7a14 1565static int
a3aefd88 1566snd_rme96_create(struct rme96 *rme96)
1da177e4
LT		 1567{
1568 struct pci_dev *pci = rme96->pci;
1569 int err;
1570
1571 rme96->irq = -1;
1572 spin_lock_init(&rme96->lock);
1573
df06df7c 1574 err = pcim_enable_device(pci);
da8eedb1 1575 if (err < 0)
1da177e4
LT		 1576 return err;
1577
da8eedb1
TI		 1578 err = pci_request_regions(pci, "RME96");
1579 if (err < 0)
1da177e4
LT		 1580 return err;
1581 rme96->port = pci_resource_start(rme96->pci, 0);
1582
df06df7c 1583 rme96->iobase = devm_ioremap(&pci->dev, rme96->port, RME96_IO_SIZE);
44977b71 1584 if (!rme96->iobase) {
342cd934
TI		 1585 dev_err(rme96->card->dev,
1586 "unable to remap memory region 0x%lx-0x%lx\n",
1587 rme96->port, rme96->port + RME96_IO_SIZE - 1);
df06df7c 1588 return -EBUSY;
688956f2
TI		 1589 }
1590
df06df7c
TI		 1591 if (devm_request_irq(&pci->dev, pci->irq, snd_rme96_interrupt,
1592 IRQF_SHARED, KBUILD_MODNAME, rme96)) {
342cd934 1593 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1594 return -EBUSY;
1595 }
1596 rme96->irq = pci->irq;
5fcf46bc 1597 rme96->card->sync_irq = rme96->irq;
1da177e4 1598
1da177e4
LT		 1599 /* read the card's revision number */
1600 pci_read_config_byte(pci, 8, &rme96->rev);
1601
1602 /* set up ALSA pcm device for S/PDIF */
da8eedb1
TI		 1603 err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1604 1, 1, &rme96->spdif_pcm);
1605 if (err < 0)
1da177e4 1606 return err;
da8eedb1 1607
1da177e4
LT		 1608 rme96->spdif_pcm->private_data = rme96;
1609 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1610 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1611 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1612 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1613
1614 rme96->spdif_pcm->info_flags = 0;
1615
1616 /* set up ALSA pcm device for ADAT */
8b7fc421 1617 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1da177e4
LT		 1618 /* ADAT is not available on the base model */
1619 rme96->adat_pcm = NULL;
1620 } else {
da8eedb1
TI		 1621 err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1622 1, 1, &rme96->adat_pcm);
1623 if (err < 0)
1da177e4 1624 return err;
1da177e4
LT		 1625 rme96->adat_pcm->private_data = rme96;
1626 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1627 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1628 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1629 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1630
1631 rme96->adat_pcm->info_flags = 0;
1632 }
1633
1634 rme96->playback_periodsize = 0;
1635 rme96->capture_periodsize = 0;
1636
1637 /* make sure playback/capture is stopped, if by some reason active */
b892ca1c 1638 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1639
1640 /* set default values in registers */
1641 rme96->wcreg =
1642 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1643 RME96_WCR_SEL | /* normal playback */
1644 RME96_WCR_MASTER | /* set to master clock mode */
1645 RME96_WCR_INP_0; /* set coaxial input */
1646
1647 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1648
1649 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1650 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1651
1652 /* reset the ADC */
1653 writel(rme96->areg | RME96_AR_PD2,
1654 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1655 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1656
1657 /* reset and enable the DAC (order is important). */
1658 snd_rme96_reset_dac(rme96);
1659 rme96->areg |= RME96_AR_DAC_EN;
1660 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1661
1662 /* reset playback and record buffer pointers */
1663 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1664 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1665
1666 /* reset volume */
1667 rme96->vol[0] = rme96->vol[1] = 0;
1668 if (RME96_HAS_ANALOG_OUT(rme96)) {
1669 snd_rme96_apply_dac_volume(rme96);
1670 }
1671
1672 /* init switch interface */
da8eedb1
TI		 1673 err = snd_rme96_create_switches(rme96->card, rme96);
1674 if (err < 0)
1da177e4 1675 return err;
1da177e4
LT		 1676
1677 /* init proc interface */
1678 snd_rme96_proc_init(rme96);
1679
1680 return 0;
1681}
1682
1683/*
1684 * proc interface
1685 */
1686
1687static void
a3aefd88 1688snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1689{
1690 int n;
9fe856e4 1691 struct rme96 *rme96 = entry->private_data;
1da177e4
LT		 1692
1693 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1694
1695 snd_iprintf(buffer, rme96->card->longname);
1696 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1697
1698 snd_iprintf(buffer, "\nGeneral settings\n");
1699 if (rme96->wcreg & RME96_WCR_IDIS) {
1700 snd_iprintf(buffer, " period size: N/A (interrupts "
1701 "disabled)\n");
1702 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1703 snd_iprintf(buffer, " period size: 2048 bytes\n");
1704 } else {
1705 snd_iprintf(buffer, " period size: 8192 bytes\n");
1706 }
1707 snd_iprintf(buffer, "\nInput settings\n");
1708 switch (snd_rme96_getinputtype(rme96)) {
1709 case RME96_INPUT_OPTICAL:
1710 snd_iprintf(buffer, " input: optical");
1711 break;
1712 case RME96_INPUT_COAXIAL:
1713 snd_iprintf(buffer, " input: coaxial");
1714 break;
1715 case RME96_INPUT_INTERNAL:
1716 snd_iprintf(buffer, " input: internal");
1717 break;
1718 case RME96_INPUT_XLR:
1719 snd_iprintf(buffer, " input: XLR");
1720 break;
1721 case RME96_INPUT_ANALOG:
1722 snd_iprintf(buffer, " input: analog");
1723 break;
1724 }
1725 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1726 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1727 } else {
1728 if (n) {
1729 snd_iprintf(buffer, " (8 channels)\n");
1730 } else {
1731 snd_iprintf(buffer, " (2 channels)\n");
1732 }
1733 snd_iprintf(buffer, " sample rate: %d Hz\n",
1734 snd_rme96_capture_getrate(rme96, &n));
1735 }
1736 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1737 snd_iprintf(buffer, " sample format: 24 bit\n");
1738 } else {
1739 snd_iprintf(buffer, " sample format: 16 bit\n");
1740 }
1741
1742 snd_iprintf(buffer, "\nOutput settings\n");
1743 if (rme96->wcreg & RME96_WCR_SEL) {
1744 snd_iprintf(buffer, " output signal: normal playback\n");
1745 } else {
1746 snd_iprintf(buffer, " output signal: same as input\n");
1747 }
1748 snd_iprintf(buffer, " sample rate: %d Hz\n",
1749 snd_rme96_playback_getrate(rme96));
1750 if (rme96->wcreg & RME96_WCR_MODE24) {
1751 snd_iprintf(buffer, " sample format: 24 bit\n");
1752 } else {
1753 snd_iprintf(buffer, " sample format: 16 bit\n");
1754 }
1755 if (rme96->areg & RME96_AR_WSEL) {
1756 snd_iprintf(buffer, " sample clock source: word clock\n");
1757 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1758 snd_iprintf(buffer, " sample clock source: internal\n");
1759 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1760 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1761 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1762 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1763 } else {
1764 snd_iprintf(buffer, " sample clock source: autosync\n");
1765 }
1766 if (rme96->wcreg & RME96_WCR_PRO) {
1767 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1768 } else {
1769 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1770 }
1771 if (rme96->wcreg & RME96_WCR_EMP) {
1772 snd_iprintf(buffer, " emphasis: on\n");
1773 } else {
1774 snd_iprintf(buffer, " emphasis: off\n");
1775 }
1776 if (rme96->wcreg & RME96_WCR_DOLBY) {
1777 snd_iprintf(buffer, " non-audio (dolby): on\n");
1778 } else {
1779 snd_iprintf(buffer, " non-audio (dolby): off\n");
1780 }
1781 if (RME96_HAS_ANALOG_IN(rme96)) {
1782 snd_iprintf(buffer, "\nAnalog output settings\n");
1783 switch (snd_rme96_getmontracks(rme96)) {
1784 case RME96_MONITOR_TRACKS_1_2:
1785 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1786 break;
1787 case RME96_MONITOR_TRACKS_3_4:
1788 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1789 break;
1790 case RME96_MONITOR_TRACKS_5_6:
1791 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1792 break;
1793 case RME96_MONITOR_TRACKS_7_8:
1794 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1795 break;
1796 }
1797 switch (snd_rme96_getattenuation(rme96)) {
1798 case RME96_ATTENUATION_0:
1799 snd_iprintf(buffer, " attenuation: 0 dB\n");
1800 break;
1801 case RME96_ATTENUATION_6:
1802 snd_iprintf(buffer, " attenuation: -6 dB\n");
1803 break;
1804 case RME96_ATTENUATION_12:
1805 snd_iprintf(buffer, " attenuation: -12 dB\n");
1806 break;
1807 case RME96_ATTENUATION_18:
1808 snd_iprintf(buffer, " attenuation: -18 dB\n");
1809 break;
1810 }
1811 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1812 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1813 }
1814}
1815
e23e7a14 1816static void snd_rme96_proc_init(struct rme96 *rme96)
1da177e4 1817{
47f2769b 1818 snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read);
1da177e4
LT		 1819}
1820
1821/*
1822 * control interface
1823 */
1824
a5ce8890
TI		 1825#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1826
1da177e4 1827static int
a3aefd88 1828snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1829{
a3aefd88 1830 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1831
1832 spin_lock_irq(&rme96->lock);
1833 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1834 spin_unlock_irq(&rme96->lock);
1835 return 0;
1836}
1837static int
a3aefd88 1838snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1839{
a3aefd88 1840 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1841 unsigned int val;
1842 int change;
1843
1844 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1845 spin_lock_irq(&rme96->lock);
1846 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1847 change = val != rme96->wcreg;
1848 rme96->wcreg = val;
1849 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1850 spin_unlock_irq(&rme96->lock);
1851 return change;
1852}
1853
1854static int
a3aefd88 1855snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 1856{
9c30d46a
TI		 1857 static const char * const _texts[5] = {
1858 "Optical", "Coaxial", "Internal", "XLR", "Analog"
1859 };
a3aefd88 1860 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
9c30d46a
TI		 1861 const char *texts[5] = {
1862 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
1863 };
1864 int num_items;
1da177e4 1865
1da177e4 1866 switch (rme96->pci->device) {
8b7fc421
RD		 1867 case PCI_DEVICE_ID_RME_DIGI96:
1868 case PCI_DEVICE_ID_RME_DIGI96_8:
9c30d46a 1869 num_items = 3;
1da177e4 1870 break;
8b7fc421 1871 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
9c30d46a 1872 num_items = 4;
1da177e4 1873 break;
8b7fc421 1874 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1875 if (rme96->rev > 4) {
1876 /* PST */
9c30d46a 1877 num_items = 4;
1da177e4
LT		 1878 texts[3] = _texts[4]; /* Analog instead of XLR */
1879 } else {
1880 /* PAD */
9c30d46a 1881 num_items = 5;
1da177e4
LT		 1882 }
1883 break;
1884 default:
1885 snd_BUG();
9c30d46a 1886 return -EINVAL;
1da177e4 1887 }
9c30d46a 1888 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1da177e4
LT		 1889}
1890static int
a3aefd88 1891snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1892{
a3aefd88 1893 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1894 unsigned int items = 3;
1895
1896 spin_lock_irq(&rme96->lock);
1897 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1898
1899 switch (rme96->pci->device) {
8b7fc421
RD		 1900 case PCI_DEVICE_ID_RME_DIGI96:
1901 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1902 items = 3;
1903 break;
8b7fc421 1904 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1905 items = 4;
1906 break;
8b7fc421 1907 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1908 if (rme96->rev > 4) {
1909 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1910 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1911 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1912 }
1913 items = 4;
1914 } else {
1915 items = 5;
1916 }
1917 break;
1918 default:
1919 snd_BUG();
1920 break;
1921 }
1922 if (ucontrol->value.enumerated.item[0] >= items) {
1923 ucontrol->value.enumerated.item[0] = items - 1;
1924 }
1925
1926 spin_unlock_irq(&rme96->lock);
1927 return 0;
1928}
1929static int
a3aefd88 1930snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1931{
a3aefd88 1932 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1933 unsigned int val;
1934 int change, items = 3;
1935
1936 switch (rme96->pci->device) {
8b7fc421
RD		 1937 case PCI_DEVICE_ID_RME_DIGI96:
1938 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1939 items = 3;
1940 break;
8b7fc421 1941 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1942 items = 4;
1943 break;
8b7fc421 1944 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1945 if (rme96->rev > 4) {
1946 items = 4;
1947 } else {
1948 items = 5;
1949 }
1950 break;
1951 default:
1952 snd_BUG();
1953 break;
1954 }
1955 val = ucontrol->value.enumerated.item[0] % items;
1956
1957 /* special case for PST */
8b7fc421 1958 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1da177e4
LT		 1959 if (val == RME96_INPUT_XLR) {
1960 val = RME96_INPUT_ANALOG;
1961 }
1962 }
1963
1964 spin_lock_irq(&rme96->lock);
1965 change = (int)val != snd_rme96_getinputtype(rme96);
1966 snd_rme96_setinputtype(rme96, val);
1967 spin_unlock_irq(&rme96->lock);
1968 return change;
1969}
1970
1971static int
a3aefd88 1972snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 1973{
9c30d46a 1974 static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
1da177e4 1975
9c30d46a 1976 return snd_ctl_enum_info(uinfo, 1, 3, texts);
1da177e4
LT		 1977}
1978static int
a3aefd88 1979snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1980{
a3aefd88 1981 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1982
1983 spin_lock_irq(&rme96->lock);
1984 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1985 spin_unlock_irq(&rme96->lock);
1986 return 0;
1987}
1988static int
a3aefd88 1989snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1990{
a3aefd88 1991 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1992 unsigned int val;
1993 int change;
1994
1995 val = ucontrol->value.enumerated.item[0] % 3;
1996 spin_lock_irq(&rme96->lock);
1997 change = (int)val != snd_rme96_getclockmode(rme96);
1998 snd_rme96_setclockmode(rme96, val);
1999 spin_unlock_irq(&rme96->lock);
2000 return change;
2001}
2002
2003static int
a3aefd88 2004snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2005{
9c30d46a
TI		 2006 static const char * const texts[4] = {
2007 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2008 };
1da177e4 2009
9c30d46a 2010 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 2011}
2012static int
a3aefd88 2013snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2014{
a3aefd88 2015 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2016
2017 spin_lock_irq(&rme96->lock);
2018 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2019 spin_unlock_irq(&rme96->lock);
2020 return 0;
2021}
2022static int
a3aefd88 2023snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2024{
a3aefd88 2025 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2026 unsigned int val;
2027 int change;
2028
2029 val = ucontrol->value.enumerated.item[0] % 4;
2030 spin_lock_irq(&rme96->lock);
2031
2032 change = (int)val != snd_rme96_getattenuation(rme96);
2033 snd_rme96_setattenuation(rme96, val);
2034 spin_unlock_irq(&rme96->lock);
2035 return change;
2036}
2037
2038static int
a3aefd88 2039snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2040{
9c30d46a 2041 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
1da177e4 2042
9c30d46a 2043 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 2044}
2045static int
a3aefd88 2046snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2047{
a3aefd88 2048 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2049
2050 spin_lock_irq(&rme96->lock);
2051 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2052 spin_unlock_irq(&rme96->lock);
2053 return 0;
2054}
2055static int
a3aefd88 2056snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2057{
a3aefd88 2058 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2059 unsigned int val;
2060 int change;
2061
2062 val = ucontrol->value.enumerated.item[0] % 4;
2063 spin_lock_irq(&rme96->lock);
2064 change = (int)val != snd_rme96_getmontracks(rme96);
2065 snd_rme96_setmontracks(rme96, val);
2066 spin_unlock_irq(&rme96->lock);
2067 return change;
2068}
2069
a3aefd88 2070static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT		 2071{
2072 u32 val = 0;
2073 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2074 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2075 if (val & RME96_WCR_PRO)
2076 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2077 else
2078 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2079 return val;
2080}
2081
a3aefd88 2082static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT		 2083{
2084 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2085 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2086 if (val & RME96_WCR_PRO)
2087 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2088 else
2089 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2090}
2091
a3aefd88 2092static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2093{
2094 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2095 uinfo->count = 1;
2096 return 0;
2097}
2098
a3aefd88 2099static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2100{
a3aefd88 2101 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2102
2103 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2104 return 0;
2105}
2106
a3aefd88 2107static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2108{
a3aefd88 2109 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2110 int change;
2111 u32 val;
2112
2113 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2114 spin_lock_irq(&rme96->lock);
2115 change = val != rme96->wcreg_spdif;
2116 rme96->wcreg_spdif = val;
2117 spin_unlock_irq(&rme96->lock);
2118 return change;
2119}
2120
a3aefd88 2121static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2122{
2123 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2124 uinfo->count = 1;
2125 return 0;
2126}
2127
a3aefd88 2128static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2129{
a3aefd88 2130 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2131
2132 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2133 return 0;
2134}
2135
a3aefd88 2136static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2137{
a3aefd88 2138 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2139 int change;
2140 u32 val;
2141
2142 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2143 spin_lock_irq(&rme96->lock);
2144 change = val != rme96->wcreg_spdif_stream;
2145 rme96->wcreg_spdif_stream = val;
2146 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2147 rme96->wcreg |= val;
2148 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2149 spin_unlock_irq(&rme96->lock);
2150 return change;
2151}
2152
a3aefd88 2153static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2154{
2155 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2156 uinfo->count = 1;
2157 return 0;
2158}
2159
a3aefd88 2160static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2161{
2162 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2163 return 0;
2164}
2165
2166static int
a3aefd88 2167snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2168{
a3aefd88 2169 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2170
2171 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2172 uinfo->count = 2;
2173 uinfo->value.integer.min = 0;
2174 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2175 return 0;
2176}
2177
2178static int
a3aefd88 2179snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2180{
a3aefd88 2181 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2182
2183 spin_lock_irq(&rme96->lock);
2184 u->value.integer.value[0] = rme96->vol[0];
2185 u->value.integer.value[1] = rme96->vol[1];
2186 spin_unlock_irq(&rme96->lock);
2187
2188 return 0;
2189}
2190
2191static int
a3aefd88 2192snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2193{
a3aefd88 2194 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4 2195 int change = 0;
4e98d6a7 2196 unsigned int vol, maxvol;
1da177e4 2197
4e98d6a7
TI		 2198
2199 if (!RME96_HAS_ANALOG_OUT(rme96))
1da177e4 2200 return -EINVAL;
4e98d6a7 2201 maxvol = RME96_185X_MAX_OUT(rme96);
1da177e4 2202 spin_lock_irq(&rme96->lock);
4e98d6a7
TI		 2203 vol = u->value.integer.value[0];
2204 if (vol != rme96->vol[0] && vol <= maxvol) {
2205 rme96->vol[0] = vol;
2206 change = 1;
2207 }
2208 vol = u->value.integer.value[1];
2209 if (vol != rme96->vol[1] && vol <= maxvol) {
2210 rme96->vol[1] = vol;
2211 change = 1;
1da177e4 2212 }
4e98d6a7
TI		 2213 if (change)
2214 snd_rme96_apply_dac_volume(rme96);
1da177e4
LT		 2215 spin_unlock_irq(&rme96->lock);
2216
2217 return change;
2218}
2219
b4e5e707 2220static const struct snd_kcontrol_new snd_rme96_controls[] = {
1da177e4
LT		 2221{
2222 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2223 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2224 .info = snd_rme96_control_spdif_info,
2225 .get = snd_rme96_control_spdif_get,
2226 .put = snd_rme96_control_spdif_put
2227},
2228{
2229 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2230 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2231 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2232 .info = snd_rme96_control_spdif_stream_info,
2233 .get = snd_rme96_control_spdif_stream_get,
2234 .put = snd_rme96_control_spdif_stream_put
2235},
2236{
2237 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2238 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2239 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2240 .info = snd_rme96_control_spdif_mask_info,
2241 .get = snd_rme96_control_spdif_mask_get,
2242 .private_value = IEC958_AES0_NONAUDIO |
2243 IEC958_AES0_PROFESSIONAL |
2244 IEC958_AES0_CON_EMPHASIS
2245},
2246{
2247 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2248 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2249 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2250 .info = snd_rme96_control_spdif_mask_info,
2251 .get = snd_rme96_control_spdif_mask_get,
2252 .private_value = IEC958_AES0_NONAUDIO |
2253 IEC958_AES0_PROFESSIONAL |
2254 IEC958_AES0_PRO_EMPHASIS
2255},
2256{
2257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2258 .name = "Input Connector",
2259 .info = snd_rme96_info_inputtype_control,
2260 .get = snd_rme96_get_inputtype_control,
2261 .put = snd_rme96_put_inputtype_control
2262},
2263{
2264 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2265 .name = "Loopback Input",
2266 .info = snd_rme96_info_loopback_control,
2267 .get = snd_rme96_get_loopback_control,
2268 .put = snd_rme96_put_loopback_control
2269},
2270{
2271 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2272 .name = "Sample Clock Source",
2273 .info = snd_rme96_info_clockmode_control,
2274 .get = snd_rme96_get_clockmode_control,
2275 .put = snd_rme96_put_clockmode_control
2276},
2277{
2278 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2279 .name = "Monitor Tracks",
2280 .info = snd_rme96_info_montracks_control,
2281 .get = snd_rme96_get_montracks_control,
2282 .put = snd_rme96_put_montracks_control
2283},
2284{
2285 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2286 .name = "Attenuation",
2287 .info = snd_rme96_info_attenuation_control,
2288 .get = snd_rme96_get_attenuation_control,
2289 .put = snd_rme96_put_attenuation_control
2290},
2291{
2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293 .name = "DAC Playback Volume",
2294 .info = snd_rme96_dac_volume_info,
2295 .get = snd_rme96_dac_volume_get,
2296 .put = snd_rme96_dac_volume_put
2297}
2298};
2299
2300static int
a3aefd88
TI		 2301snd_rme96_create_switches(struct snd_card *card,
2302 struct rme96 *rme96)
1da177e4
LT		 2303{
2304 int idx, err;
a3aefd88 2305 struct snd_kcontrol *kctl;
1da177e4
LT		 2306
2307 for (idx = 0; idx < 7; idx++) {
da8eedb1
TI		 2308 kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96);
2309 err = snd_ctl_add(card, kctl);
2310 if (err < 0)
1da177e4
LT		 2311 return err;
2312 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2313 rme96->spdif_ctl = kctl;
2314 }
2315
2316 if (RME96_HAS_ANALOG_OUT(rme96)) {
da8eedb1
TI		 2317 for (idx = 7; idx < 10; idx++) {
2318 err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96));
2319 if (err < 0)
1da177e4 2320 return err;
da8eedb1 2321 }
1da177e4
LT		 2322 }
2323
2324 return 0;
2325}
2326
2327/*
2328 * Card initialisation
2329 */
2330
a932be91 2331static int rme96_suspend(struct device *dev)
528ba522 2332{
a932be91 2333 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2334 struct rme96 *rme96 = card->private_data;
2335
2336 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
528ba522
KP		 2337
2338 /* save capture & playback pointers */
2339 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2340 & RME96_RCR_AUDIO_ADDR_MASK;
2341 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2342 & RME96_RCR_AUDIO_ADDR_MASK;
2343
2344 /* save playback and capture buffers */
2345 memcpy_fromio(rme96->playback_suspend_buffer,
2346 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2347 memcpy_fromio(rme96->capture_suspend_buffer,
2348 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2349
2350 /* disable the DAC */
2351 rme96->areg &= ~RME96_AR_DAC_EN;
2352 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
528ba522
KP		 2353 return 0;
2354}
2355
a932be91 2356static int rme96_resume(struct device *dev)
528ba522 2357{
a932be91 2358 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2359 struct rme96 *rme96 = card->private_data;
2360
528ba522
KP		 2361 /* reset playback and record buffer pointers */
2362 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2363 + rme96->playback_pointer);
2364 writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2365 + rme96->capture_pointer);
2366
2367 /* restore playback and capture buffers */
2368 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2369 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2370 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2371 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2372
2373 /* reset the ADC */
2374 writel(rme96->areg | RME96_AR_PD2,
2375 rme96->iobase + RME96_IO_ADDITIONAL_REG);
2376 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2377
2378 /* reset and enable DAC, restore analog volume */
2379 snd_rme96_reset_dac(rme96);
2380 rme96->areg |= RME96_AR_DAC_EN;
2381 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2382 if (RME96_HAS_ANALOG_OUT(rme96)) {
2383 usleep_range(3000, 10000);
2384 snd_rme96_apply_dac_volume(rme96);
2385 }
2386
2387 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2388
2389 return 0;
2390}
2391
ea1741dc 2392static DEFINE_SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
528ba522 2393
a3aefd88 2394static void snd_rme96_card_free(struct snd_card *card)
1da177e4
LT		 2395{
2396 snd_rme96_free(card->private_data);
2397}
2398
e23e7a14 2399static int
93b884f8
TI		 2400__snd_rme96_probe(struct pci_dev *pci,
2401 const struct pci_device_id *pci_id)
1da177e4
LT		 2402{
2403 static int dev;
a3aefd88
TI		 2404 struct rme96 *rme96;
2405 struct snd_card *card;
1da177e4
LT		 2406 int err;
2407 u8 val;
2408
2409 if (dev >= SNDRV_CARDS) {
2410 return -ENODEV;
2411 }
2412 if (!enable[dev]) {
2413 dev++;
2414 return -ENOENT;
2415 }
df06df7c
TI		 2416 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2417 sizeof(*rme96), &card);
e58de7ba
TI		 2418 if (err < 0)
2419 return err;
1da177e4 2420 card->private_free = snd_rme96_card_free;
9fe856e4 2421 rme96 = card->private_data;
1da177e4
LT		 2422 rme96->card = card;
2423 rme96->pci = pci;
d72a8010
ME		 2424 err = snd_rme96_create(rme96);
2425 if (err)
df06df7c 2426 return err;
1da177e4 2427
ea1741dc
TI		 2428 if (IS_ENABLED(CONFIG_PM_SLEEP)) {
2429 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2430 if (!rme96->playback_suspend_buffer)
2431 return -ENOMEM;
2432 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2433 if (!rme96->capture_suspend_buffer)
2434 return -ENOMEM;
2435 }
528ba522 2436
1da177e4
LT		 2437 strcpy(card->driver, "Digi96");
2438 switch (rme96->pci->device) {
8b7fc421 2439 case PCI_DEVICE_ID_RME_DIGI96:
1da177e4
LT		 2440 strcpy(card->shortname, "RME Digi96");
2441 break;
8b7fc421 2442 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 2443 strcpy(card->shortname, "RME Digi96/8");
2444 break;
8b7fc421 2445 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 2446 strcpy(card->shortname, "RME Digi96/8 PRO");
2447 break;
8b7fc421 2448 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2449 pci_read_config_byte(rme96->pci, 8, &val);
2450 if (val < 5) {
2451 strcpy(card->shortname, "RME Digi96/8 PAD");
2452 } else {
2453 strcpy(card->shortname, "RME Digi96/8 PST");
2454 }
2455 break;
2456 }
2457 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2458 rme96->port, rme96->irq);
d72a8010
ME		 2459 err = snd_card_register(card);
2460 if (err)
df06df7c 2461 return err;
d72a8010 2462
1da177e4
LT		 2463 pci_set_drvdata(pci, card);
2464 dev++;
2465 return 0;
1da177e4
LT		 2466}
2467
93b884f8
TI		 2468static int snd_rme96_probe(struct pci_dev *pci,
2469 const struct pci_device_id *pci_id)
2470{
2471 return snd_card_free_on_error(&pci->dev, __snd_rme96_probe(pci, pci_id));
2472}
2473
e9f66d9b 2474static struct pci_driver rme96_driver = {
3733e424 2475 .name = KBUILD_MODNAME,
1da177e4
LT		 2476 .id_table = snd_rme96_ids,
2477 .probe = snd_rme96_probe,
a932be91 2478 .driver = {
ea1741dc 2479 .pm = &rme96_pm,
a932be91 2480 },
1da177e4
LT		 2481};
2482
e9f66d9b 2483module_pci_driver(rme96_driver);
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