[linux.git] / drivers / rtc / rtc-mxc.c

/*
 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>

#include <mach/hardware.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512
static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
	{ 2,		RTC_2HZ_BIT },
	{ 4,		RTC_SAM0_BIT },
	{ 8,		RTC_SAM1_BIT },
	{ 16,		RTC_SAM2_BIT },
	{ 32,		RTC_SAM3_BIT },
	{ 64,		RTC_SAM4_BIT },
	{ 128,		RTC_SAM5_BIT },
	{ 256,		RTC_SAM6_BIT },
	{ MAX_PIE_FREQ,	RTC_SAM7_BIT },
};

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk;
	struct rtc_time g_rtc_alarm;
};

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static u32 get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return (((day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time)
{
	u32 day, hr, min, sec, temp;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = time / 86400;
	time -= day * 86400;

	/* time is within a day now */
	hr = time / 3600;
	time -= hr * 3600;

	/* time is within an hour now */
	min = time / 60;
	sec = time - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	struct rtc_time alarm_tm, now_tm;
	unsigned long now, time;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	now = get_alarm_or_time(dev, MXC_RTC_TIME);
	rtc_time_to_tm(now, &now_tm);
	alarm_tm.tm_year = now_tm.tm_year;
	alarm_tm.tm_mon = now_tm.tm_mon;
	alarm_tm.tm_mday = now_tm.tm_mday;
	alarm_tm.tm_hour = alrm->tm_hour;
	alarm_tm.tm_min = alrm->tm_min;
	alarm_tm.tm_sec = alrm->tm_sec;
	rtc_tm_to_time(&alarm_tm, &time);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);

	return 0;
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & RTC_1HZ_BIT)
		events |= (RTC_UF | RTC_IRQF);

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

/*
 * Clear all interrupts and release the IRQ
 */
static void mxc_rtc_release(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	spin_lock_irq(&pdata->rtc->irq_lock);

	/* Disable all rtc interrupts */
	writew(0, ioaddr + RTC_RTCIENR);

	/* Clear all interrupt status */
	writew(0xffffffff, ioaddr + RTC_RTCISR);

	spin_unlock_irq(&pdata->rtc->irq_lock);
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	u32 val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, unsigned long time)
{
	/*
	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	 */
	if (cpu_is_mx1()) {
		struct rtc_time tm;

		rtc_time_to_tm(time, &tm);
		tm.tm_year = 70;
		rtc_tm_to_time(&tm, &time);
	}

	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	int ret;

	ret = rtc_update_alarm(dev, &alrm->time);
	if (ret)
		return ret;

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static struct rtc_class_ops mxc_rtc_ops = {
	.release		= mxc_rtc_release,
	.read_time		= mxc_rtc_read_time,
	.set_mmss		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int __init mxc_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), pdev->name))
		return -EBUSY;

	pdata->ioaddr = devm_ioremap(&pdev->dev, res->start,
				     resource_size(res));

	pdata->clk = clk_get(&pdev->dev, "rtc");
	if (IS_ERR(pdata->clk)) {
		dev_err(&pdev->dev, "unable to get clock!\n");
		ret = PTR_ERR(pdata->clk);
		goto exit_free_pdata;
	}

	clk_enable(pdata->clk);
	rate = clk_get_rate(pdata->clk);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >=0)
		device_init_wakeup(&pdev->dev, 1);

	rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops,
				  THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		goto exit_clr_drvdata;
	}

	pdata->rtc = rtc;

	return 0;

exit_clr_drvdata:
	platform_set_drvdata(pdev, NULL);
exit_put_clk:
	clk_disable(pdata->clk);
	clk_put(pdata->clk);

exit_free_pdata:

	return ret;
}

static int __exit mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	rtc_device_unregister(pdata->rtc);

	clk_disable(pdata->clk);
	clk_put(pdata->clk);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

#ifdef CONFIG_PM
static int mxc_rtc_suspend(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pdata->irq);

	return 0;
}

static int mxc_rtc_resume(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pdata->irq);

	return 0;
}

static struct dev_pm_ops mxc_rtc_pm_ops = {
	.suspend	= mxc_rtc_suspend,
	.resume		= mxc_rtc_resume,
};
#endif

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
#ifdef CONFIG_PM
		   .pm		= &mxc_rtc_pm_ops,
#endif
		   .owner	= THIS_MODULE,
	},
	.remove		= __exit_p(mxc_rtc_remove),
};

static int __init mxc_rtc_init(void)
{
	return platform_driver_probe(&mxc_rtc_driver, mxc_rtc_probe);
}

static void __exit mxc_rtc_exit(void)
{
	platform_driver_unregister(&mxc_rtc_driver);
}

module_init(mxc_rtc_init);
module_exit(mxc_rtc_exit);

MODULE_AUTHOR("Daniel Mack <[email protected]>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
d00ed3cf DM	1	/*
	2	* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/rtc.h>
	14	#include <linux/module.h>
5a0e3ad6	15	#include <linux/slab.h>
d00ed3cf DM	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk.h>
	19
	20	#include <mach/hardware.h>
	21
	22	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	23	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	24	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	25
	26	#define RTC_SW_BIT (1 << 0)
	27	#define RTC_ALM_BIT (1 << 2)
	28	#define RTC_1HZ_BIT (1 << 4)
	29	#define RTC_2HZ_BIT (1 << 7)
	30	#define RTC_SAM0_BIT (1 << 8)
	31	#define RTC_SAM1_BIT (1 << 9)
	32	#define RTC_SAM2_BIT (1 << 10)
	33	#define RTC_SAM3_BIT (1 << 11)
	34	#define RTC_SAM4_BIT (1 << 12)
	35	#define RTC_SAM5_BIT (1 << 13)
	36	#define RTC_SAM6_BIT (1 << 14)
	37	#define RTC_SAM7_BIT (1 << 15)
	38	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	39	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	40	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	41
	42	#define RTC_ENABLE_BIT (1 << 7)
	43
	44	#define MAX_PIE_NUM 9
	45	#define MAX_PIE_FREQ 512
	46	static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
	47	{ 2, RTC_2HZ_BIT },
	48	{ 4, RTC_SAM0_BIT },
	49	{ 8, RTC_SAM1_BIT },
	50	{ 16, RTC_SAM2_BIT },
	51	{ 32, RTC_SAM3_BIT },
	52	{ 64, RTC_SAM4_BIT },
	53	{ 128, RTC_SAM5_BIT },
	54	{ 256, RTC_SAM6_BIT },
	55	{ MAX_PIE_FREQ, RTC_SAM7_BIT },
	56	};
	57
d00ed3cf DM	58	#define MXC_RTC_TIME 0
	59	#define MXC_RTC_ALARM 1
	60
	61	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	62	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	63	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	64	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	65	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	66	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	67	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	68	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	69	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	70	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	71	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	72	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	73	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	74
	75	struct rtc_plat_data {
	76	struct rtc_device *rtc;
	77	void __iomem *ioaddr;
	78	int irq;
	79	struct clk *clk;
d00ed3cf DM	80	struct rtc_time g_rtc_alarm;
	81	};
	82
	83	/*
	84	* This function is used to obtain the RTC time or the alarm value in
	85	* second.
	86	*/
	87	static u32 get_alarm_or_time(struct device *dev, int time_alarm)
	88	{
	89	struct platform_device *pdev = to_platform_device(dev);
	90	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	91	void __iomem *ioaddr = pdata->ioaddr;
	92	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	93
	94	switch (time_alarm) {
	95	case MXC_RTC_TIME:
	96	day = readw(ioaddr + RTC_DAYR);
	97	hr_min = readw(ioaddr + RTC_HOURMIN);
	98	sec = readw(ioaddr + RTC_SECOND);
	99	break;
	100	case MXC_RTC_ALARM:
	101	day = readw(ioaddr + RTC_DAYALARM);
	102	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	103	sec = readw(ioaddr + RTC_ALRM_SEC);
	104	break;
	105	}
	106
	107	hr = hr_min >> 8;
	108	min = hr_min & 0xff;
	109
	110	return (((day * 24 + hr) * 60) + min) * 60 + sec;
	111	}
	112
	113	/*
	114	* This function sets the RTC alarm value or the time value.
	115	*/
	116	static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time)
	117	{
	118	u32 day, hr, min, sec, temp;
	119	struct platform_device *pdev = to_platform_device(dev);
	120	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	121	void __iomem *ioaddr = pdata->ioaddr;
	122
	123	day = time / 86400;
	124	time -= day * 86400;
	125
	126	/* time is within a day now */
	127	hr = time / 3600;
	128	time -= hr * 3600;
	129
	130	/* time is within an hour now */
	131	min = time / 60;
	132	sec = time - min * 60;
	133
	134	temp = (hr << 8) + min;
	135
	136	switch (time_alarm) {
	137	case MXC_RTC_TIME:
	138	writew(day, ioaddr + RTC_DAYR);
	139	writew(sec, ioaddr + RTC_SECOND);
	140	writew(temp, ioaddr + RTC_HOURMIN);
	141	break;
	142	case MXC_RTC_ALARM:
	143	writew(day, ioaddr + RTC_DAYALARM);
144	writew(sec, ioaddr + RTC_ALRM_SEC);
145	writew(temp, ioaddr + RTC_ALRM_HM);
146	break;
147	}
148	}
149
150	/*
151	* This function updates the RTC alarm registers and then clears all the
152	* interrupt status bits.
153	*/
154	static int rtc_update_alarm(struct device dev, struct rtc_time alrm)
155	{
156	struct rtc_time alarm_tm, now_tm;
157	unsigned long now, time;
d00ed3cf DM	158	struct platform_device *pdev = to_platform_device(dev);
	159	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	160	void __iomem *ioaddr = pdata->ioaddr;
	161
	162	now = get_alarm_or_time(dev, MXC_RTC_TIME);
	163	rtc_time_to_tm(now, &now_tm);
	164	alarm_tm.tm_year = now_tm.tm_year;
	165	alarm_tm.tm_mon = now_tm.tm_mon;
	166	alarm_tm.tm_mday = now_tm.tm_mday;
	167	alarm_tm.tm_hour = alrm->tm_hour;
	168	alarm_tm.tm_min = alrm->tm_min;
	169	alarm_tm.tm_sec = alrm->tm_sec;
d00ed3cf DM	170	rtc_tm_to_time(&alarm_tm, &time);
d00ed3cf DM	171
d00ed3cf DM	172	/* clear all the interrupt status bits */
	173	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	174	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
	175
c92182ee YK	176	return 0;
	177	}
	178
	179	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	180	unsigned int enabled)
	181	{
	182	struct platform_device *pdev = to_platform_device(dev);
	183	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	184	void __iomem *ioaddr = pdata->ioaddr;
	185	u32 reg;
	186
	187	spin_lock_irq(&pdata->rtc->irq_lock);
	188	reg = readw(ioaddr + RTC_RTCIENR);
	189
	190	if (enabled)
	191	reg \|= bit;
	192	else
	193	reg &= ~bit;
	194
	195	writew(reg, ioaddr + RTC_RTCIENR);
	196	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	197	}
	198
	199	/* This function is the RTC interrupt service routine. */
	200	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	201	{
	202	struct platform_device *pdev = dev_id;
	203	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	204	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	205	unsigned long flags;
d00ed3cf DM	206	u32 status;
	207	u32 events = 0;
	208
b59f6d1f	209	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	210	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	211	/* clear interrupt sources */
	212	writew(status, ioaddr + RTC_RTCISR);
	213
d00ed3cf	214	/* update irq data & counter */
c92182ee	215	if (status & RTC_ALM_BIT) {
d00ed3cf	216	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	217	/* RTC alarm should be one-shot */
	218	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	219	}
d00ed3cf DM	220
	221	if (status & RTC_1HZ_BIT)
	222	events \|= (RTC_UF \| RTC_IRQF);
	223
	224	if (status & PIT_ALL_ON)
	225	events \|= (RTC_PF \| RTC_IRQF);
	226
d00ed3cf	227	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	228	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	229
	230	return IRQ_HANDLED;
	231	}
	232
	233	/*
	234	* Clear all interrupts and release the IRQ
	235	*/
	236	static void mxc_rtc_release(struct device *dev)
	237	{
	238	struct platform_device *pdev = to_platform_device(dev);
	239	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	240	void __iomem *ioaddr = pdata->ioaddr;
	241
	242	spin_lock_irq(&pdata->rtc->irq_lock);
	243
	244	/* Disable all rtc interrupts */
	245	writew(0, ioaddr + RTC_RTCIENR);
	246
	247	/* Clear all interrupt status */
	248	writew(0xffffffff, ioaddr + RTC_RTCISR);
	249
	250	spin_unlock_irq(&pdata->rtc->irq_lock);
	251	}
	252
d00ed3cf DM	253	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	254	{
	255	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	256	return 0;
	257	}
	258
d00ed3cf DM	259	/*
	260	* This function reads the current RTC time into tm in Gregorian date.
	261	*/
	262	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	263	{
	264	u32 val;
	265
	266	/* Avoid roll-over from reading the different registers */
	267	do {
	268	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	269	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	270
	271	rtc_time_to_tm(val, tm);
	272
	273	return 0;
	274	}
	275
	276	/*
	277	* This function sets the internal RTC time based on tm in Gregorian date.
	278	*/
	279	static int mxc_rtc_set_mmss(struct device *dev, unsigned long time)
	280	{
7287be1d YK	281	/*
	282	* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	283	*/
	284	if (cpu_is_mx1()) {
	285	struct rtc_time tm;
	286
	287	rtc_time_to_tm(time, &tm);
	288	tm.tm_year = 70;
	289	rtc_tm_to_time(&tm, &time);
	290	}
	291
d00ed3cf DM	292	/* Avoid roll-over from reading the different registers */
	293	do {
	294	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	295	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	296
	297	return 0;
	298	}
	299
	300	/*
	301	* This function reads the current alarm value into the passed in 'alrm'
	302	* argument. It updates the alrm's pending field value based on the whether
	303	* an alarm interrupt occurs or not.
	304	*/
	305	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	306	{
	307	struct platform_device *pdev = to_platform_device(dev);
	308	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	309	void __iomem *ioaddr = pdata->ioaddr;
	310
	311	rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	312	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	313
	314	return 0;
	315	}
	316
	317	/*
	318	* This function sets the RTC alarm based on passed in alrm.
	319	*/
	320	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	321	{
	322	struct platform_device *pdev = to_platform_device(dev);
	323	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	324	int ret;
	325
c92182ee	326	ret = rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	327	if (ret)
	328	return ret;
	329
	330	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	331	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	332
	333	return 0;
	334	}
	335
	336	/* RTC layer */
	337	static struct rtc_class_ops mxc_rtc_ops = {
	338	.release = mxc_rtc_release,
	339	.read_time = mxc_rtc_read_time,
	340	.set_mmss = mxc_rtc_set_mmss,
	341	.read_alarm = mxc_rtc_read_alarm,
	342	.set_alarm = mxc_rtc_set_alarm,
	343	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	344	};
	345
	346	static int __init mxc_rtc_probe(struct platform_device *pdev)
	347	{
d00ed3cf DM	348	struct resource *res;
	349	struct rtc_device *rtc;
	350	struct rtc_plat_data *pdata = NULL;
	351	u32 reg;
c783a29e VZ	352	unsigned long rate;
c783a29e VZ	353	int ret;
d00ed3cf DM	354
	355	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	356	if (!res)
	357	return -ENODEV;
	358
c783a29e	359	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	360	if (!pdata)
	361	return -ENOMEM;
	362
c783a29e VZ	363	if (!devm_request_mem_region(&pdev->dev, res->start,
	364	resource_size(res), pdev->name))
	365	return -EBUSY;
	366
	367	pdata->ioaddr = devm_ioremap(&pdev->dev, res->start,
	368	resource_size(res));
d00ed3cf	369
5cf8f57d VZ	370	pdata->clk = clk_get(&pdev->dev, "rtc");
	371	if (IS_ERR(pdata->clk)) {
	372	dev_err(&pdev->dev, "unable to get clock!\n");
	373	ret = PTR_ERR(pdata->clk);
49908e73 AB	374	goto exit_free_pdata;
49908e73 AB	375	}
d00ed3cf	376
5cf8f57d VZ	377	clk_enable(pdata->clk);
5cf8f57d VZ	378	rate = clk_get_rate(pdata->clk);
d00ed3cf DM	379
	380	if (rate == 32768)
	381	reg = RTC_INPUT_CLK_32768HZ;
	382	else if (rate == 32000)
	383	reg = RTC_INPUT_CLK_32000HZ;
	384	else if (rate == 38400)
	385	reg = RTC_INPUT_CLK_38400HZ;
	386	else {
c783a29e	387	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	388	ret = -EINVAL;
5cf8f57d	389	goto exit_put_clk;
d00ed3cf DM	390	}
	391
	392	reg \|= RTC_ENABLE_BIT;
	393	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	394	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	395	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	396	ret = -EIO;
5cf8f57d	397	goto exit_put_clk;
d00ed3cf DM	398	}
d00ed3cf DM	399
d00ed3cf DM	400	platform_set_drvdata(pdev, pdata);
	401
	402	/* Configure and enable the RTC */
	403	pdata->irq = platform_get_irq(pdev, 0);
	404
	405	if (pdata->irq >= 0 &&
c783a29e VZ	406	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	407	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	408	dev_warn(&pdev->dev, "interrupt not available.\n");
	409	pdata->irq = -1;
	410	}
	411
c92182ee YK	412	if (pdata->irq >=0)
	413	device_init_wakeup(&pdev->dev, 1);
	414
5f54c8a0 WS	415	rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops,
	416	THIS_MODULE);
	417	if (IS_ERR(rtc)) {
	418	ret = PTR_ERR(rtc);
	419	goto exit_clr_drvdata;
	420	}
	421
	422	pdata->rtc = rtc;
	423
d00ed3cf DM	424	return 0;
d00ed3cf DM	425
5f54c8a0 WS	426	exit_clr_drvdata:
5f54c8a0 WS	427	platform_set_drvdata(pdev, NULL);
d00ed3cf	428	exit_put_clk:
c783a29e	429	clk_disable(pdata->clk);
d00ed3cf DM	430	clk_put(pdata->clk);
	431
	432	exit_free_pdata:
d00ed3cf DM	433
	434	return ret;
	435	}
	436
	437	static int __exit mxc_rtc_remove(struct platform_device *pdev)
	438	{
	439	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	440
	441	rtc_device_unregister(pdata->rtc);
	442
d00ed3cf DM	443	clk_disable(pdata->clk);
d00ed3cf DM	444	clk_put(pdata->clk);
d00ed3cf DM	445	platform_set_drvdata(pdev, NULL);
	446
	447	return 0;
	448	}
	449
c92182ee YK	450	#ifdef CONFIG_PM
	451	static int mxc_rtc_suspend(struct device *dev)
	452	{
	453	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	454
	455	if (device_may_wakeup(dev))
	456	enable_irq_wake(pdata->irq);
	457
	458	return 0;
	459	}
	460
	461	static int mxc_rtc_resume(struct device *dev)
	462	{
	463	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	464
	465	if (device_may_wakeup(dev))
	466	disable_irq_wake(pdata->irq);
	467
	468	return 0;
	469	}
	470
	471	static struct dev_pm_ops mxc_rtc_pm_ops = {
	472	.suspend = mxc_rtc_suspend,
	473	.resume = mxc_rtc_resume,
	474	};
	475	#endif
	476
d00ed3cf DM	477	static struct platform_driver mxc_rtc_driver = {
	478	.driver = {
	479	.name = "mxc_rtc",
c92182ee YK	480	#ifdef CONFIG_PM
	481	.pm = &mxc_rtc_pm_ops,
	482	#endif
d00ed3cf DM	483	.owner = THIS_MODULE,
	484	},
	485	.remove = __exit_p(mxc_rtc_remove),
	486	};
	487
	488	static int __init mxc_rtc_init(void)
	489	{
	490	return platform_driver_probe(&mxc_rtc_driver, mxc_rtc_probe);
	491	}
	492
	493	static void __exit mxc_rtc_exit(void)
	494	{
	495	platform_driver_unregister(&mxc_rtc_driver);
	496	}
	497
	498	module_init(mxc_rtc_init);
	499	module_exit(mxc_rtc_exit);
	500
	501	MODULE_AUTHOR("Daniel Mack <[email protected]>");
	502	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	503	MODULE_LICENSE("GPL");
	504