[linux.git] / drivers / gpio / gpio-ml-ioh.c

/*
 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#define IOH_EDGE_FALLING	0
#define IOH_EDGE_RISING		BIT(0)
#define IOH_LEVEL_L		BIT(1)
#define IOH_LEVEL_H		(BIT(0) | BIT(1))
#define IOH_EDGE_BOTH		BIT(2)
#define IOH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))

#define IOH_IRQ_BASE		0

#define PCI_VENDOR_ID_ROHM             0x10DB

struct ioh_reg_comn {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im_0;
	u32	im_1;
	u32	reserved;
};

struct ioh_regs {
	struct ioh_reg_comn regs[8];
	u32 reserve1[16];
	u32 ioh_sel_reg[4];
	u32 reserve2[11];
	u32 srst;
};

/**
 * struct ioh_gpio_reg_data - The register store data.
 * @ien_reg	To store contents of interrupt enable register.
 * @imask_reg:	To store contents of interrupt mask regist
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of interrupt mode regist0
 * @im1_reg:	To store contents of interrupt mode regist1
 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
 */
struct ioh_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 use_sel_reg;
};

/**
 * struct ioh_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped IOH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @ioh_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @gpio_use_sel:		Save GPIO_USE_SEL1~4 register for PM
 * @ch:				Indicate GPIO channel
 * @irq_base:		Save base of IRQ number for interrupt
 * @spinlock:		Used for register access protection
 */
struct ioh_gpio {
	void __iomem *base;
	struct ioh_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct ioh_gpio_reg_data ioh_gpio_reg;
	u32 gpio_use_sel;
	int ch;
	int irq_base;
	spinlock_t spinlock;
};

static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};

static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	u32 reg_val;
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);

	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);

	return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
}

static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				     int val)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	u32 pm;
	u32 reg_val;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
					((1 << num_ports[chip->ch]) - 1);
	pm |= (1 << nr);
	iowrite32(pm, &chip->reg->regs[chip->ch].pm);

	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);
	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);

	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	u32 pm;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
				((1 << num_ports[chip->ch]) - 1);
	pm &= ~(1 << nr);
	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

#ifdef CONFIG_PM
/*
 * Save register configuration and disable interrupts.
 */
static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
{
	int i;

	for (i = 0; i < 8; i ++, chip++) {
		chip->ioh_gpio_reg.po_reg =
					ioread32(&chip->reg->regs[chip->ch].po);
		chip->ioh_gpio_reg.pm_reg =
					ioread32(&chip->reg->regs[chip->ch].pm);
		chip->ioh_gpio_reg.ien_reg =
				       ioread32(&chip->reg->regs[chip->ch].ien);
		chip->ioh_gpio_reg.imask_reg =
				     ioread32(&chip->reg->regs[chip->ch].imask);
		chip->ioh_gpio_reg.im0_reg =
				      ioread32(&chip->reg->regs[chip->ch].im_0);
		chip->ioh_gpio_reg.im1_reg =
				      ioread32(&chip->reg->regs[chip->ch].im_1);
		if (i < 4)
			chip->ioh_gpio_reg.use_sel_reg =
					   ioread32(&chip->reg->ioh_sel_reg[i]);
	}
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
{
	int i;

	for (i = 0; i < 8; i ++, chip++) {
		iowrite32(chip->ioh_gpio_reg.po_reg,
			  &chip->reg->regs[chip->ch].po);
		iowrite32(chip->ioh_gpio_reg.pm_reg,
			  &chip->reg->regs[chip->ch].pm);
		iowrite32(chip->ioh_gpio_reg.ien_reg,
			  &chip->reg->regs[chip->ch].ien);
		iowrite32(chip->ioh_gpio_reg.imask_reg,
			  &chip->reg->regs[chip->ch].imask);
		iowrite32(chip->ioh_gpio_reg.im0_reg,
			  &chip->reg->regs[chip->ch].im_0);
		iowrite32(chip->ioh_gpio_reg.im1_reg,
			  &chip->reg->regs[chip->ch].im_1);
		if (i < 4)
			iowrite32(chip->ioh_gpio_reg.use_sel_reg,
				  &chip->reg->ioh_sel_reg[i]);
	}
}
#endif

static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	return chip->irq_base + offset;
}

static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->owner = THIS_MODULE;
	gpio->direction_input = ioh_gpio_direction_input;
	gpio->get = ioh_gpio_get;
	gpio->direction_output = ioh_gpio_direction_output;
	gpio->set = ioh_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = -1;
	gpio->ngpio = num_port;
	gpio->can_sleep = false;
	gpio->to_irq = ioh_gpio_to_irq;
}

static int ioh_irq_type(struct irq_data *d, unsigned int type)
{
	u32 im;
	void __iomem *im_reg;
	u32 ien;
	u32 im_pos;
	int ch;
	unsigned long flags;
	u32 val;
	int irq = d->irq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	ch = irq - chip->irq_base;
	if (irq <= chip->irq_base + 7) {
		im_reg = &chip->reg->regs[chip->ch].im_0;
		im_pos = ch;
	} else {
		im_reg = &chip->reg->regs[chip->ch].im_1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
		__func__, irq, type, ch, im_pos, type);

	spin_lock_irqsave(&chip->spinlock, flags);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = IOH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = IOH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = IOH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = IOH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = IOH_LEVEL_L;
		break;
	case IRQ_TYPE_PROBE:
		goto end;
	default:
		dev_warn(chip->dev, "%s: unknown type(%dd)",
			__func__, type);
		goto end;
	}

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* iclr */
	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);

	/* IMASKCLR */
	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);

	/* Enable interrupt */
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
end:
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static void ioh_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base),
		  &chip->reg->regs[chip->ch].imaskclr);
}

static void ioh_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base),
		  &chip->reg->regs[chip->ch].imask);
}

static void ioh_irq_disable(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;
	unsigned long flags;
	u32 ien;

	spin_lock_irqsave(&chip->spinlock, flags);
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	ien &= ~(1 << (d->irq - chip->irq_base));
	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static void ioh_irq_enable(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;
	unsigned long flags;
	u32 ien;

	spin_lock_irqsave(&chip->spinlock, flags);
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	ien |= 1 << (d->irq - chip->irq_base);
	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
{
	struct ioh_gpio *chip = dev_id;
	u32 reg_val;
	int i, j;
	int ret = IRQ_NONE;

	for (i = 0; i < 8; i++, chip++) {
		reg_val = ioread32(&chip->reg->regs[i].istatus);
		for (j = 0; j < num_ports[i]; j++) {
			if (reg_val & BIT(j)) {
				dev_dbg(chip->dev,
					"%s:[%d]:irq=%d status=0x%x\n",
					__func__, j, irq, reg_val);
				iowrite32(BIT(j),
					  &chip->reg->regs[chip->ch].iclr);
				generic_handle_irq(chip->irq_base + j);
				ret = IRQ_HANDLED;
			}
		}
	}
	return ret;
}

static void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
				unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
				    handle_simple_irq);
	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_mask = ioh_irq_mask;
	ct->chip.irq_unmask = ioh_irq_unmask;
	ct->chip.irq_set_type = ioh_irq_type;
	ct->chip.irq_disable = ioh_irq_disable;
	ct->chip.irq_enable = ioh_irq_enable;

	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int ioh_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	int ret;
	int i, j;
	struct ioh_gpio *chip;
	void __iomem *base;
	void *chip_save;
	int irq_base;

	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
		goto err_pci_enable;
	}

	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
		goto err_request_regions;
	}

	base = pci_iomap(pdev, 1, 0);
	if (!base) {
		dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
		ret = -ENOMEM;
		goto err_iomap;
	}

	chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
	if (chip_save == NULL) {
		dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
		ret = -ENOMEM;
		goto err_kzalloc;
	}

	chip = chip_save;
	for (i = 0; i < 8; i++, chip++) {
		chip->dev = &pdev->dev;
		chip->base = base;
		chip->reg = chip->base;
		chip->ch = i;
		spin_lock_init(&chip->spinlock);
		ioh_gpio_setup(chip, num_ports[i]);
		ret = gpiochip_add(&chip->gpio);
		if (ret) {
			dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
			goto err_gpiochip_add;
		}
	}

	chip = chip_save;
	for (j = 0; j < 8; j++, chip++) {
		irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
					   NUMA_NO_NODE);
		if (irq_base < 0) {
			dev_warn(&pdev->dev,
				"ml_ioh_gpio: Failed to get IRQ base num\n");
			chip->irq_base = -1;
			ret = irq_base;
			goto err_irq_alloc_descs;
		}
		chip->irq_base = irq_base;
		ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
	}

	chip = chip_save;
	ret = request_irq(pdev->irq, ioh_gpio_handler,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev,
			"%s request_irq failed\n", __func__);
		goto err_request_irq;
	}

	pci_set_drvdata(pdev, chip);

	return 0;

err_request_irq:
	chip = chip_save;
err_irq_alloc_descs:
	while (--j >= 0) {
		chip--;
		irq_free_descs(chip->irq_base, num_ports[j]);
	}

	chip = chip_save;
err_gpiochip_add:
	while (--i >= 0) {
		chip--;
		gpiochip_remove(&chip->gpio);
	}
	kfree(chip_save);

err_kzalloc:
	pci_iounmap(pdev, base);

err_iomap:
	pci_release_regions(pdev);

err_request_regions:
	pci_disable_device(pdev);

err_pci_enable:

	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	return ret;
}

static void ioh_gpio_remove(struct pci_dev *pdev)
{
	int i;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	void *chip_save;

	chip_save = chip;

	free_irq(pdev->irq, chip);

	for (i = 0; i < 8; i++, chip++) {
		irq_free_descs(chip->irq_base, num_ports[i]);
		gpiochip_remove(&chip->gpio);
	}

	chip = chip_save;
	pci_iounmap(pdev, chip->base);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	kfree(chip);
}

#ifdef CONFIG_PM
static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
{
	s32 ret;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	ioh_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	ret = pci_save_state(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
		return ret;
	}
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_wake(pdev, PCI_D0, 1);
	if (ret)
		dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);

	return 0;
}

static int ioh_gpio_resume(struct pci_dev *pdev)
{
	s32 ret;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	ret = pci_enable_wake(pdev, PCI_D0, 0);

	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
		return ret;
	}
	pci_restore_state(pdev);

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->srst);
	iowrite32(0x00, &chip->reg->srst);
	ioh_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}
#else
#define ioh_gpio_suspend NULL
#define ioh_gpio_resume NULL
#endif

static const struct pci_device_id ioh_gpio_pcidev_id[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);

static struct pci_driver ioh_gpio_driver = {
	.name = "ml_ioh_gpio",
	.id_table = ioh_gpio_pcidev_id,
	.probe = ioh_gpio_probe,
	.remove = ioh_gpio_remove,
	.suspend = ioh_gpio_suspend,
	.resume = ioh_gpio_resume
};

module_pci_driver(ioh_gpio_driver);

MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
49a36793 TM	1	/*
	2	* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2 of the License.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
	16	*/
bb207ef1	17	#include <linux/module.h>
49a36793	18	#include <linux/kernel.h>
545554e7	19	#include <linux/slab.h>
49a36793 TM	20	#include <linux/pci.h>
49a36793 TM	21	#include <linux/gpio.h>
54be5663 TM	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24
	25	#define IOH_EDGE_FALLING 0
	26	#define IOH_EDGE_RISING BIT(0)
	27	#define IOH_LEVEL_L BIT(1)
	28	#define IOH_LEVEL_H (BIT(0) \| BIT(1))
	29	#define IOH_EDGE_BOTH BIT(2)
	30	#define IOH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
	31
	32	#define IOH_IRQ_BASE 0
49a36793 TM	33
	34	#define PCI_VENDOR_ID_ROHM 0x10DB
	35
	36	struct ioh_reg_comn {
	37	u32 ien;
	38	u32 istatus;
	39	u32 idisp;
	40	u32 iclr;
	41	u32 imask;
	42	u32 imaskclr;
	43	u32 po;
	44	u32 pi;
	45	u32 pm;
	46	u32 im_0;
	47	u32 im_1;
	48	u32 reserved;
	49	};
	50
	51	struct ioh_regs {
	52	struct ioh_reg_comn regs[8];
	53	u32 reserve1[16];
	54	u32 ioh_sel_reg[4];
	55	u32 reserve2[11];
	56	u32 srst;
	57	};
	58
	59	/**
	60	* struct ioh_gpio_reg_data - The register store data.
54be5663 TM	61	* @ien_reg To store contents of interrupt enable register.
54be5663 TM	62	* @imask_reg: To store contents of interrupt mask regist
49a36793 TM	63	* @po_reg: To store contents of PO register.
49a36793 TM	64	* @pm_reg: To store contents of PM register.
54be5663 TM	65	* @im0_reg: To store contents of interrupt mode regist0
54be5663 TM	66	* @im1_reg: To store contents of interrupt mode regist1
b490fa0b	67	* @use_sel_reg: To store contents of GPIO_USE_SEL0~3
49a36793 TM	68	*/
49a36793 TM	69	struct ioh_gpio_reg_data {
54be5663 TM	70	u32 ien_reg;
54be5663 TM	71	u32 imask_reg;
49a36793 TM	72	u32 po_reg;
49a36793 TM	73	u32 pm_reg;
54be5663 TM	74	u32 im0_reg;
54be5663 TM	75	u32 im1_reg;
b490fa0b	76	u32 use_sel_reg;
49a36793 TM	77	};
	78
	79	/**
	80	* struct ioh_gpio - GPIO private data structure.
	81	* @base: PCI base address of Memory mapped I/O register.
	82	* @reg: Memory mapped IOH GPIO register list.
	83	* @dev: Pointer to device structure.
	84	* @gpio: Data for GPIO infrastructure.
	85	* @ioh_gpio_reg: Memory mapped Register data is saved here
	86	* when suspend.
b490fa0b	87	* @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
49a36793	88	* @ch: Indicate GPIO channel
54be5663	89	* @irq_base: Save base of IRQ number for interrupt
02a6794d	90	* @spinlock: Used for register access protection
49a36793 TM	91	*/
	92	struct ioh_gpio {
	93	void __iomem *base;
	94	struct ioh_regs __iomem *reg;
	95	struct device *dev;
	96	struct gpio_chip gpio;
	97	struct ioh_gpio_reg_data ioh_gpio_reg;
b490fa0b	98	u32 gpio_use_sel;
49a36793	99	int ch;
54be5663 TM	100	int irq_base;
54be5663 TM	101	spinlock_t spinlock;
49a36793 TM	102	};
	103
	104	static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
	105
	106	static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	107	{
	108	u32 reg_val;
	109	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
02a6794d	110	unsigned long flags;
49a36793	111
02a6794d	112	spin_lock_irqsave(&chip->spinlock, flags);
49a36793 TM	113	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	114	if (val)
	115	reg_val \|= (1 << nr);
	116	else
	117	reg_val &= ~(1 << nr);
	118
	119	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
02a6794d	120	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	121	}
	122
	123	static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
	124	{
	125	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	126
	127	return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
	128	}
	129
	130	static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	131	int val)
	132	{
	133	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	134	u32 pm;
	135	u32 reg_val;
02a6794d	136	unsigned long flags;
49a36793	137
02a6794d	138	spin_lock_irqsave(&chip->spinlock, flags);
49a36793 TM	139	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
	140	((1 << num_ports[chip->ch]) - 1);
	141	pm \|= (1 << nr);
	142	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	143
	144	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	145	if (val)
	146	reg_val \|= (1 << nr);
	147	else
	148	reg_val &= ~(1 << nr);
ba438612	149	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
49a36793	150
02a6794d	151	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	152
	153	return 0;
	154	}
	155
	156	static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	157	{
	158	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	159	u32 pm;
02a6794d	160	unsigned long flags;
49a36793	161
02a6794d	162	spin_lock_irqsave(&chip->spinlock, flags);
49a36793 TM	163	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
	164	((1 << num_ports[chip->ch]) - 1);
	165	pm &= ~(1 << nr);
	166	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
02a6794d	167	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	168
	169	return 0;
	170	}
	171
545554e7	172	#ifdef CONFIG_PM
49a36793 TM	173	/*
	174	* Save register configuration and disable interrupts.
	175	*/
	176	static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
	177	{
b490fa0b TM	178	int i;
	179
	180	for (i = 0; i < 8; i ++, chip++) {
	181	chip->ioh_gpio_reg.po_reg =
	182	ioread32(&chip->reg->regs[chip->ch].po);
	183	chip->ioh_gpio_reg.pm_reg =
	184	ioread32(&chip->reg->regs[chip->ch].pm);
	185	chip->ioh_gpio_reg.ien_reg =
	186	ioread32(&chip->reg->regs[chip->ch].ien);
	187	chip->ioh_gpio_reg.imask_reg =
	188	ioread32(&chip->reg->regs[chip->ch].imask);
	189	chip->ioh_gpio_reg.im0_reg =
	190	ioread32(&chip->reg->regs[chip->ch].im_0);
	191	chip->ioh_gpio_reg.im1_reg =
	192	ioread32(&chip->reg->regs[chip->ch].im_1);
	193	if (i < 4)
	194	chip->ioh_gpio_reg.use_sel_reg =
	195	ioread32(&chip->reg->ioh_sel_reg[i]);
	196	}
49a36793 TM	197	}
	198
	199	/*
	200	* This function restores the register configuration of the GPIO device.
	201	*/
	202	static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
	203	{
b490fa0b TM	204	int i;
	205
	206	for (i = 0; i < 8; i ++, chip++) {
	207	iowrite32(chip->ioh_gpio_reg.po_reg,
	208	&chip->reg->regs[chip->ch].po);
	209	iowrite32(chip->ioh_gpio_reg.pm_reg,
	210	&chip->reg->regs[chip->ch].pm);
	211	iowrite32(chip->ioh_gpio_reg.ien_reg,
	212	&chip->reg->regs[chip->ch].ien);
	213	iowrite32(chip->ioh_gpio_reg.imask_reg,
	214	&chip->reg->regs[chip->ch].imask);
	215	iowrite32(chip->ioh_gpio_reg.im0_reg,
	216	&chip->reg->regs[chip->ch].im_0);
	217	iowrite32(chip->ioh_gpio_reg.im1_reg,
	218	&chip->reg->regs[chip->ch].im_1);
	219	if (i < 4)
	220	iowrite32(chip->ioh_gpio_reg.use_sel_reg,
	221	&chip->reg->ioh_sel_reg[i]);
	222	}
49a36793	223	}
545554e7	224	#endif
49a36793	225
54be5663 TM	226	static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	227	{
	228	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	229	return chip->irq_base + offset;
	230	}
	231
49a36793 TM	232	static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
	233	{
	234	struct gpio_chip *gpio = &chip->gpio;
	235
	236	gpio->label = dev_name(chip->dev);
	237	gpio->owner = THIS_MODULE;
	238	gpio->direction_input = ioh_gpio_direction_input;
	239	gpio->get = ioh_gpio_get;
	240	gpio->direction_output = ioh_gpio_direction_output;
	241	gpio->set = ioh_gpio_set;
	242	gpio->dbg_show = NULL;
	243	gpio->base = -1;
	244	gpio->ngpio = num_port;
9fb1f39e	245	gpio->can_sleep = false;
54be5663 TM	246	gpio->to_irq = ioh_gpio_to_irq;
	247	}
	248
	249	static int ioh_irq_type(struct irq_data *d, unsigned int type)
	250	{
	251	u32 im;
dd9328a6	252	void __iomem *im_reg;
54be5663 TM	253	u32 ien;
	254	u32 im_pos;
	255	int ch;
	256	unsigned long flags;
	257	u32 val;
	258	int irq = d->irq;
	259	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	260	struct ioh_gpio *chip = gc->private;
	261
	262	ch = irq - chip->irq_base;
	263	if (irq <= chip->irq_base + 7) {
	264	im_reg = &chip->reg->regs[chip->ch].im_0;
	265	im_pos = ch;
	266	} else {
	267	im_reg = &chip->reg->regs[chip->ch].im_1;
	268	im_pos = ch - 8;
	269	}
	270	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
	271	__func__, irq, type, ch, im_pos, type);
	272
	273	spin_lock_irqsave(&chip->spinlock, flags);
	274
	275	switch (type) {
	276	case IRQ_TYPE_EDGE_RISING:
	277	val = IOH_EDGE_RISING;
	278	break;
	279	case IRQ_TYPE_EDGE_FALLING:
	280	val = IOH_EDGE_FALLING;
	281	break;
	282	case IRQ_TYPE_EDGE_BOTH:
	283	val = IOH_EDGE_BOTH;
	284	break;
	285	case IRQ_TYPE_LEVEL_HIGH:
	286	val = IOH_LEVEL_H;
	287	break;
	288	case IRQ_TYPE_LEVEL_LOW:
	289	val = IOH_LEVEL_L;
	290	break;
	291	case IRQ_TYPE_PROBE:
	292	goto end;
	293	default:
	294	dev_warn(chip->dev, "%s: unknown type(%dd)",
	295	__func__, type);
	296	goto end;
	297	}
	298
	299	/* Set interrupt mode */
	300	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
	301	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	302
	303	/* iclr */
	304	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
	305
	306	/* IMASKCLR */
	307	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
	308
	309	/* Enable interrupt */
	310	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	311	iowrite32(ien \| BIT(ch), &chip->reg->regs[chip->ch].ien);
	312	end:
	313	spin_unlock_irqrestore(&chip->spinlock, flags);
	314
	315	return 0;
	316	}
317
318	static void ioh_irq_unmask(struct irq_data *d)
319	{
320	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
321	struct ioh_gpio *chip = gc->private;
322
323	iowrite32(1 << (d->irq - chip->irq_base),
324	&chip->reg->regs[chip->ch].imaskclr);
325	}
326
327	static void ioh_irq_mask(struct irq_data *d)
328	{
329	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
330	struct ioh_gpio *chip = gc->private;
331
332	iowrite32(1 << (d->irq - chip->irq_base),
333	&chip->reg->regs[chip->ch].imask);
334	}
335
4d052213 FT	336	static void ioh_irq_disable(struct irq_data *d)
	337	{
	338	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	339	struct ioh_gpio *chip = gc->private;
	340	unsigned long flags;
	341	u32 ien;
	342
	343	spin_lock_irqsave(&chip->spinlock, flags);
	344	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	345	ien &= ~(1 << (d->irq - chip->irq_base));
	346	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	347	spin_unlock_irqrestore(&chip->spinlock, flags);
	348	}
	349
	350	static void ioh_irq_enable(struct irq_data *d)
	351	{
	352	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	353	struct ioh_gpio *chip = gc->private;
	354	unsigned long flags;
	355	u32 ien;
	356
	357	spin_lock_irqsave(&chip->spinlock, flags);
	358	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	359	ien \|= 1 << (d->irq - chip->irq_base);
	360	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	361	spin_unlock_irqrestore(&chip->spinlock, flags);
	362	}
	363
54be5663 TM	364	static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
	365	{
	366	struct ioh_gpio *chip = dev_id;
	367	u32 reg_val;
	368	int i, j;
	369	int ret = IRQ_NONE;
	370
f9ea14ef	371	for (i = 0; i < 8; i++, chip++) {
54be5663 TM	372	reg_val = ioread32(&chip->reg->regs[i].istatus);
	373	for (j = 0; j < num_ports[i]; j++) {
	374	if (reg_val & BIT(j)) {
	375	dev_dbg(chip->dev,
	376	"%s:[%d]:irq=%d status=0x%x\n",
	377	__func__, j, irq, reg_val);
	378	iowrite32(BIT(j),
	379	&chip->reg->regs[chip->ch].iclr);
	380	generic_handle_irq(chip->irq_base + j);
	381	ret = IRQ_HANDLED;
	382	}
	383	}
	384	}
	385	return ret;
	386	}
	387
3836309d	388	static void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
54be5663 TM	389	unsigned int irq_start, unsigned int num)
	390	{
	391	struct irq_chip_generic *gc;
	392	struct irq_chip_type *ct;
	393
	394	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
	395	handle_simple_irq);
	396	gc->private = chip;
	397	ct = gc->chip_types;
	398
	399	ct->chip.irq_mask = ioh_irq_mask;
	400	ct->chip.irq_unmask = ioh_irq_unmask;
	401	ct->chip.irq_set_type = ioh_irq_type;
4d052213 FT	402	ct->chip.irq_disable = ioh_irq_disable;
4d052213 FT	403	ct->chip.irq_enable = ioh_irq_enable;
54be5663 TM	404
	405	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	406	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
49a36793 TM	407	}
49a36793 TM	408
3836309d	409	static int ioh_gpio_probe(struct pci_dev *pdev,
49a36793 TM	410	const struct pci_device_id *id)
	411	{
	412	int ret;
54be5663	413	int i, j;
49a36793 TM	414	struct ioh_gpio *chip;
49a36793 TM	415	void __iomem *base;
dd9328a6	416	void *chip_save;
54be5663	417	int irq_base;
49a36793 TM	418
	419	ret = pci_enable_device(pdev);
	420	if (ret) {
	421	dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
	422	goto err_pci_enable;
	423	}
	424
	425	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	426	if (ret) {
	427	dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
	428	goto err_request_regions;
	429	}
	430
	431	base = pci_iomap(pdev, 1, 0);
2bd1c85e	432	if (!base) {
49a36793 TM	433	dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
	434	ret = -ENOMEM;
	435	goto err_iomap;
	436	}
	437
	438	chip_save = kzalloc(sizeof(chip) 8, GFP_KERNEL);
	439	if (chip_save == NULL) {
	440	dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
	441	ret = -ENOMEM;
	442	goto err_kzalloc;
	443	}
	444
	445	chip = chip_save;
	446	for (i = 0; i < 8; i++, chip++) {
	447	chip->dev = &pdev->dev;
	448	chip->base = base;
	449	chip->reg = chip->base;
	450	chip->ch = i;
7e3a70fb	451	spin_lock_init(&chip->spinlock);
49a36793 TM	452	ioh_gpio_setup(chip, num_ports[i]);
	453	ret = gpiochip_add(&chip->gpio);
	454	if (ret) {
	455	dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
	456	goto err_gpiochip_add;
	457	}
	458	}
	459
	460	chip = chip_save;
54be5663 TM	461	for (j = 0; j < 8; j++, chip++) {
54be5663 TM	462	irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
a7aaa4f8	463	NUMA_NO_NODE);
54be5663 TM	464	if (irq_base < 0) {
	465	dev_warn(&pdev->dev,
	466	"ml_ioh_gpio: Failed to get IRQ base num\n");
	467	chip->irq_base = -1;
df46dce0	468	ret = irq_base;
54be5663 TM	469	goto err_irq_alloc_descs;
	470	}
	471	chip->irq_base = irq_base;
	472	ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
	473	}
	474
	475	chip = chip_save;
	476	ret = request_irq(pdev->irq, ioh_gpio_handler,
	477	IRQF_SHARED, KBUILD_MODNAME, chip);
	478	if (ret != 0) {
	479	dev_err(&pdev->dev,
	480	"%s request_irq failed\n", __func__);
	481	goto err_request_irq;
	482	}
	483
49a36793 TM	484	pci_set_drvdata(pdev, chip);
	485
	486	return 0;
	487
54be5663 TM	488	err_request_irq:
	489	chip = chip_save;
	490	err_irq_alloc_descs:
	491	while (--j >= 0) {
	492	chip--;
	493	irq_free_descs(chip->irq_base, num_ports[j]);
	494	}
	495
	496	chip = chip_save;
49a36793	497	err_gpiochip_add:
33300571	498	while (--i >= 0) {
49a36793	499	chip--;
9f5132ae	500	gpiochip_remove(&chip->gpio);
49a36793 TM	501	}
	502	kfree(chip_save);
	503
	504	err_kzalloc:
	505	pci_iounmap(pdev, base);
	506
	507	err_iomap:
	508	pci_release_regions(pdev);
	509
	510	err_request_regions:
	511	pci_disable_device(pdev);
	512
	513	err_pci_enable:
	514
	515	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	516	return ret;
	517	}
	518
206210ce	519	static void ioh_gpio_remove(struct pci_dev *pdev)
49a36793	520	{
49a36793 TM	521	int i;
49a36793 TM	522	struct ioh_gpio *chip = pci_get_drvdata(pdev);
dd9328a6	523	void *chip_save;
49a36793 TM	524
49a36793 TM	525	chip_save = chip;
54be5663 TM	526
	527	free_irq(pdev->irq, chip);
	528
49a36793	529	for (i = 0; i < 8; i++, chip++) {
54be5663	530	irq_free_descs(chip->irq_base, num_ports[i]);
9f5132ae	531	gpiochip_remove(&chip->gpio);
49a36793 TM	532	}
	533
	534	chip = chip_save;
	535	pci_iounmap(pdev, chip->base);
	536	pci_release_regions(pdev);
	537	pci_disable_device(pdev);
	538	kfree(chip);
	539	}
	540
	541	#ifdef CONFIG_PM
	542	static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
	543	{
	544	s32 ret;
	545	struct ioh_gpio *chip = pci_get_drvdata(pdev);
b490fa0b	546	unsigned long flags;
49a36793	547
b490fa0b	548	spin_lock_irqsave(&chip->spinlock, flags);
49a36793	549	ioh_gpio_save_reg_conf(chip);
b490fa0b	550	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	551
	552	ret = pci_save_state(pdev);
	553	if (ret) {
	554	dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
	555	return ret;
	556	}
	557	pci_disable_device(pdev);
	558	pci_set_power_state(pdev, PCI_D0);
	559	ret = pci_enable_wake(pdev, PCI_D0, 1);
	560	if (ret)
	561	dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
	562
	563	return 0;
	564	}
	565
	566	static int ioh_gpio_resume(struct pci_dev *pdev)
	567	{
	568	s32 ret;
	569	struct ioh_gpio *chip = pci_get_drvdata(pdev);
b490fa0b	570	unsigned long flags;
49a36793 TM	571
	572	ret = pci_enable_wake(pdev, PCI_D0, 0);
	573
	574	pci_set_power_state(pdev, PCI_D0);
	575	ret = pci_enable_device(pdev);
	576	if (ret) {
	577	dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
	578	return ret;
	579	}
	580	pci_restore_state(pdev);
	581
b490fa0b	582	spin_lock_irqsave(&chip->spinlock, flags);
49a36793 TM	583	iowrite32(0x01, &chip->reg->srst);
	584	iowrite32(0x00, &chip->reg->srst);
	585	ioh_gpio_restore_reg_conf(chip);
b490fa0b	586	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	587
	588	return 0;
	589	}
	590	#else
	591	#define ioh_gpio_suspend NULL
	592	#define ioh_gpio_resume NULL
	593	#endif
	594
14f4a883	595	static const struct pci_device_id ioh_gpio_pcidev_id[] = {
49a36793 TM	596	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
	597	{ 0, }
	598	};
19234cdd	599	MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
49a36793 TM	600
	601	static struct pci_driver ioh_gpio_driver = {
	602	.name = "ml_ioh_gpio",
	603	.id_table = ioh_gpio_pcidev_id,
	604	.probe = ioh_gpio_probe,
8283c4ff	605	.remove = ioh_gpio_remove,
49a36793 TM	606	.suspend = ioh_gpio_suspend,
	607	.resume = ioh_gpio_resume
	608	};
	609
93baa65f	610	module_pci_driver(ioh_gpio_driver);
49a36793 TM	611
	612	MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
	613	MODULE_LICENSE("GPL");