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ASoC: wm_adsp: memory leak in wm_adsp_create_control()
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
6ab2b7b4 24#include <linux/workqueue.h>
2159ad93
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/jack.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include <linux/mfd/arizona/registers.h>
34
dc91428a 35#include "arizona.h"
2159ad93
MB		 36#include "wm_adsp.h"
37
38#define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40#define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46#define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48
49#define ADSP1_CONTROL_1 0x00
50#define ADSP1_CONTROL_2 0x02
51#define ADSP1_CONTROL_3 0x03
52#define ADSP1_CONTROL_4 0x04
53#define ADSP1_CONTROL_5 0x06
54#define ADSP1_CONTROL_6 0x07
55#define ADSP1_CONTROL_7 0x08
56#define ADSP1_CONTROL_8 0x09
57#define ADSP1_CONTROL_9 0x0A
58#define ADSP1_CONTROL_10 0x0B
59#define ADSP1_CONTROL_11 0x0C
60#define ADSP1_CONTROL_12 0x0D
61#define ADSP1_CONTROL_13 0x0F
62#define ADSP1_CONTROL_14 0x10
63#define ADSP1_CONTROL_15 0x11
64#define ADSP1_CONTROL_16 0x12
65#define ADSP1_CONTROL_17 0x13
66#define ADSP1_CONTROL_18 0x14
67#define ADSP1_CONTROL_19 0x16
68#define ADSP1_CONTROL_20 0x17
69#define ADSP1_CONTROL_21 0x18
70#define ADSP1_CONTROL_22 0x1A
71#define ADSP1_CONTROL_23 0x1B
72#define ADSP1_CONTROL_24 0x1C
73#define ADSP1_CONTROL_25 0x1E
74#define ADSP1_CONTROL_26 0x20
75#define ADSP1_CONTROL_27 0x21
76#define ADSP1_CONTROL_28 0x22
77#define ADSP1_CONTROL_29 0x23
78#define ADSP1_CONTROL_30 0x24
79#define ADSP1_CONTROL_31 0x26
80
81/*
82 * ADSP1 Control 19
83 */
84#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87
88
89/*
90 * ADSP1 Control 30
91 */
92#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
100#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
104#define ADSP1_START 0x0001 /* DSP1_START */
105#define ADSP1_START_MASK 0x0001 /* DSP1_START */
106#define ADSP1_START_SHIFT 0 /* DSP1_START */
107#define ADSP1_START_WIDTH 1 /* DSP1_START */
108
94e205bf
CR		 109/*
110 * ADSP1 Control 31
111 */
112#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
114#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
115
2d30b575
MB		 116#define ADSP2_CONTROL 0x0
117#define ADSP2_CLOCKING 0x1
118#define ADSP2_STATUS1 0x4
119#define ADSP2_WDMA_CONFIG_1 0x30
120#define ADSP2_WDMA_CONFIG_2 0x31
121#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93
MB		 122
123/*
124 * ADSP2 Control
125 */
126
127#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
128#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
129#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
130#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
131#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
132#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
133#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
134#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
135#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
136#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
137#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
138#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
139#define ADSP2_START 0x0001 /* DSP1_START */
140#define ADSP2_START_MASK 0x0001 /* DSP1_START */
141#define ADSP2_START_SHIFT 0 /* DSP1_START */
142#define ADSP2_START_WIDTH 1 /* DSP1_START */
143
973838a0
MB		 144/*
145 * ADSP2 clocking
146 */
147#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
148#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
149#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
150
2159ad93
MB		 151/*
152 * ADSP2 Status 1
153 */
154#define ADSP2_RAM_RDY 0x0001
155#define ADSP2_RAM_RDY_MASK 0x0001
156#define ADSP2_RAM_RDY_SHIFT 0
157#define ADSP2_RAM_RDY_WIDTH 1
158
cf17c83c
MB		 159struct wm_adsp_buf {
160 struct list_head list;
161 void *buf;
162};
163
164static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
165 struct list_head *list)
166{
167 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
168
169 if (buf == NULL)
170 return NULL;
171
172 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
173 if (!buf->buf) {
174 kfree(buf);
175 return NULL;
176 }
177
178 if (list)
179 list_add_tail(&buf->list, list);
180
181 return buf;
182}
183
184static void wm_adsp_buf_free(struct list_head *list)
185{
186 while (!list_empty(list)) {
187 struct wm_adsp_buf *buf = list_first_entry(list,
188 struct wm_adsp_buf,
189 list);
190 list_del(&buf->list);
191 kfree(buf->buf);
192 kfree(buf);
193 }
194}
195
36e8fe99 196#define WM_ADSP_NUM_FW 4
1023dbd9 197
dd84f925
MB		 198#define WM_ADSP_FW_MBC_VSS 0
199#define WM_ADSP_FW_TX 1
200#define WM_ADSP_FW_TX_SPK 2
201#define WM_ADSP_FW_RX_ANC 3
202
1023dbd9 203static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
dd84f925
MB		 204 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
205 [WM_ADSP_FW_TX] = "Tx",
206 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
207 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
1023dbd9
MB		 208};
209
210static struct {
211 const char *file;
212} wm_adsp_fw[WM_ADSP_NUM_FW] = {
dd84f925
MB		 213 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
214 [WM_ADSP_FW_TX] = { .file = "tx" },
215 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
216 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
1023dbd9
MB		 217};
218
6ab2b7b4
DP		 219struct wm_coeff_ctl_ops {
220 int (*xget)(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *ucontrol);
222 int (*xput)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xinfo)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_info *uinfo);
226};
227
228struct wm_coeff {
229 struct device *dev;
230 struct list_head ctl_list;
231 struct regmap *regmap;
232};
233
234struct wm_coeff_ctl {
235 const char *name;
236 struct snd_card *card;
237 struct wm_adsp_alg_region region;
238 struct wm_coeff_ctl_ops ops;
239 struct wm_adsp *adsp;
240 void *private;
241 unsigned int enabled:1;
242 struct list_head list;
243 void *cache;
244 size_t len;
245 unsigned int dirty:1;
246 struct snd_kcontrol *kcontrol;
247};
248
1023dbd9
MB		 249static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
250 struct snd_ctl_elem_value *ucontrol)
251{
252 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
253 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
254 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
255
256 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
257
258 return 0;
259}
260
261static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
262 struct snd_ctl_elem_value *ucontrol)
263{
264 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
265 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
266 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
267
268 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
269 return 0;
270
271 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
272 return -EINVAL;
273
274 if (adsp[e->shift_l].running)
275 return -EBUSY;
276
31522764 277 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9
MB		 278
279 return 0;
280}
281
282static const struct soc_enum wm_adsp_fw_enum[] = {
283 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
284 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
285 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
286 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
287};
288
b6ed61cf 289const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
1023dbd9
MB		 290 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
291 wm_adsp_fw_get, wm_adsp_fw_put),
292 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
293 wm_adsp_fw_get, wm_adsp_fw_put),
294 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
295 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf
MB		 296};
297EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
298
299#if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
300static const struct soc_enum wm_adsp2_rate_enum[] = {
dc91428a
MB		 301 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
302 ARIZONA_DSP1_RATE_SHIFT, 0xf,
303 ARIZONA_RATE_ENUM_SIZE,
304 arizona_rate_text, arizona_rate_val),
305 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
306 ARIZONA_DSP1_RATE_SHIFT, 0xf,
307 ARIZONA_RATE_ENUM_SIZE,
308 arizona_rate_text, arizona_rate_val),
309 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
310 ARIZONA_DSP1_RATE_SHIFT, 0xf,
311 ARIZONA_RATE_ENUM_SIZE,
312 arizona_rate_text, arizona_rate_val),
313 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
314 ARIZONA_DSP1_RATE_SHIFT, 0xf,
315 ARIZONA_RATE_ENUM_SIZE,
316 arizona_rate_text, arizona_rate_val),
317};
318
b6ed61cf 319const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
1023dbd9
MB		 320 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
321 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 322 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
1023dbd9
MB		 323 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
324 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 325 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
1023dbd9
MB		 326 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
327 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 328 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
1023dbd9
MB		 329 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
330 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 331 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
1023dbd9 332};
b6ed61cf
MB		 333EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
334#endif
2159ad93
MB		 335
336static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
337 int type)
338{
339 int i;
340
341 for (i = 0; i < dsp->num_mems; i++)
342 if (dsp->mem[i].type == type)
343 return &dsp->mem[i];
344
345 return NULL;
346}
347
45b9ee72
MB		 348static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
349 unsigned int offset)
350{
351 switch (region->type) {
352 case WMFW_ADSP1_PM:
353 return region->base + (offset * 3);
354 case WMFW_ADSP1_DM:
355 return region->base + (offset * 2);
356 case WMFW_ADSP2_XM:
357 return region->base + (offset * 2);
358 case WMFW_ADSP2_YM:
359 return region->base + (offset * 2);
360 case WMFW_ADSP1_ZM:
361 return region->base + (offset * 2);
362 default:
363 WARN_ON(NULL != "Unknown memory region type");
364 return offset;
365 }
366}
367
6ab2b7b4
DP		 368static int wm_coeff_info(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_info *uinfo)
370{
371 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
372
373 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
374 uinfo->count = ctl->len;
375 return 0;
376}
377
378static int wm_coeff_write_control(struct snd_kcontrol *kcontrol,
379 const void *buf, size_t len)
380{
381 struct wm_coeff *wm_coeff= snd_kcontrol_chip(kcontrol);
382 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
383 struct wm_adsp_alg_region *region = &ctl->region;
384 const struct wm_adsp_region *mem;
385 struct wm_adsp *adsp = ctl->adsp;
386 void *scratch;
387 int ret;
388 unsigned int reg;
389
390 mem = wm_adsp_find_region(adsp, region->type);
391 if (!mem) {
392 adsp_err(adsp, "No base for region %x\n",
393 region->type);
394 return -EINVAL;
395 }
396
397 reg = ctl->region.base;
398 reg = wm_adsp_region_to_reg(mem, reg);
399
400 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
401 if (!scratch)
402 return -ENOMEM;
403
404 ret = regmap_raw_write(wm_coeff->regmap, reg, scratch,
405 ctl->len);
406 if (ret) {
407 adsp_err(adsp, "Failed to write %zu bytes to %x\n",
408 ctl->len, reg);
409 kfree(scratch);
410 return ret;
411 }
412
413 kfree(scratch);
414
415 return 0;
416}
417
418static int wm_coeff_put(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
422 char *p = ucontrol->value.bytes.data;
423
424 memcpy(ctl->cache, p, ctl->len);
425
426 if (!ctl->enabled) {
427 ctl->dirty = 1;
428 return 0;
429 }
430
431 return wm_coeff_write_control(kcontrol, p, ctl->len);
432}
433
434static int wm_coeff_read_control(struct snd_kcontrol *kcontrol,
435 void *buf, size_t len)
436{
437 struct wm_coeff *wm_coeff= snd_kcontrol_chip(kcontrol);
438 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
439 struct wm_adsp_alg_region *region = &ctl->region;
440 const struct wm_adsp_region *mem;
441 struct wm_adsp *adsp = ctl->adsp;
442 void *scratch;
443 int ret;
444 unsigned int reg;
445
446 mem = wm_adsp_find_region(adsp, region->type);
447 if (!mem) {
448 adsp_err(adsp, "No base for region %x\n",
449 region->type);
450 return -EINVAL;
451 }
452
453 reg = ctl->region.base;
454 reg = wm_adsp_region_to_reg(mem, reg);
455
456 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
457 if (!scratch)
458 return -ENOMEM;
459
460 ret = regmap_raw_read(wm_coeff->regmap, reg, scratch, ctl->len);
461 if (ret) {
462 adsp_err(adsp, "Failed to read %zu bytes from %x\n",
463 ctl->len, reg);
464 kfree(scratch);
465 return ret;
466 }
467
468 memcpy(buf, scratch, ctl->len);
469 kfree(scratch);
470
471 return 0;
472}
473
474static int wm_coeff_get(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
476{
477 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
478 char *p = ucontrol->value.bytes.data;
479
480 memcpy(p, ctl->cache, ctl->len);
481 return 0;
482}
483
484static int wm_coeff_add_kcontrol(struct wm_coeff *wm_coeff,
485 struct wm_coeff_ctl *ctl,
486 const struct snd_kcontrol_new *kctl)
487{
488 int ret;
489 struct snd_kcontrol *kcontrol;
490
491 kcontrol = snd_ctl_new1(kctl, wm_coeff);
492 ret = snd_ctl_add(ctl->card, kcontrol);
493 if (ret < 0) {
494 dev_err(wm_coeff->dev, "Failed to add %s: %d\n",
495 kctl->name, ret);
496 return ret;
497 }
498 ctl->kcontrol = kcontrol;
499 return 0;
500}
501
502struct wmfw_ctl_work {
503 struct wm_coeff *wm_coeff;
504 struct wm_coeff_ctl *ctl;
505 struct work_struct work;
506};
507
508static int wmfw_add_ctl(struct wm_coeff *wm_coeff,
509 struct wm_coeff_ctl *ctl)
510{
511 struct snd_kcontrol_new *kcontrol;
512 int ret;
513
514 if (!wm_coeff || !ctl || !ctl->name || !ctl->card)
515 return -EINVAL;
516
517 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
518 if (!kcontrol)
519 return -ENOMEM;
520 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
521
522 kcontrol->name = ctl->name;
523 kcontrol->info = wm_coeff_info;
524 kcontrol->get = wm_coeff_get;
525 kcontrol->put = wm_coeff_put;
526 kcontrol->private_value = (unsigned long)ctl;
527
528 ret = wm_coeff_add_kcontrol(wm_coeff,
529 ctl, kcontrol);
530 if (ret < 0)
531 goto err_kcontrol;
532
533 kfree(kcontrol);
534
535 list_add(&ctl->list, &wm_coeff->ctl_list);
536 return 0;
537
538err_kcontrol:
539 kfree(kcontrol);
540 return ret;
541}
542
2159ad93
MB		 543static int wm_adsp_load(struct wm_adsp *dsp)
544{
cf17c83c 545 LIST_HEAD(buf_list);
2159ad93
MB		 546 const struct firmware *firmware;
547 struct regmap *regmap = dsp->regmap;
548 unsigned int pos = 0;
549 const struct wmfw_header *header;
550 const struct wmfw_adsp1_sizes *adsp1_sizes;
551 const struct wmfw_adsp2_sizes *adsp2_sizes;
552 const struct wmfw_footer *footer;
553 const struct wmfw_region *region;
554 const struct wm_adsp_region *mem;
555 const char *region_name;
556 char *file, *text;
cf17c83c 557 struct wm_adsp_buf *buf;
2159ad93
MB		 558 unsigned int reg;
559 int regions = 0;
560 int ret, offset, type, sizes;
561
562 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
563 if (file == NULL)
564 return -ENOMEM;
565
1023dbd9
MB		 566 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
567 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 568 file[PAGE_SIZE - 1] = '\0';
569
570 ret = request_firmware(&firmware, file, dsp->dev);
571 if (ret != 0) {
572 adsp_err(dsp, "Failed to request '%s'\n", file);
573 goto out;
574 }
575 ret = -EINVAL;
576
577 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
578 if (pos >= firmware->size) {
579 adsp_err(dsp, "%s: file too short, %zu bytes\n",
580 file, firmware->size);
581 goto out_fw;
582 }
583
584 header = (void*)&firmware->data[0];
585
586 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
587 adsp_err(dsp, "%s: invalid magic\n", file);
588 goto out_fw;
589 }
590
591 if (header->ver != 0) {
592 adsp_err(dsp, "%s: unknown file format %d\n",
593 file, header->ver);
594 goto out_fw;
595 }
596
597 if (header->core != dsp->type) {
598 adsp_err(dsp, "%s: invalid core %d != %d\n",
599 file, header->core, dsp->type);
600 goto out_fw;
601 }
602
603 switch (dsp->type) {
604 case WMFW_ADSP1:
605 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
606 adsp1_sizes = (void *)&(header[1]);
607 footer = (void *)&(adsp1_sizes[1]);
608 sizes = sizeof(*adsp1_sizes);
609
610 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
611 file, le32_to_cpu(adsp1_sizes->dm),
612 le32_to_cpu(adsp1_sizes->pm),
613 le32_to_cpu(adsp1_sizes->zm));
614 break;
615
616 case WMFW_ADSP2:
617 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
618 adsp2_sizes = (void *)&(header[1]);
619 footer = (void *)&(adsp2_sizes[1]);
620 sizes = sizeof(*adsp2_sizes);
621
622 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
623 file, le32_to_cpu(adsp2_sizes->xm),
624 le32_to_cpu(adsp2_sizes->ym),
625 le32_to_cpu(adsp2_sizes->pm),
626 le32_to_cpu(adsp2_sizes->zm));
627 break;
628
629 default:
630 BUG_ON(NULL == "Unknown DSP type");
631 goto out_fw;
632 }
633
634 if (le32_to_cpu(header->len) != sizeof(*header) +
635 sizes + sizeof(*footer)) {
636 adsp_err(dsp, "%s: unexpected header length %d\n",
637 file, le32_to_cpu(header->len));
638 goto out_fw;
639 }
640
641 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
642 le64_to_cpu(footer->timestamp));
643
644 while (pos < firmware->size &&
645 pos - firmware->size > sizeof(*region)) {
646 region = (void *)&(firmware->data[pos]);
647 region_name = "Unknown";
648 reg = 0;
649 text = NULL;
650 offset = le32_to_cpu(region->offset) & 0xffffff;
651 type = be32_to_cpu(region->type) & 0xff;
652 mem = wm_adsp_find_region(dsp, type);
653
654 switch (type) {
655 case WMFW_NAME_TEXT:
656 region_name = "Firmware name";
657 text = kzalloc(le32_to_cpu(region->len) + 1,
658 GFP_KERNEL);
659 break;
660 case WMFW_INFO_TEXT:
661 region_name = "Information";
662 text = kzalloc(le32_to_cpu(region->len) + 1,
663 GFP_KERNEL);
664 break;
665 case WMFW_ABSOLUTE:
666 region_name = "Absolute";
667 reg = offset;
668 break;
669 case WMFW_ADSP1_PM:
670 BUG_ON(!mem);
671 region_name = "PM";
45b9ee72 672 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 673 break;
674 case WMFW_ADSP1_DM:
675 BUG_ON(!mem);
676 region_name = "DM";
45b9ee72 677 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 678 break;
679 case WMFW_ADSP2_XM:
680 BUG_ON(!mem);
681 region_name = "XM";
45b9ee72 682 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 683 break;
684 case WMFW_ADSP2_YM:
685 BUG_ON(!mem);
686 region_name = "YM";
45b9ee72 687 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 688 break;
689 case WMFW_ADSP1_ZM:
690 BUG_ON(!mem);
691 region_name = "ZM";
45b9ee72 692 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 693 break;
694 default:
695 adsp_warn(dsp,
696 "%s.%d: Unknown region type %x at %d(%x)\n",
697 file, regions, type, pos, pos);
698 break;
699 }
700
701 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
702 regions, le32_to_cpu(region->len), offset,
703 region_name);
704
705 if (text) {
706 memcpy(text, region->data, le32_to_cpu(region->len));
707 adsp_info(dsp, "%s: %s\n", file, text);
708 kfree(text);
709 }
710
711 if (reg) {
cf17c83c
MB		 712 buf = wm_adsp_buf_alloc(region->data,
713 le32_to_cpu(region->len),
714 &buf_list);
a76fefab
MB		 715 if (!buf) {
716 adsp_err(dsp, "Out of memory\n");
717 return -ENOMEM;
718 }
719
cf17c83c
MB		 720 ret = regmap_raw_write_async(regmap, reg, buf->buf,
721 le32_to_cpu(region->len));
2159ad93
MB		 722 if (ret != 0) {
723 adsp_err(dsp,
724 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
725 file, regions,
726 le32_to_cpu(region->len), offset,
727 region_name, ret);
728 goto out_fw;
729 }
730 }
731
732 pos += le32_to_cpu(region->len) + sizeof(*region);
733 regions++;
734 }
cf17c83c
MB		 735
736 ret = regmap_async_complete(regmap);
737 if (ret != 0) {
738 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
739 goto out_fw;
740 }
741
2159ad93
MB		 742 if (pos > firmware->size)
743 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
744 file, regions, pos - firmware->size);
745
746out_fw:
cf17c83c
MB		 747 regmap_async_complete(regmap);
748 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 749 release_firmware(firmware);
750out:
751 kfree(file);
752
753 return ret;
754}
755
6ab2b7b4
DP		 756static int wm_coeff_init_control_caches(struct wm_coeff *wm_coeff)
757{
758 struct wm_coeff_ctl *ctl;
759 int ret;
760
761 list_for_each_entry(ctl, &wm_coeff->ctl_list,
762 list) {
763 if (!ctl->enabled || ctl->dirty)
764 continue;
765 ret = wm_coeff_read_control(ctl->kcontrol,
766 ctl->cache,
767 ctl->len);
768 if (ret < 0)
769 return ret;
770 }
771
772 return 0;
773}
774
775static int wm_coeff_sync_controls(struct wm_coeff *wm_coeff)
776{
777 struct wm_coeff_ctl *ctl;
778 int ret;
779
780 list_for_each_entry(ctl, &wm_coeff->ctl_list,
781 list) {
782 if (!ctl->enabled)
783 continue;
784 if (ctl->dirty) {
785 ret = wm_coeff_write_control(ctl->kcontrol,
786 ctl->cache,
787 ctl->len);
788 if (ret < 0)
789 return ret;
790 ctl->dirty = 0;
791 }
792 }
793
794 return 0;
795}
796
797static void wm_adsp_ctl_work(struct work_struct *work)
798{
799 struct wmfw_ctl_work *ctl_work = container_of(work,
800 struct wmfw_ctl_work,
801 work);
802
803 wmfw_add_ctl(ctl_work->wm_coeff, ctl_work->ctl);
804 kfree(ctl_work);
805}
806
807static int wm_adsp_create_control(struct snd_soc_codec *codec,
808 const struct wm_adsp_alg_region *region)
809
810{
811 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
812 struct wm_coeff_ctl *ctl;
813 struct wmfw_ctl_work *ctl_work;
814 char *name;
815 char *region_name;
816 int ret;
817
818 name = kmalloc(PAGE_SIZE, GFP_KERNEL);
819 if (!name)
820 return -ENOMEM;
821
822 switch (region->type) {
823 case WMFW_ADSP1_PM:
824 region_name = "PM";
825 break;
826 case WMFW_ADSP1_DM:
827 region_name = "DM";
828 break;
829 case WMFW_ADSP2_XM:
830 region_name = "XM";
831 break;
832 case WMFW_ADSP2_YM:
833 region_name = "YM";
834 break;
835 case WMFW_ADSP1_ZM:
836 region_name = "ZM";
837 break;
838 default:
9dbce044
DC		 839 ret = -EINVAL;
840 goto err_name;
6ab2b7b4
DP		 841 }
842
843 snprintf(name, PAGE_SIZE, "DSP%d %s %x",
844 dsp->num, region_name, region->alg);
845
846 list_for_each_entry(ctl, &dsp->wm_coeff->ctl_list,
847 list) {
848 if (!strcmp(ctl->name, name)) {
849 if (!ctl->enabled)
850 ctl->enabled = 1;
9dbce044 851 goto found;
6ab2b7b4
DP		 852 }
853 }
854
855 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
856 if (!ctl) {
857 ret = -ENOMEM;
858 goto err_name;
859 }
860 ctl->region = *region;
861 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
862 if (!ctl->name) {
863 ret = -ENOMEM;
864 goto err_ctl;
865 }
866 ctl->enabled = 1;
867 ctl->dirty = 0;
868 ctl->ops.xget = wm_coeff_get;
869 ctl->ops.xput = wm_coeff_put;
870 ctl->card = codec->card->snd_card;
871 ctl->adsp = dsp;
872
873 ctl->len = region->len;
874 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
875 if (!ctl->cache) {
876 ret = -ENOMEM;
877 goto err_ctl_name;
878 }
879
880 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
881 if (!ctl_work) {
882 ret = -ENOMEM;
883 goto err_ctl_cache;
884 }
885
886 ctl_work->wm_coeff = dsp->wm_coeff;
887 ctl_work->ctl = ctl;
888 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
889 schedule_work(&ctl_work->work);
890
9dbce044 891found:
6ab2b7b4
DP		 892 kfree(name);
893
894 return 0;
895
896err_ctl_cache:
897 kfree(ctl->cache);
898err_ctl_name:
899 kfree(ctl->name);
900err_ctl:
901 kfree(ctl);
902err_name:
903 kfree(name);
904 return ret;
905}
906
907static int wm_adsp_setup_algs(struct wm_adsp *dsp, struct snd_soc_codec *codec)
db40517c
MB		 908{
909 struct regmap *regmap = dsp->regmap;
910 struct wmfw_adsp1_id_hdr adsp1_id;
911 struct wmfw_adsp2_id_hdr adsp2_id;
912 struct wmfw_adsp1_alg_hdr *adsp1_alg;
913 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 914 void *alg, *buf;
471f4885 915 struct wm_adsp_alg_region *region;
db40517c
MB		 916 const struct wm_adsp_region *mem;
917 unsigned int pos, term;
d62f4bc6 918 size_t algs, buf_size;
db40517c
MB		 919 __be32 val;
920 int i, ret;
921
922 switch (dsp->type) {
923 case WMFW_ADSP1:
924 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
925 break;
926 case WMFW_ADSP2:
927 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
928 break;
929 default:
930 mem = NULL;
931 break;
932 }
933
934 if (mem == NULL) {
935 BUG_ON(mem != NULL);
936 return -EINVAL;
937 }
938
939 switch (dsp->type) {
940 case WMFW_ADSP1:
941 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
942 sizeof(adsp1_id));
943 if (ret != 0) {
944 adsp_err(dsp, "Failed to read algorithm info: %d\n",
945 ret);
946 return ret;
947 }
948
d62f4bc6
MB		 949 buf = &adsp1_id;
950 buf_size = sizeof(adsp1_id);
951
db40517c 952 algs = be32_to_cpu(adsp1_id.algs);
f395a218 953 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
db40517c 954 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
f395a218 955 dsp->fw_id,
db40517c
MB		 956 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
957 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
958 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
959 algs);
960
ac50009f
MB		 961 region = kzalloc(sizeof(*region), GFP_KERNEL);
962 if (!region)
963 return -ENOMEM;
964 region->type = WMFW_ADSP1_ZM;
965 region->alg = be32_to_cpu(adsp1_id.fw.id);
966 region->base = be32_to_cpu(adsp1_id.zm);
967 list_add_tail(&region->list, &dsp->alg_regions);
968
969 region = kzalloc(sizeof(*region), GFP_KERNEL);
970 if (!region)
971 return -ENOMEM;
972 region->type = WMFW_ADSP1_DM;
973 region->alg = be32_to_cpu(adsp1_id.fw.id);
974 region->base = be32_to_cpu(adsp1_id.dm);
975 list_add_tail(&region->list, &dsp->alg_regions);
976
db40517c
MB		 977 pos = sizeof(adsp1_id) / 2;
978 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
979 break;
980
981 case WMFW_ADSP2:
982 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
983 sizeof(adsp2_id));
984 if (ret != 0) {
985 adsp_err(dsp, "Failed to read algorithm info: %d\n",
986 ret);
987 return ret;
988 }
989
d62f4bc6
MB		 990 buf = &adsp2_id;
991 buf_size = sizeof(adsp2_id);
992
db40517c 993 algs = be32_to_cpu(adsp2_id.algs);
f395a218 994 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
db40517c 995 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
f395a218 996 dsp->fw_id,
db40517c
MB		 997 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
998 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
999 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
1000 algs);
1001
ac50009f
MB		 1002 region = kzalloc(sizeof(*region), GFP_KERNEL);
1003 if (!region)
1004 return -ENOMEM;
1005 region->type = WMFW_ADSP2_XM;
1006 region->alg = be32_to_cpu(adsp2_id.fw.id);
1007 region->base = be32_to_cpu(adsp2_id.xm);
1008 list_add_tail(&region->list, &dsp->alg_regions);
1009
1010 region = kzalloc(sizeof(*region), GFP_KERNEL);
1011 if (!region)
1012 return -ENOMEM;
1013 region->type = WMFW_ADSP2_YM;
1014 region->alg = be32_to_cpu(adsp2_id.fw.id);
1015 region->base = be32_to_cpu(adsp2_id.ym);
1016 list_add_tail(&region->list, &dsp->alg_regions);
1017
1018 region = kzalloc(sizeof(*region), GFP_KERNEL);
1019 if (!region)
1020 return -ENOMEM;
1021 region->type = WMFW_ADSP2_ZM;
1022 region->alg = be32_to_cpu(adsp2_id.fw.id);
1023 region->base = be32_to_cpu(adsp2_id.zm);
1024 list_add_tail(&region->list, &dsp->alg_regions);
1025
db40517c
MB		 1026 pos = sizeof(adsp2_id) / 2;
1027 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
1028 break;
1029
1030 default:
1031 BUG_ON(NULL == "Unknown DSP type");
1032 return -EINVAL;
1033 }
1034
1035 if (algs == 0) {
1036 adsp_err(dsp, "No algorithms\n");
1037 return -EINVAL;
1038 }
1039
d62f4bc6
MB		 1040 if (algs > 1024) {
1041 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
1042 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
1043 buf, buf_size);
1044 return -EINVAL;
1045 }
1046
db40517c
MB		 1047 /* Read the terminator first to validate the length */
1048 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
1049 if (ret != 0) {
1050 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1051 ret);
1052 return ret;
1053 }
1054
1055 if (be32_to_cpu(val) != 0xbedead)
1056 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1057 term, be32_to_cpu(val));
1058
f2a93e2a 1059 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
db40517c
MB		 1060 if (!alg)
1061 return -ENOMEM;
1062
1063 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
1064 if (ret != 0) {
1065 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1066 ret);
1067 goto out;
1068 }
1069
1070 adsp1_alg = alg;
1071 adsp2_alg = alg;
1072
1073 for (i = 0; i < algs; i++) {
1074 switch (dsp->type) {
1075 case WMFW_ADSP1:
471f4885 1076 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
db40517c
MB		 1077 i, be32_to_cpu(adsp1_alg[i].alg.id),
1078 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1079 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 1080 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1081 be32_to_cpu(adsp1_alg[i].dm),
1082 be32_to_cpu(adsp1_alg[i].zm));
1083
7480800e
MB		 1084 region = kzalloc(sizeof(*region), GFP_KERNEL);
1085 if (!region)
1086 return -ENOMEM;
1087 region->type = WMFW_ADSP1_DM;
1088 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1089 region->base = be32_to_cpu(adsp1_alg[i].dm);
6ab2b7b4 1090 region->len = 0;
7480800e 1091 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1092 if (i + 1 < algs) {
1093 region->len = be32_to_cpu(adsp1_alg[i + 1].dm);
1094 region->len -= be32_to_cpu(adsp1_alg[i].dm);
1095 wm_adsp_create_control(codec, region);
1096 } else {
1097 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1098 be32_to_cpu(adsp1_alg[i].alg.id));
1099 }
471f4885 1100
7480800e
MB		 1101 region = kzalloc(sizeof(*region), GFP_KERNEL);
1102 if (!region)
1103 return -ENOMEM;
1104 region->type = WMFW_ADSP1_ZM;
1105 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1106 region->base = be32_to_cpu(adsp1_alg[i].zm);
6ab2b7b4 1107 region->len = 0;
7480800e 1108 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1109 if (i + 1 < algs) {
1110 region->len = be32_to_cpu(adsp1_alg[i + 1].zm);
1111 region->len -= be32_to_cpu(adsp1_alg[i].zm);
1112 wm_adsp_create_control(codec, region);
1113 } else {
1114 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1115 be32_to_cpu(adsp1_alg[i].alg.id));
1116 }
db40517c
MB		 1117 break;
1118
1119 case WMFW_ADSP2:
471f4885
MB		 1120 adsp_info(dsp,
1121 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
db40517c
MB		 1122 i, be32_to_cpu(adsp2_alg[i].alg.id),
1123 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1124 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 1125 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1126 be32_to_cpu(adsp2_alg[i].xm),
1127 be32_to_cpu(adsp2_alg[i].ym),
1128 be32_to_cpu(adsp2_alg[i].zm));
1129
7480800e
MB		 1130 region = kzalloc(sizeof(*region), GFP_KERNEL);
1131 if (!region)
1132 return -ENOMEM;
1133 region->type = WMFW_ADSP2_XM;
1134 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1135 region->base = be32_to_cpu(adsp2_alg[i].xm);
6ab2b7b4 1136 region->len = 0;
7480800e 1137 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1138 if (i + 1 < algs) {
1139 region->len = be32_to_cpu(adsp2_alg[i + 1].xm);
1140 region->len -= be32_to_cpu(adsp2_alg[i].xm);
1141 wm_adsp_create_control(codec, region);
1142 } else {
1143 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1144 be32_to_cpu(adsp2_alg[i].alg.id));
1145 }
471f4885 1146
7480800e
MB		 1147 region = kzalloc(sizeof(*region), GFP_KERNEL);
1148 if (!region)
1149 return -ENOMEM;
1150 region->type = WMFW_ADSP2_YM;
1151 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1152 region->base = be32_to_cpu(adsp2_alg[i].ym);
6ab2b7b4 1153 region->len = 0;
7480800e 1154 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1155 if (i + 1 < algs) {
1156 region->len = be32_to_cpu(adsp2_alg[i + 1].ym);
1157 region->len -= be32_to_cpu(adsp2_alg[i].ym);
1158 wm_adsp_create_control(codec, region);
1159 } else {
1160 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1161 be32_to_cpu(adsp2_alg[i].alg.id));
1162 }
471f4885 1163
7480800e
MB		 1164 region = kzalloc(sizeof(*region), GFP_KERNEL);
1165 if (!region)
1166 return -ENOMEM;
1167 region->type = WMFW_ADSP2_ZM;
1168 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1169 region->base = be32_to_cpu(adsp2_alg[i].zm);
6ab2b7b4 1170 region->len = 0;
7480800e 1171 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1172 if (i + 1 < algs) {
1173 region->len = be32_to_cpu(adsp2_alg[i + 1].zm);
1174 region->len -= be32_to_cpu(adsp2_alg[i].zm);
1175 wm_adsp_create_control(codec, region);
1176 } else {
1177 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1178 be32_to_cpu(adsp2_alg[i].alg.id));
1179 }
db40517c
MB		 1180 break;
1181 }
1182 }
1183
1184out:
1185 kfree(alg);
1186 return ret;
1187}
1188
2159ad93
MB		 1189static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1190{
cf17c83c 1191 LIST_HEAD(buf_list);
2159ad93
MB		 1192 struct regmap *regmap = dsp->regmap;
1193 struct wmfw_coeff_hdr *hdr;
1194 struct wmfw_coeff_item *blk;
1195 const struct firmware *firmware;
471f4885
MB		 1196 const struct wm_adsp_region *mem;
1197 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1198 const char *region_name;
1199 int ret, pos, blocks, type, offset, reg;
1200 char *file;
cf17c83c 1201 struct wm_adsp_buf *buf;
bdaacea3 1202 int tmp;
2159ad93
MB		 1203
1204 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1205 if (file == NULL)
1206 return -ENOMEM;
1207
1023dbd9
MB		 1208 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1209 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1210 file[PAGE_SIZE - 1] = '\0';
1211
1212 ret = request_firmware(&firmware, file, dsp->dev);
1213 if (ret != 0) {
1214 adsp_warn(dsp, "Failed to request '%s'\n", file);
1215 ret = 0;
1216 goto out;
1217 }
1218 ret = -EINVAL;
1219
1220 if (sizeof(*hdr) >= firmware->size) {
1221 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1222 file, firmware->size);
1223 goto out_fw;
1224 }
1225
1226 hdr = (void*)&firmware->data[0];
1227 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1228 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1229 goto out_fw;
2159ad93
MB		 1230 }
1231
c712326d
MB		 1232 switch (be32_to_cpu(hdr->rev) & 0xff) {
1233 case 1:
1234 break;
1235 default:
1236 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1237 file, be32_to_cpu(hdr->rev) & 0xff);
1238 ret = -EINVAL;
1239 goto out_fw;
1240 }
1241
2159ad93
MB		 1242 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1243 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1244 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1245 le32_to_cpu(hdr->ver) & 0xff);
1246
1247 pos = le32_to_cpu(hdr->len);
1248
1249 blocks = 0;
1250 while (pos < firmware->size &&
1251 pos - firmware->size > sizeof(*blk)) {
1252 blk = (void*)(&firmware->data[pos]);
1253
c712326d
MB		 1254 type = le16_to_cpu(blk->type);
1255 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1256
1257 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1258 file, blocks, le32_to_cpu(blk->id),
1259 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1260 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1261 le32_to_cpu(blk->ver) & 0xff);
1262 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1263 file, blocks, le32_to_cpu(blk->len), offset, type);
1264
1265 reg = 0;
1266 region_name = "Unknown";
1267 switch (type) {
c712326d
MB		 1268 case (WMFW_NAME_TEXT << 8):
1269 case (WMFW_INFO_TEXT << 8):
2159ad93 1270 break;
c712326d 1271 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1272 /*
1273 * Old files may use this for global
1274 * coefficients.
1275 */
1276 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1277 offset == 0) {
1278 region_name = "global coefficients";
1279 mem = wm_adsp_find_region(dsp, type);
1280 if (!mem) {
1281 adsp_err(dsp, "No ZM\n");
1282 break;
1283 }
1284 reg = wm_adsp_region_to_reg(mem, 0);
1285
1286 } else {
1287 region_name = "register";
1288 reg = offset;
1289 }
2159ad93 1290 break;
471f4885
MB		 1291
1292 case WMFW_ADSP1_DM:
1293 case WMFW_ADSP1_ZM:
1294 case WMFW_ADSP2_XM:
1295 case WMFW_ADSP2_YM:
1296 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1297 file, blocks, le32_to_cpu(blk->len),
1298 type, le32_to_cpu(blk->id));
1299
1300 mem = wm_adsp_find_region(dsp, type);
1301 if (!mem) {
1302 adsp_err(dsp, "No base for region %x\n", type);
1303 break;
1304 }
1305
1306 reg = 0;
1307 list_for_each_entry(alg_region,
1308 &dsp->alg_regions, list) {
1309 if (le32_to_cpu(blk->id) == alg_region->alg &&
1310 type == alg_region->type) {
338c5188 1311 reg = alg_region->base;
471f4885
MB		 1312 reg = wm_adsp_region_to_reg(mem,
1313 reg);
338c5188 1314 reg += offset;
471f4885
MB		 1315 }
1316 }
1317
1318 if (reg == 0)
1319 adsp_err(dsp, "No %x for algorithm %x\n",
1320 type, le32_to_cpu(blk->id));
1321 break;
1322
2159ad93 1323 default:
25c62f7e
MB		 1324 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1325 file, blocks, type, pos);
2159ad93
MB		 1326 break;
1327 }
1328
1329 if (reg) {
cf17c83c
MB		 1330 buf = wm_adsp_buf_alloc(blk->data,
1331 le32_to_cpu(blk->len),
1332 &buf_list);
a76fefab
MB		 1333 if (!buf) {
1334 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1335 ret = -ENOMEM;
1336 goto out_fw;
a76fefab
MB		 1337 }
1338
20da6d5a
MB		 1339 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1340 file, blocks, le32_to_cpu(blk->len),
1341 reg);
cf17c83c
MB		 1342 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1343 le32_to_cpu(blk->len));
2159ad93
MB		 1344 if (ret != 0) {
1345 adsp_err(dsp,
1346 "%s.%d: Failed to write to %x in %s\n",
1347 file, blocks, reg, region_name);
1348 }
1349 }
1350
bdaacea3
CR		 1351 tmp = le32_to_cpu(blk->len) % 4;
1352 if (tmp)
1353 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
1354 else
1355 pos += le32_to_cpu(blk->len) + sizeof(*blk);
1356
2159ad93
MB		 1357 blocks++;
1358 }
1359
cf17c83c
MB		 1360 ret = regmap_async_complete(regmap);
1361 if (ret != 0)
1362 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1363
2159ad93
MB		 1364 if (pos > firmware->size)
1365 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1366 file, blocks, pos - firmware->size);
1367
1368out_fw:
1369 release_firmware(firmware);
cf17c83c 1370 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1371out:
1372 kfree(file);
f4b82812 1373 return ret;
2159ad93
MB		 1374}
1375
5e7a7a22
MB		 1376int wm_adsp1_init(struct wm_adsp *adsp)
1377{
1378 INIT_LIST_HEAD(&adsp->alg_regions);
1379
1380 return 0;
1381}
1382EXPORT_SYMBOL_GPL(wm_adsp1_init);
1383
2159ad93
MB		 1384int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1385 struct snd_kcontrol *kcontrol,
1386 int event)
1387{
1388 struct snd_soc_codec *codec = w->codec;
1389 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1390 struct wm_adsp *dsp = &dsps[w->shift];
6ab2b7b4 1391 struct wm_coeff_ctl *ctl;
2159ad93 1392 int ret;
94e205bf 1393 int val;
2159ad93
MB		 1394
1395 switch (event) {
1396 case SND_SOC_DAPM_POST_PMU:
1397 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1398 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1399
94e205bf
CR		 1400 /*
1401 * For simplicity set the DSP clock rate to be the
1402 * SYSCLK rate rather than making it configurable.
1403 */
1404 if(dsp->sysclk_reg) {
1405 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1406 if (ret != 0) {
1407 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1408 ret);
1409 return ret;
1410 }
1411
1412 val = (val & dsp->sysclk_mask)
1413 >> dsp->sysclk_shift;
1414
1415 ret = regmap_update_bits(dsp->regmap,
1416 dsp->base + ADSP1_CONTROL_31,
1417 ADSP1_CLK_SEL_MASK, val);
1418 if (ret != 0) {
1419 adsp_err(dsp, "Failed to set clock rate: %d\n",
1420 ret);
1421 return ret;
1422 }
1423 }
1424
2159ad93
MB		 1425 ret = wm_adsp_load(dsp);
1426 if (ret != 0)
1427 goto err;
1428
6ab2b7b4 1429 ret = wm_adsp_setup_algs(dsp, codec);
db40517c
MB		 1430 if (ret != 0)
1431 goto err;
1432
2159ad93
MB		 1433 ret = wm_adsp_load_coeff(dsp);
1434 if (ret != 0)
1435 goto err;
1436
6ab2b7b4
DP		 1437 /* Initialize caches for enabled and non-dirty controls */
1438 ret = wm_coeff_init_control_caches(dsp->wm_coeff);
1439 if (ret != 0)
1440 goto err;
1441
1442 /* Sync dirty controls */
1443 ret = wm_coeff_sync_controls(dsp->wm_coeff);
1444 if (ret != 0)
1445 goto err;
1446
2159ad93
MB		 1447 /* Start the core running */
1448 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1449 ADSP1_CORE_ENA | ADSP1_START,
1450 ADSP1_CORE_ENA | ADSP1_START);
1451 break;
1452
1453 case SND_SOC_DAPM_PRE_PMD:
1454 /* Halt the core */
1455 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1456 ADSP1_CORE_ENA | ADSP1_START, 0);
1457
1458 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1459 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1460
1461 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1462 ADSP1_SYS_ENA, 0);
6ab2b7b4
DP		 1463
1464 list_for_each_entry(ctl, &dsp->wm_coeff->ctl_list,
1465 list) {
1466 ctl->enabled = 0;
1467 }
2159ad93
MB		 1468 break;
1469
1470 default:
1471 break;
1472 }
1473
1474 return 0;
1475
1476err:
1477 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1478 ADSP1_SYS_ENA, 0);
1479 return ret;
1480}
1481EXPORT_SYMBOL_GPL(wm_adsp1_event);
1482
1483static int wm_adsp2_ena(struct wm_adsp *dsp)
1484{
1485 unsigned int val;
1486 int ret, count;
1487
1488 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1489 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1490 if (ret != 0)
1491 return ret;
1492
1493 /* Wait for the RAM to start, should be near instantaneous */
1494 count = 0;
1495 do {
1496 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1497 &val);
1498 if (ret != 0)
1499 return ret;
1500 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
1501
1502 if (!(val & ADSP2_RAM_RDY)) {
1503 adsp_err(dsp, "Failed to start DSP RAM\n");
1504 return -EBUSY;
1505 }
1506
1507 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1508 adsp_info(dsp, "RAM ready after %d polls\n", count);
1509
1510 return 0;
1511}
1512
1513int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1514 struct snd_kcontrol *kcontrol, int event)
1515{
1516 struct snd_soc_codec *codec = w->codec;
1517 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1518 struct wm_adsp *dsp = &dsps[w->shift];
471f4885 1519 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 1520 struct wm_coeff_ctl *ctl;
973838a0 1521 unsigned int val;
2159ad93
MB		 1522 int ret;
1523
1524 switch (event) {
1525 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 1526 /*
1527 * For simplicity set the DSP clock rate to be the
1528 * SYSCLK rate rather than making it configurable.
1529 */
1530 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1531 if (ret != 0) {
1532 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1533 ret);
1534 return ret;
1535 }
1536 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1537 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1538
1539 ret = regmap_update_bits(dsp->regmap,
1540 dsp->base + ADSP2_CLOCKING,
1541 ADSP2_CLK_SEL_MASK, val);
1542 if (ret != 0) {
1543 adsp_err(dsp, "Failed to set clock rate: %d\n",
1544 ret);
1545 return ret;
1546 }
1547
973838a0
MB		 1548 if (dsp->dvfs) {
1549 ret = regmap_read(dsp->regmap,
1550 dsp->base + ADSP2_CLOCKING, &val);
1551 if (ret != 0) {
1552 dev_err(dsp->dev,
1553 "Failed to read clocking: %d\n", ret);
1554 return ret;
1555 }
1556
25c6fdb0 1557 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 1558 ret = regulator_enable(dsp->dvfs);
1559 if (ret != 0) {
1560 dev_err(dsp->dev,
1561 "Failed to enable supply: %d\n",
1562 ret);
1563 return ret;
1564 }
1565
1566 ret = regulator_set_voltage(dsp->dvfs,
1567 1800000,
1568 1800000);
1569 if (ret != 0) {
1570 dev_err(dsp->dev,
1571 "Failed to raise supply: %d\n",
1572 ret);
1573 return ret;
1574 }
1575 }
1576 }
1577
2159ad93
MB		 1578 ret = wm_adsp2_ena(dsp);
1579 if (ret != 0)
1580 return ret;
1581
1582 ret = wm_adsp_load(dsp);
1583 if (ret != 0)
1584 goto err;
1585
6ab2b7b4 1586 ret = wm_adsp_setup_algs(dsp, codec);
db40517c
MB		 1587 if (ret != 0)
1588 goto err;
1589
2159ad93
MB		 1590 ret = wm_adsp_load_coeff(dsp);
1591 if (ret != 0)
1592 goto err;
1593
6ab2b7b4
DP		 1594 /* Initialize caches for enabled and non-dirty controls */
1595 ret = wm_coeff_init_control_caches(dsp->wm_coeff);
1596 if (ret != 0)
1597 goto err;
1598
1599 /* Sync dirty controls */
1600 ret = wm_coeff_sync_controls(dsp->wm_coeff);
1601 if (ret != 0)
1602 goto err;
1603
2159ad93
MB		 1604 ret = regmap_update_bits(dsp->regmap,
1605 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1606 ADSP2_CORE_ENA | ADSP2_START,
1607 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 1608 if (ret != 0)
1609 goto err;
1023dbd9
MB		 1610
1611 dsp->running = true;
2159ad93
MB		 1612 break;
1613
1614 case SND_SOC_DAPM_PRE_PMD:
1023dbd9
MB		 1615 dsp->running = false;
1616
2159ad93 1617 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1618 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1619 ADSP2_START, 0);
973838a0 1620
2d30b575
MB		 1621 /* Make sure DMAs are quiesced */
1622 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1623 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1624 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1625
973838a0
MB		 1626 if (dsp->dvfs) {
1627 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1628 1800000);
1629 if (ret != 0)
1630 dev_warn(dsp->dev,
1631 "Failed to lower supply: %d\n",
1632 ret);
1633
1634 ret = regulator_disable(dsp->dvfs);
1635 if (ret != 0)
1636 dev_err(dsp->dev,
1637 "Failed to enable supply: %d\n",
1638 ret);
1639 }
471f4885 1640
6ab2b7b4
DP		 1641 list_for_each_entry(ctl, &dsp->wm_coeff->ctl_list,
1642 list) {
1643 ctl->enabled = 0;
1644 }
1645
471f4885
MB		 1646 while (!list_empty(&dsp->alg_regions)) {
1647 alg_region = list_first_entry(&dsp->alg_regions,
1648 struct wm_adsp_alg_region,
1649 list);
1650 list_del(&alg_region->list);
1651 kfree(alg_region);
1652 }
2159ad93
MB		 1653 break;
1654
1655 default:
1656 break;
1657 }
1658
1659 return 0;
1660err:
1661 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 1662 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 1663 return ret;
1664}
1665EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 1666
1667int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1668{
1669 int ret;
1670
10a2b662
MB		 1671 /*
1672 * Disable the DSP memory by default when in reset for a small
1673 * power saving.
1674 */
1675 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1676 ADSP2_MEM_ENA, 0);
1677 if (ret != 0) {
1678 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1679 return ret;
1680 }
1681
471f4885
MB		 1682 INIT_LIST_HEAD(&adsp->alg_regions);
1683
6ab2b7b4
DP		 1684 adsp->wm_coeff = kzalloc(sizeof(*adsp->wm_coeff),
1685 GFP_KERNEL);
1686 if (!adsp->wm_coeff)
1687 return -ENOMEM;
1688 adsp->wm_coeff->regmap = adsp->regmap;
1689 adsp->wm_coeff->dev = adsp->dev;
1690 INIT_LIST_HEAD(&adsp->wm_coeff->ctl_list);
1691
973838a0
MB		 1692 if (dvfs) {
1693 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1694 if (IS_ERR(adsp->dvfs)) {
1695 ret = PTR_ERR(adsp->dvfs);
1696 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
6ab2b7b4 1697 goto out_coeff;
973838a0
MB		 1698 }
1699
1700 ret = regulator_enable(adsp->dvfs);
1701 if (ret != 0) {
1702 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1703 ret);
6ab2b7b4 1704 goto out_coeff;
973838a0
MB		 1705 }
1706
1707 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1708 if (ret != 0) {
1709 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1710 ret);
6ab2b7b4 1711 goto out_coeff;
973838a0
MB		 1712 }
1713
1714 ret = regulator_disable(adsp->dvfs);
1715 if (ret != 0) {
1716 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1717 ret);
6ab2b7b4 1718 goto out_coeff;
973838a0
MB		 1719 }
1720 }
1721
1722 return 0;
6ab2b7b4
DP		 1723
1724out_coeff:
1725 kfree(adsp->wm_coeff);
1726 return ret;
973838a0
MB		 1727}
1728EXPORT_SYMBOL_GPL(wm_adsp2_init);
Empty description
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