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1da177e4 LT |
1 | /* |
2 | * This driver adapted from Drew Eckhardt's Trantor T128 driver | |
3 | * | |
4 | * Copyright 1993, Drew Eckhardt | |
5 | * Visionary Computing | |
6 | * (Unix and Linux consulting and custom programming) | |
7 | * [email protected] | |
8 | * +1 (303) 666-5836 | |
9 | * | |
10 | * ( Based on T128 - DISTRIBUTION RELEASE 3. ) | |
11 | * | |
12 | * Modified to work with the Pro Audio Spectrum/Studio 16 | |
13 | * by John Weidman. | |
14 | * | |
15 | * | |
16 | * For more information, please consult | |
17 | * | |
18 | * Media Vision | |
19 | * (510) 770-8600 | |
20 | * (800) 348-7116 | |
1da177e4 LT |
21 | */ |
22 | ||
23 | ||
24 | #ifndef PAS16_H | |
25 | #define PAS16_H | |
26 | ||
1da177e4 LT |
27 | #define PDEBUG_INIT 0x1 |
28 | #define PDEBUG_TRANSFER 0x2 | |
29 | ||
30 | #define PAS16_DEFAULT_BASE_1 0x388 | |
31 | #define PAS16_DEFAULT_BASE_2 0x384 | |
32 | #define PAS16_DEFAULT_BASE_3 0x38c | |
33 | #define PAS16_DEFAULT_BASE_4 0x288 | |
34 | ||
35 | #define PAS16_DEFAULT_BOARD_1_IRQ 10 | |
36 | #define PAS16_DEFAULT_BOARD_2_IRQ 12 | |
37 | #define PAS16_DEFAULT_BOARD_3_IRQ 14 | |
38 | #define PAS16_DEFAULT_BOARD_4_IRQ 15 | |
39 | ||
40 | ||
41 | /* | |
42 | * The Pro Audio Spectrum boards are I/O mapped. They use a Zilog 5380 | |
43 | * SCSI controller, which is the equivalent of NCR's 5380. "Pseudo-DMA" | |
44 | * architecture is used, where a PAL drives the DMA signals on the 5380 | |
45 | * allowing fast, blind transfers with proper handshaking. | |
46 | */ | |
47 | ||
48 | ||
49 | /* The Time-out Counter register is used to safe-guard against a stuck | |
50 | * bus (in the case of RDY driven handshake) or a stuck byte (if 16-Bit | |
51 | * DMA conversion is used). The counter uses a 28.224MHz clock | |
52 | * divided by 14 as its clock source. In the case of a stuck byte in | |
53 | * the holding register, an interrupt is generated (and mixed with the | |
54 | * one with the drive) using the CD-ROM interrupt pointer. | |
55 | */ | |
56 | ||
57 | #define P_TIMEOUT_COUNTER_REG 0x4000 | |
58 | #define P_TC_DISABLE 0x80 /* Set to 0 to enable timeout int. */ | |
59 | /* Bits D6-D0 contain timeout count */ | |
60 | ||
61 | ||
62 | #define P_TIMEOUT_STATUS_REG_OFFSET 0x4001 | |
63 | #define P_TS_TIM 0x80 /* check timeout status */ | |
64 | /* Bits D6-D4 N/U */ | |
65 | #define P_TS_ARM_DRQ_INT 0x08 /* Arm DRQ Int. When set high, | |
66 | * the next rising edge will | |
67 | * cause a CD-ROM interrupt. | |
68 | * When set low, the interrupt | |
69 | * will be cleared. There is | |
70 | * no status available for | |
71 | * this interrupt. | |
72 | */ | |
73 | #define P_TS_ENABLE_TO_ERR_INTERRUPT /* Enable timeout error int. */ | |
74 | #define P_TS_ENABLE_WAIT /* Enable Wait */ | |
75 | ||
76 | #define P_TS_CT 0x01 /* clear timeout. Note: writing | |
77 | * to this register clears the | |
78 | * timeout error int. or status | |
79 | */ | |
80 | ||
81 | ||
82 | /* | |
83 | * The data register reads/writes to/from the 5380 in pseudo-DMA mode | |
84 | */ | |
85 | ||
86 | #define P_DATA_REG_OFFSET 0x5c00 /* rw */ | |
87 | ||
88 | #define P_STATUS_REG_OFFSET 0x5c01 /* ro */ | |
89 | #define P_ST_RDY 0x80 /* 5380 DDRQ Status */ | |
90 | ||
91 | #define P_IRQ_STATUS 0x5c03 | |
92 | #define P_IS_IRQ 0x80 /* DIRQ status */ | |
93 | ||
94 | #define PCB_CONFIG 0x803 | |
95 | #define MASTER_ADDRESS_PTR 0x9a01 /* Fixed position - no relo */ | |
96 | #define SYS_CONFIG_4 0x8003 | |
97 | #define WAIT_STATE 0xbc00 | |
98 | #define OPERATION_MODE_1 0xec03 | |
99 | #define IO_CONFIG_3 0xf002 | |
100 | ||
101 | ||
102 | #ifndef ASM | |
1da177e4 LT |
103 | |
104 | #ifndef CMD_PER_LUN | |
105 | #define CMD_PER_LUN 2 | |
106 | #endif | |
107 | ||
108 | #ifndef CAN_QUEUE | |
109 | #define CAN_QUEUE 32 | |
110 | #endif | |
111 | ||
1da177e4 LT |
112 | #define NCR5380_implementation_fields \ |
113 | volatile unsigned short io_port | |
114 | ||
115 | #define NCR5380_local_declare() \ | |
116 | volatile unsigned short io_port | |
117 | ||
118 | #define NCR5380_setup(instance) \ | |
119 | io_port = (instance)->io_port | |
120 | ||
121 | #define PAS16_io_port(reg) ( io_port + pas16_offset[(reg)] ) | |
122 | ||
123 | #if !(PDEBUG & PDEBUG_TRANSFER) | |
124 | #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) | |
125 | #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) ) | |
126 | #else | |
127 | #define NCR5380_read(reg) \ | |
128 | (((unsigned char) printk("scsi%d : read register %d at io_port %04x\n"\ | |
129 | , instance->hostno, (reg), PAS16_io_port(reg))), inb( PAS16_io_port(reg)) ) | |
130 | ||
131 | #define NCR5380_write(reg, value) \ | |
132 | (printk("scsi%d : write %02x to register %d at io_port %04x\n", \ | |
133 | instance->hostno, (value), (reg), PAS16_io_port(reg)), \ | |
134 | outb( (value),PAS16_io_port(reg) ) ) | |
135 | ||
136 | #endif | |
137 | ||
138 | ||
139 | #define NCR5380_intr pas16_intr | |
140 | #define do_NCR5380_intr do_pas16_intr | |
141 | #define NCR5380_queue_command pas16_queue_command | |
142 | #define NCR5380_abort pas16_abort | |
1da177e4 | 143 | #define NCR5380_bus_reset pas16_bus_reset |
8c32513b | 144 | #define NCR5380_info pas16_info |
dd7ab71b AV |
145 | #define NCR5380_show_info pas16_show_info |
146 | #define NCR5380_write_info pas16_write_info | |
1da177e4 LT |
147 | |
148 | /* 15 14 12 10 7 5 3 | |
149 | 1101 0100 1010 1000 */ | |
150 | ||
151 | #define PAS16_IRQS 0xd4a8 | |
152 | ||
1da177e4 LT |
153 | #endif /* ndef ASM */ |
154 | #endif /* PAS16_H */ |