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qed*: Add support for QL41xxx adapters
[linux.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
CommitLineData
fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/mutex.h>
41#include <linux/pci.h>
42#include <linux/slab.h>
43#include <linux/string.h>
a91eb52a 44#include <linux/vmalloc.h>
fe56b9e6
YM		 45#include <linux/etherdevice.h>
46#include <linux/qed/qed_chain.h>
47#include <linux/qed/qed_if.h>
48#include "qed.h"
49#include "qed_cxt.h"
39651abd 50#include "qed_dcbx.h"
fe56b9e6 51#include "qed_dev_api.h"
1e128c81 52#include "qed_fcoe.h"
fe56b9e6
YM		 53#include "qed_hsi.h"
54#include "qed_hw.h"
55#include "qed_init_ops.h"
56#include "qed_int.h"
fc831825 57#include "qed_iscsi.h"
0a7fb11c 58#include "qed_ll2.h"
fe56b9e6 59#include "qed_mcp.h"
1d6cff4f 60#include "qed_ooo.h"
fe56b9e6
YM		 61#include "qed_reg_addr.h"
62#include "qed_sp.h"
32a47e72 63#include "qed_sriov.h"
0b55e27d 64#include "qed_vf.h"
51ff1725 65#include "qed_roce.h"
fe56b9e6 66
0caf5b26 67static DEFINE_SPINLOCK(qm_lock);
39651abd 68
51ff1725
RA		 69#define QED_MIN_DPIS (4)
70#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
71
fe56b9e6 72/* API common to all protocols */
c2035eea
RA		 73enum BAR_ID {
74 BAR_ID_0, /* used for GRC */
75 BAR_ID_1 /* Used for doorbells */
76};
77
1a635e48 78static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
c2035eea 79{
1408cc1f
YM		 80 u32 bar_reg = (bar_id == BAR_ID_0 ?
81 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
82 u32 val;
c2035eea 83
1408cc1f
YM		 84 if (IS_VF(p_hwfn->cdev))
85 return 1 << 17;
86
87 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
c2035eea
RA		 88 if (val)
89 return 1 << (val + 15);
90
91 /* Old MFW initialized above registered only conditionally */
92 if (p_hwfn->cdev->num_hwfns > 1) {
93 DP_INFO(p_hwfn,
94 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
95 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
96 } else {
97 DP_INFO(p_hwfn,
98 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
99 return 512 * 1024;
100 }
101}
102
1a635e48 103void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
fe56b9e6
YM		 104{
105 u32 i;
106
107 cdev->dp_level = dp_level;
108 cdev->dp_module = dp_module;
109 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
110 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
111
112 p_hwfn->dp_level = dp_level;
113 p_hwfn->dp_module = dp_module;
114 }
115}
116
117void qed_init_struct(struct qed_dev *cdev)
118{
119 u8 i;
120
121 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
122 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
123
124 p_hwfn->cdev = cdev;
125 p_hwfn->my_id = i;
126 p_hwfn->b_active = false;
127
128 mutex_init(&p_hwfn->dmae_info.mutex);
129 }
130
131 /* hwfn 0 is always active */
132 cdev->hwfns[0].b_active = true;
133
134 /* set the default cache alignment to 128 */
135 cdev->cache_shift = 7;
136}
137
138static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
139{
140 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
141
142 kfree(qm_info->qm_pq_params);
143 qm_info->qm_pq_params = NULL;
144 kfree(qm_info->qm_vport_params);
145 qm_info->qm_vport_params = NULL;
146 kfree(qm_info->qm_port_params);
147 qm_info->qm_port_params = NULL;
bcd197c8
MC		 148 kfree(qm_info->wfq_data);
149 qm_info->wfq_data = NULL;
fe56b9e6
YM		 150}
151
152void qed_resc_free(struct qed_dev *cdev)
153{
154 int i;
155
1408cc1f
YM		 156 if (IS_VF(cdev))
157 return;
158
fe56b9e6
YM		 159 kfree(cdev->fw_data);
160 cdev->fw_data = NULL;
161
162 kfree(cdev->reset_stats);
163
164 for_each_hwfn(cdev, i) {
165 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
166
167 qed_cxt_mngr_free(p_hwfn);
168 qed_qm_info_free(p_hwfn);
169 qed_spq_free(p_hwfn);
170 qed_eq_free(p_hwfn, p_hwfn->p_eq);
171 qed_consq_free(p_hwfn, p_hwfn->p_consq);
172 qed_int_free(p_hwfn);
0a7fb11c
YM		 173#ifdef CONFIG_QED_LL2
174 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
175#endif
1e128c81
AE		 176 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
177 qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info);
178
1d6cff4f 179 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 180 qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 181 qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
182 }
32a47e72 183 qed_iov_free(p_hwfn);
fe56b9e6 184 qed_dmae_info_free(p_hwfn);
39651abd 185 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
fe56b9e6
YM		 186 }
187}
188
79529291 189static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
fe56b9e6 190{
1408cc1f 191 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
fe56b9e6
YM		 192 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
193 struct init_qm_port_params *p_qm_port;
dbb799c3
YM		 194 bool init_rdma_offload_pq = false;
195 bool init_pure_ack_pq = false;
196 bool init_ooo_pq = false;
fe56b9e6 197 u16 num_pqs, multi_cos_tcs = 1;
cc3d5eb0
YM		 198 u8 pf_wfq = qm_info->pf_wfq;
199 u32 pf_rl = qm_info->pf_rl;
dbb799c3 200 u16 num_pf_rls = 0;
1408cc1f 201 u16 num_vfs = 0;
fe56b9e6 202
1408cc1f
YM		 203#ifdef CONFIG_QED_SRIOV
204 if (p_hwfn->cdev->p_iov_info)
205 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
206#endif
fe56b9e6
YM		 207 memset(qm_info, 0, sizeof(*qm_info));
208
1408cc1f 209 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
fe56b9e6
YM		 210 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
211
dbb799c3
YM		 212 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
213 num_pqs++; /* for RoCE queue */
214 init_rdma_offload_pq = true;
215 /* we subtract num_vfs because each require a rate limiter,
216 * and one default rate limiter
217 */
218 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
219 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
220
221 num_pqs += num_pf_rls;
222 qm_info->num_pf_rls = (u8) num_pf_rls;
223 }
224
225 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
226 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
227 init_pure_ack_pq = true;
228 init_ooo_pq = true;
229 }
230
fe56b9e6
YM		 231 /* Sanity checking that setup requires legal number of resources */
232 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
233 DP_ERR(p_hwfn,
234 "Need too many Physical queues - 0x%04x when only %04x are available\n",
235 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
236 return -EINVAL;
237 }
238
239 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
240 */
79529291
SRK		 241 qm_info->qm_pq_params = kcalloc(num_pqs,
242 sizeof(struct init_qm_pq_params),
243 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
fe56b9e6
YM		 244 if (!qm_info->qm_pq_params)
245 goto alloc_err;
246
79529291
SRK		 247 qm_info->qm_vport_params = kcalloc(num_vports,
248 sizeof(struct init_qm_vport_params),
249 b_sleepable ? GFP_KERNEL
250 : GFP_ATOMIC);
fe56b9e6
YM		 251 if (!qm_info->qm_vport_params)
252 goto alloc_err;
253
79529291
SRK		 254 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
255 sizeof(struct init_qm_port_params),
256 b_sleepable ? GFP_KERNEL
257 : GFP_ATOMIC);
fe56b9e6
YM		 258 if (!qm_info->qm_port_params)
259 goto alloc_err;
260
79529291
SRK		 261 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
262 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
bcd197c8
MC		 263 if (!qm_info->wfq_data)
264 goto alloc_err;
265
fe56b9e6
YM		 266 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
267
dbb799c3
YM		 268 /* First init rate limited queues */
269 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
270 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
271 qm_info->qm_pq_params[curr_queue].tc_id =
272 p_hwfn->hw_info.non_offload_tc;
273 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
274 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
275 }
276
fe56b9e6 277 /* First init per-TC PQs */
39651abd 278 for (i = 0; i < multi_cos_tcs; i++) {
1408cc1f 279 struct init_qm_pq_params *params =
39651abd
SRK		 280 &qm_info->qm_pq_params[curr_queue++];
281
dbb799c3
YM		 282 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
283 p_hwfn->hw_info.personality == QED_PCI_ETH) {
39651abd
SRK		 284 params->vport_id = vport_id;
285 params->tc_id = p_hwfn->hw_info.non_offload_tc;
286 params->wrr_group = 1;
287 } else {
288 params->vport_id = vport_id;
289 params->tc_id = p_hwfn->hw_info.offload_tc;
290 params->wrr_group = 1;
291 }
fe56b9e6
YM		 292 }
293
294 /* Then init pure-LB PQ */
1408cc1f
YM		 295 qm_info->pure_lb_pq = curr_queue;
296 qm_info->qm_pq_params[curr_queue].vport_id =
297 (u8) RESC_START(p_hwfn, QED_VPORT);
298 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
299 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
300 curr_queue++;
fe56b9e6
YM		 301
302 qm_info->offload_pq = 0;
dbb799c3
YM		 303 if (init_rdma_offload_pq) {
304 qm_info->offload_pq = curr_queue;
305 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
306 qm_info->qm_pq_params[curr_queue].tc_id =
307 p_hwfn->hw_info.offload_tc;
308 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
309 curr_queue++;
310 }
311
312 if (init_pure_ack_pq) {
313 qm_info->pure_ack_pq = curr_queue;
314 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
315 qm_info->qm_pq_params[curr_queue].tc_id =
316 p_hwfn->hw_info.offload_tc;
317 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
318 curr_queue++;
319 }
320
321 if (init_ooo_pq) {
322 qm_info->ooo_pq = curr_queue;
323 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
324 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
325 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
326 curr_queue++;
327 }
328
1408cc1f
YM		 329 /* Then init per-VF PQs */
330 vf_offset = curr_queue;
331 for (i = 0; i < num_vfs; i++) {
332 /* First vport is used by the PF */
333 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
334 qm_info->qm_pq_params[curr_queue].tc_id =
335 p_hwfn->hw_info.non_offload_tc;
336 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
351a4ded 337 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
1408cc1f
YM		 338 curr_queue++;
339 }
340
341 qm_info->vf_queues_offset = vf_offset;
fe56b9e6
YM		 342 qm_info->num_pqs = num_pqs;
343 qm_info->num_vports = num_vports;
344
345 /* Initialize qm port parameters */
346 num_ports = p_hwfn->cdev->num_ports_in_engines;
347 for (i = 0; i < num_ports; i++) {
348 p_qm_port = &qm_info->qm_port_params[i];
349 p_qm_port->active = 1;
351a4ded
YM		 350 if (num_ports == 4)
351 p_qm_port->active_phys_tcs = 0x7;
352 else
353 p_qm_port->active_phys_tcs = 0x9f;
fe56b9e6
YM		 354 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
355 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
356 }
357
358 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
359
360 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
361
1408cc1f
YM		 362 qm_info->num_vf_pqs = num_vfs;
363 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
fe56b9e6 364
a64b02d5
MC		 365 for (i = 0; i < qm_info->num_vports; i++)
366 qm_info->qm_vport_params[i].vport_wfq = 1;
367
fe56b9e6 368 qm_info->vport_rl_en = 1;
a64b02d5 369 qm_info->vport_wfq_en = 1;
cc3d5eb0
YM		 370 qm_info->pf_rl = pf_rl;
371 qm_info->pf_wfq = pf_wfq;
fe56b9e6
YM		 372
373 return 0;
374
375alloc_err:
bcd197c8 376 qed_qm_info_free(p_hwfn);
fe56b9e6
YM		 377 return -ENOMEM;
378}
379
39651abd
SRK		 380/* This function reconfigures the QM pf on the fly.
381 * For this purpose we:
382 * 1. reconfigure the QM database
383 * 2. set new values to runtime arrat
384 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
385 * 4. activate init tool in QM_PF stage
386 * 5. send an sdm_qm_cmd through rbc interface to release the QM
387 */
388int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
389{
390 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
391 bool b_rc;
392 int rc;
393
394 /* qm_info is allocated in qed_init_qm_info() which is already called
395 * from qed_resc_alloc() or previous call of qed_qm_reconf().
396 * The allocated size may change each init, so we free it before next
397 * allocation.
398 */
399 qed_qm_info_free(p_hwfn);
400
401 /* initialize qed's qm data structure */
79529291 402 rc = qed_init_qm_info(p_hwfn, false);
39651abd
SRK		 403 if (rc)
404 return rc;
405
406 /* stop PF's qm queues */
407 spin_lock_bh(&qm_lock);
408 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
409 qm_info->start_pq, qm_info->num_pqs);
410 spin_unlock_bh(&qm_lock);
411 if (!b_rc)
412 return -EINVAL;
413
414 /* clear the QM_PF runtime phase leftovers from previous init */
415 qed_init_clear_rt_data(p_hwfn);
416
417 /* prepare QM portion of runtime array */
418 qed_qm_init_pf(p_hwfn);
419
420 /* activate init tool on runtime array */
421 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
422 p_hwfn->hw_info.hw_mode);
423 if (rc)
424 return rc;
425
426 /* start PF's qm queues */
427 spin_lock_bh(&qm_lock);
428 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
429 qm_info->start_pq, qm_info->num_pqs);
430 spin_unlock_bh(&qm_lock);
431 if (!b_rc)
432 return -EINVAL;
433
434 return 0;
435}
436
fe56b9e6
YM		 437int qed_resc_alloc(struct qed_dev *cdev)
438{
fc831825 439 struct qed_iscsi_info *p_iscsi_info;
1e128c81 440 struct qed_fcoe_info *p_fcoe_info;
1d6cff4f 441 struct qed_ooo_info *p_ooo_info;
0a7fb11c
YM		 442#ifdef CONFIG_QED_LL2
443 struct qed_ll2_info *p_ll2_info;
444#endif
fe56b9e6
YM		 445 struct qed_consq *p_consq;
446 struct qed_eq *p_eq;
447 int i, rc = 0;
448
1408cc1f
YM		 449 if (IS_VF(cdev))
450 return rc;
451
fe56b9e6
YM		 452 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
453 if (!cdev->fw_data)
454 return -ENOMEM;
455
456 for_each_hwfn(cdev, i) {
457 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dbb799c3 458 u32 n_eqes, num_cons;
fe56b9e6
YM		 459
460 /* First allocate the context manager structure */
461 rc = qed_cxt_mngr_alloc(p_hwfn);
462 if (rc)
463 goto alloc_err;
464
465 /* Set the HW cid/tid numbers (in the contest manager)
466 * Must be done prior to any further computations.
467 */
468 rc = qed_cxt_set_pf_params(p_hwfn);
469 if (rc)
470 goto alloc_err;
471
472 /* Prepare and process QM requirements */
79529291 473 rc = qed_init_qm_info(p_hwfn, true);
fe56b9e6
YM		 474 if (rc)
475 goto alloc_err;
476
477 /* Compute the ILT client partition */
478 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
479 if (rc)
480 goto alloc_err;
481
482 /* CID map / ILT shadow table / T2
483 * The talbes sizes are determined by the computations above
484 */
485 rc = qed_cxt_tables_alloc(p_hwfn);
486 if (rc)
487 goto alloc_err;
488
489 /* SPQ, must follow ILT because initializes SPQ context */
490 rc = qed_spq_alloc(p_hwfn);
491 if (rc)
492 goto alloc_err;
493
494 /* SP status block allocation */
495 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
496 RESERVED_PTT_DPC);
497
498 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
499 if (rc)
500 goto alloc_err;
501
32a47e72
YM		 502 rc = qed_iov_alloc(p_hwfn);
503 if (rc)
504 goto alloc_err;
505
fe56b9e6 506 /* EQ */
dbb799c3
YM		 507 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
508 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
509 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
510 PROTOCOLID_ROCE,
8c93beaf 511 NULL) * 2;
dbb799c3
YM		 512 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
513 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
514 num_cons =
515 qed_cxt_get_proto_cid_count(p_hwfn,
8c93beaf
YM		 516 PROTOCOLID_ISCSI,
517 NULL);
dbb799c3
YM		 518 n_eqes += 2 * num_cons;
519 }
520
521 if (n_eqes > 0xFFFF) {
522 DP_ERR(p_hwfn,
523 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
524 n_eqes, 0xFFFF);
1b4985b5 525 rc = -EINVAL;
fe56b9e6 526 goto alloc_err;
9b15acbf 527 }
dbb799c3
YM		 528
529 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
530 if (!p_eq)
531 goto alloc_no_mem;
fe56b9e6
YM		 532 p_hwfn->p_eq = p_eq;
533
534 p_consq = qed_consq_alloc(p_hwfn);
dbb799c3
YM		 535 if (!p_consq)
536 goto alloc_no_mem;
fe56b9e6
YM		 537 p_hwfn->p_consq = p_consq;
538
0a7fb11c
YM		 539#ifdef CONFIG_QED_LL2
540 if (p_hwfn->using_ll2) {
541 p_ll2_info = qed_ll2_alloc(p_hwfn);
542 if (!p_ll2_info)
543 goto alloc_no_mem;
544 p_hwfn->p_ll2_info = p_ll2_info;
545 }
546#endif
1e128c81
AE		 547
548 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
549 p_fcoe_info = qed_fcoe_alloc(p_hwfn);
550 if (!p_fcoe_info)
551 goto alloc_no_mem;
552 p_hwfn->p_fcoe_info = p_fcoe_info;
553 }
554
fc831825
YM		 555 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
556 p_iscsi_info = qed_iscsi_alloc(p_hwfn);
557 if (!p_iscsi_info)
558 goto alloc_no_mem;
559 p_hwfn->p_iscsi_info = p_iscsi_info;
1d6cff4f
YM		 560 p_ooo_info = qed_ooo_alloc(p_hwfn);
561 if (!p_ooo_info)
562 goto alloc_no_mem;
563 p_hwfn->p_ooo_info = p_ooo_info;
fc831825 564 }
0a7fb11c 565
fe56b9e6
YM		 566 /* DMA info initialization */
567 rc = qed_dmae_info_alloc(p_hwfn);
2591c280 568 if (rc)
fe56b9e6 569 goto alloc_err;
39651abd
SRK		 570
571 /* DCBX initialization */
572 rc = qed_dcbx_info_alloc(p_hwfn);
2591c280 573 if (rc)
39651abd 574 goto alloc_err;
fe56b9e6
YM		 575 }
576
577 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2591c280 578 if (!cdev->reset_stats)
83aeb933 579 goto alloc_no_mem;
fe56b9e6
YM		 580
581 return 0;
582
dbb799c3
YM		 583alloc_no_mem:
584 rc = -ENOMEM;
fe56b9e6
YM		 585alloc_err:
586 qed_resc_free(cdev);
587 return rc;
588}
589
590void qed_resc_setup(struct qed_dev *cdev)
591{
592 int i;
593
1408cc1f
YM		 594 if (IS_VF(cdev))
595 return;
596
fe56b9e6
YM		 597 for_each_hwfn(cdev, i) {
598 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
599
600 qed_cxt_mngr_setup(p_hwfn);
601 qed_spq_setup(p_hwfn);
602 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
603 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
604
605 /* Read shadow of current MFW mailbox */
606 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
607 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
608 p_hwfn->mcp_info->mfw_mb_cur,
609 p_hwfn->mcp_info->mfw_mb_length);
610
611 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
32a47e72
YM		 612
613 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
0a7fb11c
YM		 614#ifdef CONFIG_QED_LL2
615 if (p_hwfn->using_ll2)
616 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
617#endif
1e128c81
AE		 618 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
619 qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info);
620
1d6cff4f 621 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 622 qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 623 qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
624 }
fe56b9e6
YM		 625 }
626}
627
fe56b9e6
YM		 628#define FINAL_CLEANUP_POLL_CNT (100)
629#define FINAL_CLEANUP_POLL_TIME (10)
630int qed_final_cleanup(struct qed_hwfn *p_hwfn,
0b55e27d 631 struct qed_ptt *p_ptt, u16 id, bool is_vf)
fe56b9e6
YM		 632{
633 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
634 int rc = -EBUSY;
635
fc48b7a6
YM		 636 addr = GTT_BAR0_MAP_REG_USDM_RAM +
637 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 638
0b55e27d
YM		 639 if (is_vf)
640 id += 0x10;
641
fc48b7a6
YM		 642 command |= X_FINAL_CLEANUP_AGG_INT <<
643 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
644 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
645 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
646 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 647
648 /* Make sure notification is not set before initiating final cleanup */
649 if (REG_RD(p_hwfn, addr)) {
1a635e48
YM		 650 DP_NOTICE(p_hwfn,
651 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
fe56b9e6
YM		 652 REG_WR(p_hwfn, addr, 0);
653 }
654
655 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
656 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
657 id, command);
658
659 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
660
661 /* Poll until completion */
662 while (!REG_RD(p_hwfn, addr) && count--)
663 msleep(FINAL_CLEANUP_POLL_TIME);
664
665 if (REG_RD(p_hwfn, addr))
666 rc = 0;
667 else
668 DP_NOTICE(p_hwfn,
669 "Failed to receive FW final cleanup notification\n");
670
671 /* Cleanup afterwards */
672 REG_WR(p_hwfn, addr, 0);
673
674 return rc;
675}
676
9c79ddaa 677static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
fe56b9e6
YM		 678{
679 int hw_mode = 0;
680
9c79ddaa
MY		 681 if (QED_IS_BB_B0(p_hwfn->cdev)) {
682 hw_mode |= 1 << MODE_BB;
683 } else if (QED_IS_AH(p_hwfn->cdev)) {
684 hw_mode |= 1 << MODE_K2;
685 } else {
686 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
687 p_hwfn->cdev->type);
688 return -EINVAL;
689 }
fe56b9e6
YM		 690
691 switch (p_hwfn->cdev->num_ports_in_engines) {
692 case 1:
693 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
694 break;
695 case 2:
696 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
697 break;
698 case 4:
699 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
700 break;
701 default:
702 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
703 p_hwfn->cdev->num_ports_in_engines);
9c79ddaa 704 return -EINVAL;
fe56b9e6
YM		 705 }
706
707 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 708 case QED_MF_DEFAULT:
709 case QED_MF_NPAR:
710 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 711 break;
fc48b7a6 712 case QED_MF_OVLAN:
fe56b9e6
YM		 713 hw_mode |= 1 << MODE_MF_SD;
714 break;
fe56b9e6 715 default:
fc48b7a6
YM		 716 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
717 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 718 }
719
720 hw_mode |= 1 << MODE_ASIC;
721
1af9dcf7
YM		 722 if (p_hwfn->cdev->num_hwfns > 1)
723 hw_mode |= 1 << MODE_100G;
724
fe56b9e6 725 p_hwfn->hw_info.hw_mode = hw_mode;
1af9dcf7
YM		 726
727 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
728 "Configuring function for hw_mode: 0x%08x\n",
729 p_hwfn->hw_info.hw_mode);
9c79ddaa
MY		 730
731 return 0;
fe56b9e6
YM		 732}
733
734/* Init run time data for all PFs on an engine. */
735static void qed_init_cau_rt_data(struct qed_dev *cdev)
736{
737 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
738 int i, sb_id;
739
740 for_each_hwfn(cdev, i) {
741 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
742 struct qed_igu_info *p_igu_info;
743 struct qed_igu_block *p_block;
744 struct cau_sb_entry sb_entry;
745
746 p_igu_info = p_hwfn->hw_info.p_igu_info;
747
748 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
749 sb_id++) {
750 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
751 if (!p_block->is_pf)
752 continue;
753
754 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1a635e48
YM		 755 p_block->function_id, 0, 0);
756 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
fe56b9e6
YM		 757 }
758 }
759}
760
761static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1a635e48 762 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6
YM		 763{
764 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
765 struct qed_qm_common_rt_init_params params;
766 struct qed_dev *cdev = p_hwfn->cdev;
9c79ddaa 767 u8 vf_id, max_num_vfs;
dbb799c3 768 u16 num_pfs, pf_id;
1408cc1f 769 u32 concrete_fid;
fe56b9e6
YM		 770 int rc = 0;
771
772 qed_init_cau_rt_data(cdev);
773
774 /* Program GTT windows */
775 qed_gtt_init(p_hwfn);
776
777 if (p_hwfn->mcp_info) {
778 if (p_hwfn->mcp_info->func_info.bandwidth_max)
779 qm_info->pf_rl_en = 1;
780 if (p_hwfn->mcp_info->func_info.bandwidth_min)
781 qm_info->pf_wfq_en = 1;
782 }
783
784 memset(&params, 0, sizeof(params));
785 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
786 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
787 params.pf_rl_en = qm_info->pf_rl_en;
788 params.pf_wfq_en = qm_info->pf_wfq_en;
789 params.vport_rl_en = qm_info->vport_rl_en;
790 params.vport_wfq_en = qm_info->vport_wfq_en;
791 params.port_params = qm_info->qm_port_params;
792
793 qed_qm_common_rt_init(p_hwfn, &params);
794
795 qed_cxt_hw_init_common(p_hwfn);
796
797 /* Close gate from NIG to BRB/Storm; By default they are open, but
798 * we close them to prevent NIG from passing data to reset blocks.
799 * Should have been done in the ENGINE phase, but init-tool lacks
800 * proper port-pretend capabilities.
801 */
802 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
803 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
804 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
805 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
806 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
807 qed_port_unpretend(p_hwfn, p_ptt);
808
809 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1a635e48 810 if (rc)
fe56b9e6
YM		 811 return rc;
812
813 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
814 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
815
dbb799c3
YM		 816 if (QED_IS_BB(p_hwfn->cdev)) {
817 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
818 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
819 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
820 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
821 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
822 }
823 /* pretend to original PF */
824 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
825 }
fe56b9e6 826
9c79ddaa
MY		 827 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
828 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1408cc1f
YM		 829 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
830 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
831 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
05fafbfb
YM		 832 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
833 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
834 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1408cc1f
YM		 835 }
836 /* pretend to original PF */
837 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
838
fe56b9e6
YM		 839 return rc;
840}
841
51ff1725
RA		 842static int
843qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
844 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
845{
846 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
847 u32 dpi_bit_shift, dpi_count;
848 u32 min_dpis;
849
850 /* Calculate DPI size */
851 dpi_page_size_1 = QED_WID_SIZE * n_cpus;
852 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
853 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
854 dpi_page_size = roundup_pow_of_two(dpi_page_size);
855 dpi_bit_shift = ilog2(dpi_page_size / 4096);
856
857 dpi_count = pwm_region_size / dpi_page_size;
858
859 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
860 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
861
862 p_hwfn->dpi_size = dpi_page_size;
863 p_hwfn->dpi_count = dpi_count;
864
865 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
866
867 if (dpi_count < min_dpis)
868 return -EINVAL;
869
870 return 0;
871}
872
873enum QED_ROCE_EDPM_MODE {
874 QED_ROCE_EDPM_MODE_ENABLE = 0,
875 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
876 QED_ROCE_EDPM_MODE_DISABLE = 2,
877};
878
879static int
880qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
881{
882 u32 pwm_regsize, norm_regsize;
883 u32 non_pwm_conn, min_addr_reg1;
884 u32 db_bar_size, n_cpus;
885 u32 roce_edpm_mode;
886 u32 pf_dems_shift;
887 int rc = 0;
888 u8 cond;
889
890 db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1);
891 if (p_hwfn->cdev->num_hwfns > 1)
892 db_bar_size /= 2;
893
894 /* Calculate doorbell regions */
895 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
896 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
897 NULL) +
898 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
899 NULL);
900 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
901 min_addr_reg1 = norm_regsize / 4096;
902 pwm_regsize = db_bar_size - norm_regsize;
903
904 /* Check that the normal and PWM sizes are valid */
905 if (db_bar_size < norm_regsize) {
906 DP_ERR(p_hwfn->cdev,
907 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
908 db_bar_size, norm_regsize);
909 return -EINVAL;
910 }
911
912 if (pwm_regsize < QED_MIN_PWM_REGION) {
913 DP_ERR(p_hwfn->cdev,
914 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
915 pwm_regsize,
916 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
917 return -EINVAL;
918 }
919
920 /* Calculate number of DPIs */
921 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
922 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
923 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
924 /* Either EDPM is mandatory, or we are attempting to allocate a
925 * WID per CPU.
926 */
c2dedf87 927 n_cpus = num_present_cpus();
51ff1725
RA		 928 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
929 }
930
931 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
932 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
933 if (cond || p_hwfn->dcbx_no_edpm) {
934 /* Either EDPM is disabled from user configuration, or it is
935 * disabled via DCBx, or it is not mandatory and we failed to
936 * allocated a WID per CPU.
937 */
938 n_cpus = 1;
939 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
940
941 if (cond)
942 qed_rdma_dpm_bar(p_hwfn, p_ptt);
943 }
944
945 DP_INFO(p_hwfn,
946 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
947 norm_regsize,
948 pwm_regsize,
949 p_hwfn->dpi_size,
950 p_hwfn->dpi_count,
951 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
952 "disabled" : "enabled");
953
954 if (rc) {
955 DP_ERR(p_hwfn,
956 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
957 p_hwfn->dpi_count,
958 p_hwfn->pf_params.rdma_pf_params.min_dpis);
959 return -EINVAL;
960 }
961
962 p_hwfn->dpi_start_offset = norm_regsize;
963
964 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
965 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
966 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
967 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
968
969 return 0;
970}
971
fe56b9e6 972static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1a635e48 973 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6 974{
05fafbfb
YM		 975 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
976 p_hwfn->port_id, hw_mode);
fe56b9e6
YM		 977}
978
979static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
980 struct qed_ptt *p_ptt,
464f6645 981 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 982 int hw_mode,
983 bool b_hw_start,
984 enum qed_int_mode int_mode,
985 bool allow_npar_tx_switch)
986{
987 u8 rel_pf_id = p_hwfn->rel_pf_id;
988 int rc = 0;
989
990 if (p_hwfn->mcp_info) {
991 struct qed_mcp_function_info *p_info;
992
993 p_info = &p_hwfn->mcp_info->func_info;
994 if (p_info->bandwidth_min)
995 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
996
997 /* Update rate limit once we'll actually have a link */
4b01e519 998 p_hwfn->qm_info.pf_rl = 100000;
fe56b9e6
YM		 999 }
1000
1001 qed_cxt_hw_init_pf(p_hwfn);
1002
1003 qed_int_igu_init_rt(p_hwfn);
1004
1005 /* Set VLAN in NIG if needed */
1a635e48 1006 if (hw_mode & BIT(MODE_MF_SD)) {
fe56b9e6
YM		 1007 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1008 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1009 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1010 p_hwfn->hw_info.ovlan);
1011 }
1012
1013 /* Enable classification by MAC if needed */
1a635e48 1014 if (hw_mode & BIT(MODE_MF_SI)) {
fe56b9e6
YM		 1015 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1016 "Configuring TAGMAC_CLS_TYPE\n");
1017 STORE_RT_REG(p_hwfn,
1018 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1019 }
1020
1021 /* Protocl Configuration */
dbb799c3
YM		 1022 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1023 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1e128c81
AE		 1024 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1025 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
fe56b9e6
YM		 1026 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1027
1028 /* Cleanup chip from previous driver if such remains exist */
0b55e27d 1029 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1a635e48 1030 if (rc)
fe56b9e6
YM		 1031 return rc;
1032
1033 /* PF Init sequence */
1034 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1035 if (rc)
1036 return rc;
1037
1038 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1039 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1040 if (rc)
1041 return rc;
1042
1043 /* Pure runtime initializations - directly to the HW */
1044 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1045
51ff1725
RA		 1046 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1047 if (rc)
1048 return rc;
1049
fe56b9e6
YM		 1050 if (b_hw_start) {
1051 /* enable interrupts */
1052 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1053
1054 /* send function start command */
831bfb0e
YM		 1055 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1056 allow_npar_tx_switch);
1e128c81 1057 if (rc) {
fe56b9e6 1058 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1e128c81
AE		 1059 return rc;
1060 }
1061 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1062 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1063 qed_wr(p_hwfn, p_ptt,
1064 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1065 0x100);
1066 }
fe56b9e6
YM		 1067 }
1068 return rc;
1069}
1070
1071static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1072 struct qed_ptt *p_ptt,
1073 u8 enable)
1074{
1075 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1076
1077 /* Change PF in PXP */
1078 qed_wr(p_hwfn, p_ptt,
1079 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1080
1081 /* wait until value is set - try for 1 second every 50us */
1082 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1083 val = qed_rd(p_hwfn, p_ptt,
1084 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1085 if (val == set_val)
1086 break;
1087
1088 usleep_range(50, 60);
1089 }
1090
1091 if (val != set_val) {
1092 DP_NOTICE(p_hwfn,
1093 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1094 return -EAGAIN;
1095 }
1096
1097 return 0;
1098}
1099
1100static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1101 struct qed_ptt *p_main_ptt)
1102{
1103 /* Read shadow of current MFW mailbox */
1104 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1105 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1a635e48 1106 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
fe56b9e6
YM		 1107}
1108
1109int qed_hw_init(struct qed_dev *cdev,
464f6645 1110 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 1111 bool b_hw_start,
1112 enum qed_int_mode int_mode,
1113 bool allow_npar_tx_switch,
1114 const u8 *bin_fw_data)
1115{
0fefbfba
SK		 1116 u32 load_code, param, drv_mb_param;
1117 bool b_default_mtu = true;
1118 struct qed_hwfn *p_hwfn;
1119 int rc = 0, mfw_rc, i;
fe56b9e6 1120
bb13ace7
SRK		 1121 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1122 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1123 return -EINVAL;
1124 }
1125
1408cc1f
YM		 1126 if (IS_PF(cdev)) {
1127 rc = qed_init_fw_data(cdev, bin_fw_data);
1a635e48 1128 if (rc)
1408cc1f
YM		 1129 return rc;
1130 }
fe56b9e6
YM		 1131
1132 for_each_hwfn(cdev, i) {
1133 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1134
0fefbfba
SK		 1135 /* If management didn't provide a default, set one of our own */
1136 if (!p_hwfn->hw_info.mtu) {
1137 p_hwfn->hw_info.mtu = 1500;
1138 b_default_mtu = false;
1139 }
1140
1408cc1f
YM		 1141 if (IS_VF(cdev)) {
1142 p_hwfn->b_int_enabled = 1;
1143 continue;
1144 }
1145
fe56b9e6
YM		 1146 /* Enable DMAE in PXP */
1147 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1148
9c79ddaa
MY		 1149 rc = qed_calc_hw_mode(p_hwfn);
1150 if (rc)
1151 return rc;
fe56b9e6 1152
1a635e48 1153 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
fe56b9e6
YM		 1154 if (rc) {
1155 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
1156 return rc;
1157 }
1158
1159 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1160
1161 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1162 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1163 rc, load_code);
1164
1165 p_hwfn->first_on_engine = (load_code ==
1166 FW_MSG_CODE_DRV_LOAD_ENGINE);
1167
1168 switch (load_code) {
1169 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1170 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1171 p_hwfn->hw_info.hw_mode);
1172 if (rc)
1173 break;
1174 /* Fall into */
1175 case FW_MSG_CODE_DRV_LOAD_PORT:
1176 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1177 p_hwfn->hw_info.hw_mode);
1178 if (rc)
1179 break;
1180
1181 /* Fall into */
1182 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1183 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
464f6645 1184 p_tunn, p_hwfn->hw_info.hw_mode,
fe56b9e6
YM		 1185 b_hw_start, int_mode,
1186 allow_npar_tx_switch);
1187 break;
1188 default:
1189 rc = -EINVAL;
1190 break;
1191 }
1192
1193 if (rc)
1194 DP_NOTICE(p_hwfn,
1195 "init phase failed for loadcode 0x%x (rc %d)\n",
1196 load_code, rc);
1197
1198 /* ACK mfw regardless of success or failure of initialization */
1199 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1200 DRV_MSG_CODE_LOAD_DONE,
1201 0, &load_code, &param);
1202 if (rc)
1203 return rc;
1204 if (mfw_rc) {
1205 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1206 return mfw_rc;
1207 }
1208
39651abd
SRK		 1209 /* send DCBX attention request command */
1210 DP_VERBOSE(p_hwfn,
1211 QED_MSG_DCB,
1212 "sending phony dcbx set command to trigger DCBx attention handling\n");
1213 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1214 DRV_MSG_CODE_SET_DCBX,
1215 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1216 &load_code, &param);
1217 if (mfw_rc) {
1218 DP_NOTICE(p_hwfn,
1219 "Failed to send DCBX attention request\n");
1220 return mfw_rc;
1221 }
1222
fe56b9e6
YM		 1223 p_hwfn->hw_init_done = true;
1224 }
1225
0fefbfba
SK		 1226 if (IS_PF(cdev)) {
1227 p_hwfn = QED_LEADING_HWFN(cdev);
1228 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1229 (FW_MINOR_VERSION << 16) |
1230 (FW_REVISION_VERSION << 8) |
1231 (FW_ENGINEERING_VERSION);
1232 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1233 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1234 drv_mb_param, &load_code, &param);
1235 if (rc)
1236 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1237
1238 if (!b_default_mtu) {
1239 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1240 p_hwfn->hw_info.mtu);
1241 if (rc)
1242 DP_INFO(p_hwfn,
1243 "Failed to update default mtu\n");
1244 }
1245
1246 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1247 p_hwfn->p_main_ptt,
1248 QED_OV_DRIVER_STATE_DISABLED);
1249 if (rc)
1250 DP_INFO(p_hwfn, "Failed to update driver state\n");
1251
1252 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1253 QED_OV_ESWITCH_VEB);
1254 if (rc)
1255 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1256 }
1257
fe56b9e6
YM		 1258 return 0;
1259}
1260
1261#define QED_HW_STOP_RETRY_LIMIT (10)
1a635e48
YM		 1262static void qed_hw_timers_stop(struct qed_dev *cdev,
1263 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
8c925c44
YM		 1264{
1265 int i;
1266
1267 /* close timers */
1268 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1269 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1270
1271 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1272 if ((!qed_rd(p_hwfn, p_ptt,
1273 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1a635e48 1274 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
8c925c44
YM		 1275 break;
1276
1277 /* Dependent on number of connection/tasks, possibly
1278 * 1ms sleep is required between polls
1279 */
1280 usleep_range(1000, 2000);
1281 }
1282
1283 if (i < QED_HW_STOP_RETRY_LIMIT)
1284 return;
1285
1286 DP_NOTICE(p_hwfn,
1287 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1288 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1289 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1290}
1291
1292void qed_hw_timers_stop_all(struct qed_dev *cdev)
1293{
1294 int j;
1295
1296 for_each_hwfn(cdev, j) {
1297 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1298 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1299
1300 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1301 }
1302}
1303
fe56b9e6
YM		 1304int qed_hw_stop(struct qed_dev *cdev)
1305{
1306 int rc = 0, t_rc;
8c925c44 1307 int j;
fe56b9e6
YM		 1308
1309 for_each_hwfn(cdev, j) {
1310 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1311 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1312
1313 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1314
1408cc1f 1315 if (IS_VF(cdev)) {
0b55e27d 1316 qed_vf_pf_int_cleanup(p_hwfn);
1408cc1f
YM		 1317 continue;
1318 }
1319
fe56b9e6
YM		 1320 /* mark the hw as uninitialized... */
1321 p_hwfn->hw_init_done = false;
1322
1323 rc = qed_sp_pf_stop(p_hwfn);
1324 if (rc)
8c925c44
YM		 1325 DP_NOTICE(p_hwfn,
1326 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
fe56b9e6
YM		 1327
1328 qed_wr(p_hwfn, p_ptt,
1329 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1330
1331 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1332 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1333 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1334 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1335 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1336
8c925c44 1337 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
fe56b9e6
YM		 1338
1339 /* Disable Attention Generation */
1340 qed_int_igu_disable_int(p_hwfn, p_ptt);
1341
1342 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1343 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1344
1345 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1346
1347 /* Need to wait 1ms to guarantee SBs are cleared */
1348 usleep_range(1000, 2000);
1349 }
1350
1408cc1f
YM		 1351 if (IS_PF(cdev)) {
1352 /* Disable DMAE in PXP - in CMT, this should only be done for
1353 * first hw-function, and only after all transactions have
1354 * stopped for all active hw-functions.
1355 */
1356 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1357 cdev->hwfns[0].p_main_ptt, false);
1358 if (t_rc != 0)
1359 rc = t_rc;
1360 }
fe56b9e6
YM		 1361
1362 return rc;
1363}
1364
cee4d264
MC		 1365void qed_hw_stop_fastpath(struct qed_dev *cdev)
1366{
8c925c44 1367 int j;
cee4d264
MC		 1368
1369 for_each_hwfn(cdev, j) {
1370 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
dacd88d6
YM		 1371 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1372
1373 if (IS_VF(cdev)) {
1374 qed_vf_pf_int_cleanup(p_hwfn);
1375 continue;
1376 }
cee4d264
MC		 1377
1378 DP_VERBOSE(p_hwfn,
1a635e48 1379 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
cee4d264
MC		 1380
1381 qed_wr(p_hwfn, p_ptt,
1382 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1383
1384 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1385 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1386 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1387 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1388 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1389
cee4d264
MC		 1390 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1391
1392 /* Need to wait 1ms to guarantee SBs are cleared */
1393 usleep_range(1000, 2000);
1394 }
1395}
1396
1397void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1398{
dacd88d6
YM		 1399 if (IS_VF(p_hwfn->cdev))
1400 return;
1401
cee4d264
MC		 1402 /* Re-open incoming traffic */
1403 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1404 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1405}
1406
1a635e48
YM		 1407static int qed_reg_assert(struct qed_hwfn *p_hwfn,
1408 struct qed_ptt *p_ptt, u32 reg, bool expected)
fe56b9e6 1409{
1a635e48 1410 u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);
fe56b9e6
YM		 1411
1412 if (assert_val != expected) {
525ef5c0 1413 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",
fe56b9e6
YM		 1414 reg, expected);
1415 return -EINVAL;
1416 }
1417
1418 return 0;
1419}
1420
1421int qed_hw_reset(struct qed_dev *cdev)
1422{
1423 int rc = 0;
1424 u32 unload_resp, unload_param;
14d39648 1425 u32 wol_param;
fe56b9e6
YM		 1426 int i;
1427
14d39648
MY		 1428 switch (cdev->wol_config) {
1429 case QED_OV_WOL_DISABLED:
1430 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
1431 break;
1432 case QED_OV_WOL_ENABLED:
1433 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
1434 break;
1435 default:
1436 DP_NOTICE(cdev,
1437 "Unknown WoL configuration %02x\n", cdev->wol_config);
1438 /* Fallthrough */
1439 case QED_OV_WOL_DEFAULT:
1440 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1441 }
1442
fe56b9e6
YM		 1443 for_each_hwfn(cdev, i) {
1444 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1445
1408cc1f 1446 if (IS_VF(cdev)) {
0b55e27d
YM		 1447 rc = qed_vf_pf_reset(p_hwfn);
1448 if (rc)
1449 return rc;
1408cc1f
YM		 1450 continue;
1451 }
1452
fe56b9e6
YM		 1453 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1454
1455 /* Check for incorrect states */
1456 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1457 QM_REG_USG_CNT_PF_TX, 0);
1458 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1459 QM_REG_USG_CNT_PF_OTHER, 0);
1460
1461 /* Disable PF in HW blocks */
1462 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1463 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1464 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1465 TCFC_REG_STRONG_ENABLE_PF, 0);
1466 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1467 CCFC_REG_STRONG_ENABLE_PF, 0);
1468
1469 /* Send unload command to MCP */
1470 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
14d39648 1471 DRV_MSG_CODE_UNLOAD_REQ, wol_param,
fe56b9e6
YM		 1472 &unload_resp, &unload_param);
1473 if (rc) {
1474 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1475 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1476 }
1477
1478 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1479 DRV_MSG_CODE_UNLOAD_DONE,
1480 0, &unload_resp, &unload_param);
1481 if (rc) {
1482 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1483 return rc;
1484 }
1485 }
1486
1487 return rc;
1488}
1489
1490/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1491static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1492{
1493 qed_ptt_pool_free(p_hwfn);
1494 kfree(p_hwfn->hw_info.p_igu_info);
1495}
1496
1497/* Setup bar access */
12e09c69 1498static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 1499{
fe56b9e6 1500 /* clear indirect access */
9c79ddaa
MY		 1501 if (QED_IS_AH(p_hwfn->cdev)) {
1502 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1503 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1504 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1505 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1506 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1507 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1508 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1509 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1510 } else {
1511 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1512 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
1513 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1514 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
1515 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1516 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
1517 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1518 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
1519 }
fe56b9e6
YM		 1520
1521 /* Clean Previous errors if such exist */
1522 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1a635e48 1523 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
fe56b9e6
YM		 1524
1525 /* enable internal target-read */
1526 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1527 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 1528}
1529
1530static void get_function_id(struct qed_hwfn *p_hwfn)
1531{
1532 /* ME Register */
1a635e48
YM		 1533 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1534 PXP_PF_ME_OPAQUE_ADDR);
fe56b9e6
YM		 1535
1536 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1537
1538 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1539 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1540 PXP_CONCRETE_FID_PFID);
1541 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1542 PXP_CONCRETE_FID_PORT);
525ef5c0
YM		 1543
1544 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1545 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1546 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
fe56b9e6
YM		 1547}
1548
25c089d7
YM		 1549static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1550{
1551 u32 *feat_num = p_hwfn->hw_info.feat_num;
5a1f965a 1552 struct qed_sb_cnt_info sb_cnt_info;
25c089d7
YM		 1553 int num_features = 1;
1554
0189efb8
YM		 1555 if (IS_ENABLED(CONFIG_QED_RDMA) &&
1556 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
1557 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
1558 * the status blocks equally between L2 / RoCE but with
1559 * consideration as to how many l2 queues / cnqs we have.
1560 */
51ff1725
RA		 1561 num_features++;
1562
1563 feat_num[QED_RDMA_CNQ] =
1564 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features,
1565 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
1566 }
0189efb8 1567
25c089d7
YM		 1568 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1569 num_features,
1570 RESC_NUM(p_hwfn, QED_L2_QUEUE));
5a1f965a
MY		 1571
1572 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1573 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1574 feat_num[QED_VF_L2_QUE] =
1575 min_t(u32,
1576 RESC_NUM(p_hwfn, QED_L2_QUEUE) -
1577 FEAT_NUM(p_hwfn, QED_PF_L2_QUE), sb_cnt_info.sb_iov_cnt);
1578
1579 DP_VERBOSE(p_hwfn,
1580 NETIF_MSG_PROBE,
1581 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
1582 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
1583 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
1584 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
1585 RESC_NUM(p_hwfn, QED_SB), num_features);
25c089d7
YM		 1586}
1587
2edbff8d
TT		 1588static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id)
1589{
1590 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
1591
1592 switch (res_id) {
1593 case QED_SB:
1594 mfw_res_id = RESOURCE_NUM_SB_E;
1595 break;
1596 case QED_L2_QUEUE:
1597 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
1598 break;
1599 case QED_VPORT:
1600 mfw_res_id = RESOURCE_NUM_VPORT_E;
1601 break;
1602 case QED_RSS_ENG:
1603 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
1604 break;
1605 case QED_PQ:
1606 mfw_res_id = RESOURCE_NUM_PQ_E;
1607 break;
1608 case QED_RL:
1609 mfw_res_id = RESOURCE_NUM_RL_E;
1610 break;
1611 case QED_MAC:
1612 case QED_VLAN:
1613 /* Each VFC resource can accommodate both a MAC and a VLAN */
1614 mfw_res_id = RESOURCE_VFC_FILTER_E;
1615 break;
1616 case QED_ILT:
1617 mfw_res_id = RESOURCE_ILT_E;
1618 break;
1619 case QED_LL2_QUEUE:
1620 mfw_res_id = RESOURCE_LL2_QUEUE_E;
1621 break;
1622 case QED_RDMA_CNQ_RAM:
1623 case QED_CMDQS_CQS:
1624 /* CNQ/CMDQS are the same resource */
1625 mfw_res_id = RESOURCE_CQS_E;
1626 break;
1627 case QED_RDMA_STATS_QUEUE:
1628 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
1629 break;
1630 default:
1631 break;
1632 }
1633
1634 return mfw_res_id;
1635}
1636
1637static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
1638 enum qed_resources res_id)
fe56b9e6 1639{
1408cc1f 1640 u8 num_funcs = p_hwfn->num_funcs_on_engine;
9c79ddaa 1641 bool b_ah = QED_IS_AH(p_hwfn->cdev);
4ac801b7 1642 struct qed_sb_cnt_info sb_cnt_info;
2edbff8d 1643 u32 dflt_resc_num = 0;
fe56b9e6 1644
2edbff8d
TT		 1645 switch (res_id) {
1646 case QED_SB:
1647 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1648 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1649 dflt_resc_num = sb_cnt_info.sb_cnt;
1650 break;
1651 case QED_L2_QUEUE:
9c79ddaa
MY		 1652 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2
1653 : MAX_NUM_L2_QUEUES_BB) / num_funcs;
2edbff8d
TT		 1654 break;
1655 case QED_VPORT:
1656 dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs;
9c79ddaa
MY		 1657 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2
1658 : MAX_NUM_VPORTS_BB) / num_funcs;
2edbff8d
TT		 1659 break;
1660 case QED_RSS_ENG:
9c79ddaa
MY		 1661 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2
1662 : ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2edbff8d
TT		 1663 break;
1664 case QED_PQ:
1665 /* The granularity of the PQs is 8 */
9c79ddaa
MY		 1666 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2
1667 : MAX_QM_TX_QUEUES_BB) / num_funcs;
2edbff8d
TT		 1668 dflt_resc_num &= ~0x7;
1669 break;
1670 case QED_RL:
1671 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
1672 break;
1673 case QED_MAC:
1674 case QED_VLAN:
1675 /* Each VFC resource can accommodate both a MAC and a VLAN */
1676 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
1677 break;
1678 case QED_ILT:
9c79ddaa
MY		 1679 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2
1680 : PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2edbff8d
TT		 1681 break;
1682 case QED_LL2_QUEUE:
1683 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
1684 break;
1685 case QED_RDMA_CNQ_RAM:
1686 case QED_CMDQS_CQS:
1687 /* CNQ/CMDQS are the same resource */
1688 dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
1689 break;
1690 case QED_RDMA_STATS_QUEUE:
9c79ddaa
MY		 1691 dflt_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
1692 : RDMA_NUM_STATISTIC_COUNTERS_BB) /
1693 num_funcs;
1694
2edbff8d
TT		 1695 break;
1696 default:
1697 break;
1698 }
08feecd7 1699
2edbff8d
TT		 1700 return dflt_resc_num;
1701}
08feecd7 1702
2edbff8d
TT		 1703static const char *qed_hw_get_resc_name(enum qed_resources res_id)
1704{
1705 switch (res_id) {
1706 case QED_SB:
1707 return "SB";
1708 case QED_L2_QUEUE:
1709 return "L2_QUEUE";
1710 case QED_VPORT:
1711 return "VPORT";
1712 case QED_RSS_ENG:
1713 return "RSS_ENG";
1714 case QED_PQ:
1715 return "PQ";
1716 case QED_RL:
1717 return "RL";
1718 case QED_MAC:
1719 return "MAC";
1720 case QED_VLAN:
1721 return "VLAN";
1722 case QED_RDMA_CNQ_RAM:
1723 return "RDMA_CNQ_RAM";
1724 case QED_ILT:
1725 return "ILT";
1726 case QED_LL2_QUEUE:
1727 return "LL2_QUEUE";
1728 case QED_CMDQS_CQS:
1729 return "CMDQS_CQS";
1730 case QED_RDMA_STATS_QUEUE:
1731 return "RDMA_STATS_QUEUE";
1732 default:
1733 return "UNKNOWN_RESOURCE";
1734 }
1735}
1736
1737static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
1738 enum qed_resources res_id)
1739{
1740 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
1741 u32 *p_resc_num, *p_resc_start;
1742 struct resource_info resc_info;
1743 int rc;
1744
1745 p_resc_num = &RESC_NUM(p_hwfn, res_id);
1746 p_resc_start = &RESC_START(p_hwfn, res_id);
1747
1748 /* Default values assumes that each function received equal share */
1749 dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id);
1750 if (!dflt_resc_num) {
1751 DP_ERR(p_hwfn,
1752 "Failed to get default amount for resource %d [%s]\n",
1753 res_id, qed_hw_get_resc_name(res_id));
1754 return -EINVAL;
1755 }
1756 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
1757
1758 memset(&resc_info, 0, sizeof(resc_info));
1759 resc_info.res_id = qed_hw_get_mfw_res_id(res_id);
1760 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
1761 DP_ERR(p_hwfn,
1762 "Failed to match resource %d [%s] with the MFW resources\n",
1763 res_id, qed_hw_get_resc_name(res_id));
1764 return -EINVAL;
1765 }
1766
1767 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
1768 &mcp_resp, &mcp_param);
1769 if (rc) {
1770 DP_NOTICE(p_hwfn,
1771 "MFW response failure for an allocation request for resource %d [%s]\n",
1772 res_id, qed_hw_get_resc_name(res_id));
1773 return rc;
1774 }
1775
1776 /* Default driver values are applied in the following cases:
1777 * - The resource allocation MB command is not supported by the MFW
1778 * - There is an internal error in the MFW while processing the request
1779 * - The resource ID is unknown to the MFW
1780 */
1781 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
1782 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
1783 DP_NOTICE(p_hwfn,
1784 "Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n",
1785 res_id,
1786 qed_hw_get_resc_name(res_id),
1787 mcp_resp, dflt_resc_num, dflt_resc_start);
1788 *p_resc_num = dflt_resc_num;
1789 *p_resc_start = dflt_resc_start;
1790 goto out;
1791 }
1792
1793 /* Special handling for status blocks; Would be revised in future */
1794 if (res_id == QED_SB) {
1795 resc_info.size -= 1;
1796 resc_info.offset -= p_hwfn->enabled_func_idx;
1797 }
1798
1799 *p_resc_num = resc_info.size;
1800 *p_resc_start = resc_info.offset;
1801
1802out:
1803 /* PQs have to divide by 8 [that's the HW granularity].
1804 * Reduce number so it would fit.
1805 */
1806 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
1807 DP_INFO(p_hwfn,
1808 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
1809 *p_resc_num,
1810 (*p_resc_num) & ~0x7,
1811 *p_resc_start, (*p_resc_start) & ~0x7);
1812 *p_resc_num &= ~0x7;
1813 *p_resc_start &= ~0x7;
1814 }
4ac801b7 1815
2edbff8d
TT		 1816 return 0;
1817}
1818
1819static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1820{
9c79ddaa 1821 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2edbff8d
TT		 1822 u8 res_id;
1823 int rc;
1824
1825 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
1826 rc = qed_hw_set_resc_info(p_hwfn, res_id);
1827 if (rc)
1828 return rc;
1829 }
dbb799c3
YM		 1830
1831 /* Sanity for ILT */
9c79ddaa
MY		 1832 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1833 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
dbb799c3
YM		 1834 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1835 RESC_START(p_hwfn, QED_ILT),
1836 RESC_END(p_hwfn, QED_ILT) - 1);
1837 return -EINVAL;
1838 }
fe56b9e6 1839
25c089d7
YM		 1840 qed_hw_set_feat(p_hwfn);
1841
fe56b9e6 1842 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2edbff8d
TT		 1843 "The numbers for each resource are:\n");
1844 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
1845 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
1846 qed_hw_get_resc_name(res_id),
1847 RESC_NUM(p_hwfn, res_id),
1848 RESC_START(p_hwfn, res_id));
dbb799c3
YM		 1849
1850 return 0;
fe56b9e6
YM		 1851}
1852
1a635e48 1853static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 1854{
fc48b7a6 1855 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1e128c81 1856 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
cc875c2e 1857 struct qed_mcp_link_params *link;
fe56b9e6
YM		 1858
1859 /* Read global nvm_cfg address */
1860 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1861
1862 /* Verify MCP has initialized it */
1863 if (!nvm_cfg_addr) {
1864 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1865 return -EINVAL;
1866 }
1867
1868 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1869 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1870
cc875c2e
YM		 1871 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1872 offsetof(struct nvm_cfg1, glob) +
1873 offsetof(struct nvm_cfg1_glob, core_cfg);
1874
1875 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1876
1877 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1878 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
351a4ded 1879 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
cc875c2e
YM		 1880 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1881 break;
351a4ded 1882 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
cc875c2e
YM		 1883 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1884 break;
351a4ded 1885 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
cc875c2e
YM		 1886 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1887 break;
351a4ded 1888 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
cc875c2e
YM		 1889 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1890 break;
351a4ded 1891 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
cc875c2e
YM		 1892 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1893 break;
351a4ded 1894 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
cc875c2e
YM		 1895 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1896 break;
351a4ded 1897 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
cc875c2e
YM		 1898 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1899 break;
351a4ded 1900 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
cc875c2e
YM		 1901 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1902 break;
9c79ddaa
MY		 1903 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
1904 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
1905 break;
351a4ded 1906 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
cc875c2e
YM		 1907 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1908 break;
9c79ddaa
MY		 1909 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
1910 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
1911 break;
cc875c2e 1912 default:
1a635e48 1913 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
cc875c2e
YM		 1914 break;
1915 }
1916
cc875c2e
YM		 1917 /* Read default link configuration */
1918 link = &p_hwfn->mcp_info->link_input;
1919 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1920 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1921 link_temp = qed_rd(p_hwfn, p_ptt,
1922 port_cfg_addr +
1923 offsetof(struct nvm_cfg1_port, speed_cap_mask));
83aeb933
YM		 1924 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1925 link->speed.advertised_speeds = link_temp;
cc875c2e 1926
83aeb933
YM		 1927 link_temp = link->speed.advertised_speeds;
1928 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
cc875c2e
YM		 1929
1930 link_temp = qed_rd(p_hwfn, p_ptt,
1931 port_cfg_addr +
1932 offsetof(struct nvm_cfg1_port, link_settings));
1933 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1934 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1935 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1936 link->speed.autoneg = true;
1937 break;
1938 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1939 link->speed.forced_speed = 1000;
1940 break;
1941 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1942 link->speed.forced_speed = 10000;
1943 break;
1944 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1945 link->speed.forced_speed = 25000;
1946 break;
1947 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1948 link->speed.forced_speed = 40000;
1949 break;
1950 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1951 link->speed.forced_speed = 50000;
1952 break;
351a4ded 1953 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
cc875c2e
YM		 1954 link->speed.forced_speed = 100000;
1955 break;
1956 default:
1a635e48 1957 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
cc875c2e
YM		 1958 }
1959
1960 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1961 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1962 link->pause.autoneg = !!(link_temp &
1963 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1964 link->pause.forced_rx = !!(link_temp &
1965 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1966 link->pause.forced_tx = !!(link_temp &
1967 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1968 link->loopback_mode = 0;
1969
1970 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1971 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1972 link->speed.forced_speed, link->speed.advertised_speeds,
1973 link->speed.autoneg, link->pause.autoneg);
1974
fe56b9e6
YM		 1975 /* Read Multi-function information from shmem */
1976 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1977 offsetof(struct nvm_cfg1, glob) +
1978 offsetof(struct nvm_cfg1_glob, generic_cont0);
1979
1980 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1981
1982 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1983 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1984
1985 switch (mf_mode) {
1986 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 1987 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 1988 break;
1989 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 1990 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 1991 break;
fc48b7a6
YM		 1992 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1993 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 1994 break;
1995 }
1996 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1997 p_hwfn->cdev->mf_mode);
1998
fc48b7a6
YM		 1999 /* Read Multi-function information from shmem */
2000 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2001 offsetof(struct nvm_cfg1, glob) +
2002 offsetof(struct nvm_cfg1_glob, device_capabilities);
2003
2004 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2005 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2006 __set_bit(QED_DEV_CAP_ETH,
2007 &p_hwfn->hw_info.device_capabilities);
1e128c81
AE		 2008 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2009 __set_bit(QED_DEV_CAP_FCOE,
2010 &p_hwfn->hw_info.device_capabilities);
c5ac9319
YM		 2011 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2012 __set_bit(QED_DEV_CAP_ISCSI,
2013 &p_hwfn->hw_info.device_capabilities);
2014 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2015 __set_bit(QED_DEV_CAP_ROCE,
2016 &p_hwfn->hw_info.device_capabilities);
fc48b7a6 2017
fe56b9e6
YM		 2018 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2019}
2020
1408cc1f
YM		 2021static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2022{
dbb799c3
YM		 2023 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2024 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
9c79ddaa 2025 struct qed_dev *cdev = p_hwfn->cdev;
1408cc1f 2026
9c79ddaa 2027 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
1408cc1f
YM		 2028
2029 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2030 * in the other bits are selected.
2031 * Bits 1-15 are for functions 1-15, respectively, and their value is
2032 * '0' only for enabled functions (function 0 always exists and
2033 * enabled).
2034 * In case of CMT, only the "even" functions are enabled, and thus the
2035 * number of functions for both hwfns is learnt from the same bits.
2036 */
2037 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2038
2039 if (reg_function_hide & 0x1) {
9c79ddaa
MY		 2040 if (QED_IS_BB(cdev)) {
2041 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2042 num_funcs = 0;
2043 eng_mask = 0xaaaa;
2044 } else {
2045 num_funcs = 1;
2046 eng_mask = 0x5554;
2047 }
1408cc1f
YM		 2048 } else {
2049 num_funcs = 1;
9c79ddaa 2050 eng_mask = 0xfffe;
1408cc1f
YM		 2051 }
2052
2053 /* Get the number of the enabled functions on the engine */
2054 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2055 while (tmp) {
2056 if (tmp & 0x1)
2057 num_funcs++;
2058 tmp >>= 0x1;
2059 }
dbb799c3
YM		 2060
2061 /* Get the PF index within the enabled functions */
2062 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2063 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2064 while (tmp) {
2065 if (tmp & 0x1)
2066 enabled_func_idx--;
2067 tmp >>= 0x1;
2068 }
1408cc1f
YM		 2069 }
2070
2071 p_hwfn->num_funcs_on_engine = num_funcs;
dbb799c3 2072 p_hwfn->enabled_func_idx = enabled_func_idx;
1408cc1f
YM		 2073
2074 DP_VERBOSE(p_hwfn,
2075 NETIF_MSG_PROBE,
525ef5c0 2076 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1408cc1f
YM		 2077 p_hwfn->rel_pf_id,
2078 p_hwfn->abs_pf_id,
525ef5c0 2079 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1408cc1f
YM		 2080}
2081
9c79ddaa
MY		 2082static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2083 struct qed_ptt *p_ptt)
fe56b9e6
YM		 2084{
2085 u32 port_mode;
fe56b9e6 2086
9c79ddaa 2087 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
fe56b9e6
YM		 2088
2089 if (port_mode < 3) {
2090 p_hwfn->cdev->num_ports_in_engines = 1;
2091 } else if (port_mode <= 5) {
2092 p_hwfn->cdev->num_ports_in_engines = 2;
2093 } else {
2094 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2095 p_hwfn->cdev->num_ports_in_engines);
2096
2097 /* Default num_ports_in_engines to something */
2098 p_hwfn->cdev->num_ports_in_engines = 1;
2099 }
9c79ddaa
MY		 2100}
2101
2102static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2103 struct qed_ptt *p_ptt)
2104{
2105 u32 port;
2106 int i;
2107
2108 p_hwfn->cdev->num_ports_in_engines = 0;
2109
2110 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2111 port = qed_rd(p_hwfn, p_ptt,
2112 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2113 if (port & 1)
2114 p_hwfn->cdev->num_ports_in_engines++;
2115 }
2116
2117 if (!p_hwfn->cdev->num_ports_in_engines) {
2118 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2119
2120 /* Default num_ports_in_engine to something */
2121 p_hwfn->cdev->num_ports_in_engines = 1;
2122 }
2123}
2124
2125static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2126{
2127 if (QED_IS_BB(p_hwfn->cdev))
2128 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2129 else
2130 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2131}
2132
2133static int
2134qed_get_hw_info(struct qed_hwfn *p_hwfn,
2135 struct qed_ptt *p_ptt,
2136 enum qed_pci_personality personality)
2137{
2138 int rc;
2139
2140 /* Since all information is common, only first hwfns should do this */
2141 if (IS_LEAD_HWFN(p_hwfn)) {
2142 rc = qed_iov_hw_info(p_hwfn);
2143 if (rc)
2144 return rc;
2145 }
2146
2147 qed_hw_info_port_num(p_hwfn, p_ptt);
fe56b9e6
YM		 2148
2149 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2150
2151 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2152 if (rc)
2153 return rc;
2154
2155 if (qed_mcp_is_init(p_hwfn))
2156 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2157 p_hwfn->mcp_info->func_info.mac);
2158 else
2159 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2160
2161 if (qed_mcp_is_init(p_hwfn)) {
2162 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2163 p_hwfn->hw_info.ovlan =
2164 p_hwfn->mcp_info->func_info.ovlan;
2165
2166 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2167 }
2168
2169 if (qed_mcp_is_init(p_hwfn)) {
2170 enum qed_pci_personality protocol;
2171
2172 protocol = p_hwfn->mcp_info->func_info.protocol;
2173 p_hwfn->hw_info.personality = protocol;
2174 }
2175
1408cc1f
YM		 2176 qed_get_num_funcs(p_hwfn, p_ptt);
2177
0fefbfba
SK		 2178 if (qed_mcp_is_init(p_hwfn))
2179 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2180
dbb799c3 2181 return qed_hw_get_resc(p_hwfn);
fe56b9e6
YM		 2182}
2183
12e09c69 2184static int qed_get_dev_info(struct qed_dev *cdev)
fe56b9e6 2185{
fc48b7a6 2186 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
9c79ddaa 2187 u16 device_id_mask;
fe56b9e6
YM		 2188 u32 tmp;
2189
fc48b7a6 2190 /* Read Vendor Id / Device Id */
1a635e48
YM		 2191 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2192 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2193
9c79ddaa
MY		 2194 /* Determine type */
2195 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2196 switch (device_id_mask) {
2197 case QED_DEV_ID_MASK_BB:
2198 cdev->type = QED_DEV_TYPE_BB;
2199 break;
2200 case QED_DEV_ID_MASK_AH:
2201 cdev->type = QED_DEV_TYPE_AH;
2202 break;
2203 default:
2204 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2205 return -EBUSY;
2206 }
2207
fc48b7a6 2208 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6 2209 MISCS_REG_CHIP_NUM);
fc48b7a6 2210 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2211 MISCS_REG_CHIP_REV);
2212 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2213
2214 /* Learn number of HW-functions */
fc48b7a6 2215 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2216 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2217
fc48b7a6 2218 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 2219 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2220 cdev->num_hwfns = 2;
2221 } else {
2222 cdev->num_hwfns = 1;
2223 }
2224
fc48b7a6 2225 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2226 MISCS_REG_CHIP_TEST_REG) >> 4;
2227 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
fc48b7a6 2228 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2229 MISCS_REG_CHIP_METAL);
2230 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2231
2232 DP_INFO(cdev->hwfns,
9c79ddaa
MY		 2233 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2234 QED_IS_BB(cdev) ? "BB" : "AH",
2235 'A' + cdev->chip_rev,
2236 (int)cdev->chip_metal,
fe56b9e6
YM		 2237 cdev->chip_num, cdev->chip_rev,
2238 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 2239
2240 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
2241 DP_NOTICE(cdev->hwfns,
2242 "The chip type/rev (BB A0) is not supported!\n");
2243 return -EINVAL;
2244 }
2245
2246 return 0;
fe56b9e6
YM		 2247}
2248
2249static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2250 void __iomem *p_regview,
2251 void __iomem *p_doorbells,
2252 enum qed_pci_personality personality)
2253{
2254 int rc = 0;
2255
2256 /* Split PCI bars evenly between hwfns */
2257 p_hwfn->regview = p_regview;
2258 p_hwfn->doorbells = p_doorbells;
2259
1408cc1f
YM		 2260 if (IS_VF(p_hwfn->cdev))
2261 return qed_vf_hw_prepare(p_hwfn);
2262
fe56b9e6
YM		 2263 /* Validate that chip access is feasible */
2264 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2265 DP_ERR(p_hwfn,
2266 "Reading the ME register returns all Fs; Preventing further chip access\n");
2267 return -EINVAL;
2268 }
2269
2270 get_function_id(p_hwfn);
2271
12e09c69
YM		 2272 /* Allocate PTT pool */
2273 rc = qed_ptt_pool_alloc(p_hwfn);
2591c280 2274 if (rc)
fe56b9e6 2275 goto err0;
fe56b9e6 2276
12e09c69
YM		 2277 /* Allocate the main PTT */
2278 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2279
fe56b9e6 2280 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69
YM		 2281 if (!p_hwfn->my_id) {
2282 rc = qed_get_dev_info(p_hwfn->cdev);
1a635e48 2283 if (rc)
12e09c69
YM		 2284 goto err1;
2285 }
2286
2287 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 2288
2289 /* Initialize MCP structure */
2290 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2291 if (rc) {
2292 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2293 goto err1;
2294 }
2295
2296 /* Read the device configuration information from the HW and SHMEM */
2297 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2298 if (rc) {
2299 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2300 goto err2;
2301 }
2302
2303 /* Allocate the init RT array and initialize the init-ops engine */
2304 rc = qed_init_alloc(p_hwfn);
2591c280 2305 if (rc)
fe56b9e6 2306 goto err2;
fe56b9e6
YM		 2307
2308 return rc;
2309err2:
32a47e72
YM		 2310 if (IS_LEAD_HWFN(p_hwfn))
2311 qed_iov_free_hw_info(p_hwfn->cdev);
fe56b9e6
YM		 2312 qed_mcp_free(p_hwfn);
2313err1:
2314 qed_hw_hwfn_free(p_hwfn);
2315err0:
2316 return rc;
2317}
2318
fe56b9e6
YM		 2319int qed_hw_prepare(struct qed_dev *cdev,
2320 int personality)
2321{
c78df14e
AE		 2322 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2323 int rc;
fe56b9e6
YM		 2324
2325 /* Store the precompiled init data ptrs */
1408cc1f
YM		 2326 if (IS_PF(cdev))
2327 qed_init_iro_array(cdev);
fe56b9e6
YM		 2328
2329 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 2330 rc = qed_hw_prepare_single(p_hwfn,
2331 cdev->regview,
fe56b9e6
YM		 2332 cdev->doorbells, personality);
2333 if (rc)
2334 return rc;
2335
c78df14e 2336 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 2337
2338 /* Initialize the rest of the hwfns */
c78df14e 2339 if (cdev->num_hwfns > 1) {
fe56b9e6 2340 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 2341 u8 __iomem *addr;
2342
2343 /* adjust bar offset for second engine */
c2035eea 2344 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
c78df14e 2345 p_regview = addr;
fe56b9e6 2346
c78df14e 2347 /* adjust doorbell bar offset for second engine */
c2035eea 2348 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
c78df14e
AE		 2349 p_doorbell = addr;
2350
2351 /* prepare second hw function */
2352 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 2353 p_doorbell, personality);
c78df14e
AE		 2354
2355 /* in case of error, need to free the previously
2356 * initiliazed hwfn 0.
2357 */
fe56b9e6 2358 if (rc) {
1408cc1f
YM		 2359 if (IS_PF(cdev)) {
2360 qed_init_free(p_hwfn);
2361 qed_mcp_free(p_hwfn);
2362 qed_hw_hwfn_free(p_hwfn);
2363 }
fe56b9e6
YM		 2364 }
2365 }
2366
c78df14e 2367 return rc;
fe56b9e6
YM		 2368}
2369
2370void qed_hw_remove(struct qed_dev *cdev)
2371{
0fefbfba 2372 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 2373 int i;
2374
0fefbfba
SK		 2375 if (IS_PF(cdev))
2376 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2377 QED_OV_DRIVER_STATE_NOT_LOADED);
2378
fe56b9e6
YM		 2379 for_each_hwfn(cdev, i) {
2380 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2381
1408cc1f 2382 if (IS_VF(cdev)) {
0b55e27d 2383 qed_vf_pf_release(p_hwfn);
1408cc1f
YM		 2384 continue;
2385 }
2386
fe56b9e6
YM		 2387 qed_init_free(p_hwfn);
2388 qed_hw_hwfn_free(p_hwfn);
2389 qed_mcp_free(p_hwfn);
2390 }
32a47e72
YM		 2391
2392 qed_iov_free_hw_info(cdev);
fe56b9e6
YM		 2393}
2394
a91eb52a
YM		 2395static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2396 struct qed_chain *p_chain)
2397{
2398 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2399 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2400 struct qed_chain_next *p_next;
2401 u32 size, i;
2402
2403 if (!p_virt)
2404 return;
2405
2406 size = p_chain->elem_size * p_chain->usable_per_page;
2407
2408 for (i = 0; i < p_chain->page_cnt; i++) {
2409 if (!p_virt)
2410 break;
2411
2412 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2413 p_virt_next = p_next->next_virt;
2414 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2415
2416 dma_free_coherent(&cdev->pdev->dev,
2417 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2418
2419 p_virt = p_virt_next;
2420 p_phys = p_phys_next;
2421 }
2422}
2423
2424static void qed_chain_free_single(struct qed_dev *cdev,
2425 struct qed_chain *p_chain)
2426{
2427 if (!p_chain->p_virt_addr)
2428 return;
2429
2430 dma_free_coherent(&cdev->pdev->dev,
2431 QED_CHAIN_PAGE_SIZE,
2432 p_chain->p_virt_addr, p_chain->p_phys_addr);
2433}
2434
2435static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2436{
2437 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2438 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
6d937acf 2439 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
a91eb52a
YM		 2440
2441 if (!pp_virt_addr_tbl)
2442 return;
2443
6d937acf 2444 if (!p_pbl_virt)
a91eb52a
YM		 2445 goto out;
2446
2447 for (i = 0; i < page_cnt; i++) {
2448 if (!pp_virt_addr_tbl[i])
2449 break;
2450
2451 dma_free_coherent(&cdev->pdev->dev,
2452 QED_CHAIN_PAGE_SIZE,
2453 pp_virt_addr_tbl[i],
2454 *(dma_addr_t *)p_pbl_virt);
2455
2456 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2457 }
2458
2459 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2460 dma_free_coherent(&cdev->pdev->dev,
2461 pbl_size,
6d937acf
MY		 2462 p_chain->pbl_sp.p_virt_table,
2463 p_chain->pbl_sp.p_phys_table);
a91eb52a
YM		 2464out:
2465 vfree(p_chain->pbl.pp_virt_addr_tbl);
2466}
2467
2468void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
2469{
2470 switch (p_chain->mode) {
2471 case QED_CHAIN_MODE_NEXT_PTR:
2472 qed_chain_free_next_ptr(cdev, p_chain);
2473 break;
2474 case QED_CHAIN_MODE_SINGLE:
2475 qed_chain_free_single(cdev, p_chain);
2476 break;
2477 case QED_CHAIN_MODE_PBL:
2478 qed_chain_free_pbl(cdev, p_chain);
2479 break;
2480 }
2481}
2482
2483static int
2484qed_chain_alloc_sanity_check(struct qed_dev *cdev,
2485 enum qed_chain_cnt_type cnt_type,
2486 size_t elem_size, u32 page_cnt)
fe56b9e6 2487{
a91eb52a
YM		 2488 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2489
2490 /* The actual chain size can be larger than the maximal possible value
2491 * after rounding up the requested elements number to pages, and after
2492 * taking into acount the unusuable elements (next-ptr elements).
2493 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2494 * size/capacity fields are of a u32 type.
2495 */
2496 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
2497 chain_size > 0x10000) ||
2498 (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
2499 chain_size > 0x100000000ULL)) {
2500 DP_NOTICE(cdev,
2501 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
2502 chain_size);
2503 return -EINVAL;
2504 }
2505
2506 return 0;
2507}
2508
2509static int
2510qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
2511{
2512 void *p_virt = NULL, *p_virt_prev = NULL;
fe56b9e6 2513 dma_addr_t p_phys = 0;
a91eb52a 2514 u32 i;
fe56b9e6 2515
a91eb52a
YM		 2516 for (i = 0; i < p_chain->page_cnt; i++) {
2517 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2518 QED_CHAIN_PAGE_SIZE,
2519 &p_phys, GFP_KERNEL);
2591c280 2520 if (!p_virt)
a91eb52a 2521 return -ENOMEM;
a91eb52a
YM		 2522
2523 if (i == 0) {
2524 qed_chain_init_mem(p_chain, p_virt, p_phys);
2525 qed_chain_reset(p_chain);
2526 } else {
2527 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2528 p_virt, p_phys);
2529 }
2530
2531 p_virt_prev = p_virt;
2532 }
2533 /* Last page's next element should point to the beginning of the
2534 * chain.
2535 */
2536 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2537 p_chain->p_virt_addr,
2538 p_chain->p_phys_addr);
2539
2540 return 0;
2541}
2542
2543static int
2544qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2545{
2546 dma_addr_t p_phys = 0;
2547 void *p_virt = NULL;
fe56b9e6 2548
fe56b9e6 2549 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
a91eb52a 2550 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2591c280 2551 if (!p_virt)
a91eb52a 2552 return -ENOMEM;
fe56b9e6 2553
a91eb52a
YM		 2554 qed_chain_init_mem(p_chain, p_virt, p_phys);
2555 qed_chain_reset(p_chain);
fe56b9e6 2556
a91eb52a
YM		 2557 return 0;
2558}
2559
2560static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2561{
2562 u32 page_cnt = p_chain->page_cnt, size, i;
2563 dma_addr_t p_phys = 0, p_pbl_phys = 0;
2564 void **pp_virt_addr_tbl = NULL;
2565 u8 *p_pbl_virt = NULL;
2566 void *p_virt = NULL;
2567
2568 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2591c280
JP		 2569 pp_virt_addr_tbl = vzalloc(size);
2570 if (!pp_virt_addr_tbl)
a91eb52a 2571 return -ENOMEM;
fe56b9e6 2572
a91eb52a
YM		 2573 /* The allocation of the PBL table is done with its full size, since it
2574 * is expected to be successive.
2575 * qed_chain_init_pbl_mem() is called even in a case of an allocation
2576 * failure, since pp_virt_addr_tbl was previously allocated, and it
2577 * should be saved to allow its freeing during the error flow.
2578 */
2579 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2580 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2581 size, &p_pbl_phys, GFP_KERNEL);
2582 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2583 pp_virt_addr_tbl);
2591c280 2584 if (!p_pbl_virt)
a91eb52a 2585 return -ENOMEM;
fe56b9e6 2586
a91eb52a
YM		 2587 for (i = 0; i < page_cnt; i++) {
2588 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2589 QED_CHAIN_PAGE_SIZE,
2590 &p_phys, GFP_KERNEL);
2591c280 2591 if (!p_virt)
a91eb52a 2592 return -ENOMEM;
fe56b9e6 2593
a91eb52a
YM		 2594 if (i == 0) {
2595 qed_chain_init_mem(p_chain, p_virt, p_phys);
2596 qed_chain_reset(p_chain);
2597 }
2598
2599 /* Fill the PBL table with the physical address of the page */
2600 *(dma_addr_t *)p_pbl_virt = p_phys;
2601 /* Keep the virtual address of the page */
2602 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2603
2604 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2605 }
2606
2607 return 0;
fe56b9e6
YM		 2608}
2609
a91eb52a
YM		 2610int qed_chain_alloc(struct qed_dev *cdev,
2611 enum qed_chain_use_mode intended_use,
2612 enum qed_chain_mode mode,
2613 enum qed_chain_cnt_type cnt_type,
2614 u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
fe56b9e6 2615{
a91eb52a
YM		 2616 u32 page_cnt;
2617 int rc = 0;
fe56b9e6 2618
a91eb52a
YM		 2619 if (mode == QED_CHAIN_MODE_SINGLE)
2620 page_cnt = 1;
2621 else
2622 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
fe56b9e6 2623
a91eb52a
YM		 2624 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2625 if (rc) {
2626 DP_NOTICE(cdev,
2591c280
JP		 2627 "Cannot allocate a chain with the given arguments:\n");
2628 DP_NOTICE(cdev,
a91eb52a
YM		 2629 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2630 intended_use, mode, cnt_type, num_elems, elem_size);
2631 return rc;
fe56b9e6
YM		 2632 }
2633
a91eb52a
YM		 2634 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2635 mode, cnt_type);
2636
2637 switch (mode) {
2638 case QED_CHAIN_MODE_NEXT_PTR:
2639 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2640 break;
2641 case QED_CHAIN_MODE_SINGLE:
2642 rc = qed_chain_alloc_single(cdev, p_chain);
2643 break;
2644 case QED_CHAIN_MODE_PBL:
2645 rc = qed_chain_alloc_pbl(cdev, p_chain);
2646 break;
2647 }
2648 if (rc)
2649 goto nomem;
2650
2651 return 0;
2652
2653nomem:
2654 qed_chain_free(cdev, p_chain);
2655 return rc;
fe56b9e6 2656}
cee4d264 2657
a91eb52a 2658int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
cee4d264
MC		 2659{
2660 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2661 u16 min, max;
2662
a91eb52a 2663 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
cee4d264
MC		 2664 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2665 DP_NOTICE(p_hwfn,
2666 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2667 src_id, min, max);
2668
2669 return -EINVAL;
2670 }
2671
2672 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2673
2674 return 0;
2675}
2676
1a635e48 2677int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 2678{
2679 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2680 u8 min, max;
2681
2682 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2683 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2684 DP_NOTICE(p_hwfn,
2685 "vport id [%d] is not valid, available indices [%d - %d]\n",
2686 src_id, min, max);
2687
2688 return -EINVAL;
2689 }
2690
2691 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2692
2693 return 0;
2694}
2695
1a635e48 2696int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 2697{
2698 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2699 u8 min, max;
2700
2701 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2702 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2703 DP_NOTICE(p_hwfn,
2704 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2705 src_id, min, max);
2706
2707 return -EINVAL;
2708 }
2709
2710 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2711
2712 return 0;
2713}
bcd197c8 2714
0a7fb11c
YM		 2715static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
2716 u8 *p_filter)
2717{
2718 *p_high = p_filter[1] | (p_filter[0] << 8);
2719 *p_low = p_filter[5] | (p_filter[4] << 8) |
2720 (p_filter[3] << 16) | (p_filter[2] << 24);
2721}
2722
2723int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
2724 struct qed_ptt *p_ptt, u8 *p_filter)
2725{
2726 u32 high = 0, low = 0, en;
2727 int i;
2728
2729 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2730 return 0;
2731
2732 qed_llh_mac_to_filter(&high, &low, p_filter);
2733
2734 /* Find a free entry and utilize it */
2735 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2736 en = qed_rd(p_hwfn, p_ptt,
2737 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2738 if (en)
2739 continue;
2740 qed_wr(p_hwfn, p_ptt,
2741 NIG_REG_LLH_FUNC_FILTER_VALUE +
2742 2 * i * sizeof(u32), low);
2743 qed_wr(p_hwfn, p_ptt,
2744 NIG_REG_LLH_FUNC_FILTER_VALUE +
2745 (2 * i + 1) * sizeof(u32), high);
2746 qed_wr(p_hwfn, p_ptt,
2747 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2748 qed_wr(p_hwfn, p_ptt,
2749 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2750 i * sizeof(u32), 0);
2751 qed_wr(p_hwfn, p_ptt,
2752 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2753 break;
2754 }
2755 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2756 DP_NOTICE(p_hwfn,
2757 "Failed to find an empty LLH filter to utilize\n");
2758 return -EINVAL;
2759 }
2760
2761 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2762 "mac: %pM is added at %d\n",
2763 p_filter, i);
2764
2765 return 0;
2766}
2767
2768void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
2769 struct qed_ptt *p_ptt, u8 *p_filter)
2770{
2771 u32 high = 0, low = 0;
2772 int i;
2773
2774 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2775 return;
2776
2777 qed_llh_mac_to_filter(&high, &low, p_filter);
2778
2779 /* Find the entry and clean it */
2780 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2781 if (qed_rd(p_hwfn, p_ptt,
2782 NIG_REG_LLH_FUNC_FILTER_VALUE +
2783 2 * i * sizeof(u32)) != low)
2784 continue;
2785 if (qed_rd(p_hwfn, p_ptt,
2786 NIG_REG_LLH_FUNC_FILTER_VALUE +
2787 (2 * i + 1) * sizeof(u32)) != high)
2788 continue;
2789
2790 qed_wr(p_hwfn, p_ptt,
2791 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2792 qed_wr(p_hwfn, p_ptt,
2793 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2794 qed_wr(p_hwfn, p_ptt,
2795 NIG_REG_LLH_FUNC_FILTER_VALUE +
2796 (2 * i + 1) * sizeof(u32), 0);
2797
2798 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2799 "mac: %pM is removed from %d\n",
2800 p_filter, i);
2801 break;
2802 }
2803 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2804 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2805}
2806
1e128c81
AE		 2807int
2808qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
2809 struct qed_ptt *p_ptt,
2810 u16 source_port_or_eth_type,
2811 u16 dest_port, enum qed_llh_port_filter_type_t type)
2812{
2813 u32 high = 0, low = 0, en;
2814 int i;
2815
2816 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2817 return 0;
2818
2819 switch (type) {
2820 case QED_LLH_FILTER_ETHERTYPE:
2821 high = source_port_or_eth_type;
2822 break;
2823 case QED_LLH_FILTER_TCP_SRC_PORT:
2824 case QED_LLH_FILTER_UDP_SRC_PORT:
2825 low = source_port_or_eth_type << 16;
2826 break;
2827 case QED_LLH_FILTER_TCP_DEST_PORT:
2828 case QED_LLH_FILTER_UDP_DEST_PORT:
2829 low = dest_port;
2830 break;
2831 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
2832 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
2833 low = (source_port_or_eth_type << 16) | dest_port;
2834 break;
2835 default:
2836 DP_NOTICE(p_hwfn,
2837 "Non valid LLH protocol filter type %d\n", type);
2838 return -EINVAL;
2839 }
2840 /* Find a free entry and utilize it */
2841 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2842 en = qed_rd(p_hwfn, p_ptt,
2843 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2844 if (en)
2845 continue;
2846 qed_wr(p_hwfn, p_ptt,
2847 NIG_REG_LLH_FUNC_FILTER_VALUE +
2848 2 * i * sizeof(u32), low);
2849 qed_wr(p_hwfn, p_ptt,
2850 NIG_REG_LLH_FUNC_FILTER_VALUE +
2851 (2 * i + 1) * sizeof(u32), high);
2852 qed_wr(p_hwfn, p_ptt,
2853 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2854 qed_wr(p_hwfn, p_ptt,
2855 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2856 i * sizeof(u32), 1 << type);
2857 qed_wr(p_hwfn, p_ptt,
2858 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2859 break;
2860 }
2861 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2862 DP_NOTICE(p_hwfn,
2863 "Failed to find an empty LLH filter to utilize\n");
2864 return -EINVAL;
2865 }
2866 switch (type) {
2867 case QED_LLH_FILTER_ETHERTYPE:
2868 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2869 "ETH type %x is added at %d\n",
2870 source_port_or_eth_type, i);
2871 break;
2872 case QED_LLH_FILTER_TCP_SRC_PORT:
2873 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2874 "TCP src port %x is added at %d\n",
2875 source_port_or_eth_type, i);
2876 break;
2877 case QED_LLH_FILTER_UDP_SRC_PORT:
2878 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2879 "UDP src port %x is added at %d\n",
2880 source_port_or_eth_type, i);
2881 break;
2882 case QED_LLH_FILTER_TCP_DEST_PORT:
2883 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2884 "TCP dst port %x is added at %d\n", dest_port, i);
2885 break;
2886 case QED_LLH_FILTER_UDP_DEST_PORT:
2887 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2888 "UDP dst port %x is added at %d\n", dest_port, i);
2889 break;
2890 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
2891 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2892 "TCP src/dst ports %x/%x are added at %d\n",
2893 source_port_or_eth_type, dest_port, i);
2894 break;
2895 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
2896 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2897 "UDP src/dst ports %x/%x are added at %d\n",
2898 source_port_or_eth_type, dest_port, i);
2899 break;
2900 }
2901 return 0;
2902}
2903
2904void
2905qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
2906 struct qed_ptt *p_ptt,
2907 u16 source_port_or_eth_type,
2908 u16 dest_port,
2909 enum qed_llh_port_filter_type_t type)
2910{
2911 u32 high = 0, low = 0;
2912 int i;
2913
2914 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2915 return;
2916
2917 switch (type) {
2918 case QED_LLH_FILTER_ETHERTYPE:
2919 high = source_port_or_eth_type;
2920 break;
2921 case QED_LLH_FILTER_TCP_SRC_PORT:
2922 case QED_LLH_FILTER_UDP_SRC_PORT:
2923 low = source_port_or_eth_type << 16;
2924 break;
2925 case QED_LLH_FILTER_TCP_DEST_PORT:
2926 case QED_LLH_FILTER_UDP_DEST_PORT:
2927 low = dest_port;
2928 break;
2929 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
2930 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
2931 low = (source_port_or_eth_type << 16) | dest_port;
2932 break;
2933 default:
2934 DP_NOTICE(p_hwfn,
2935 "Non valid LLH protocol filter type %d\n", type);
2936 return;
2937 }
2938
2939 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2940 if (!qed_rd(p_hwfn, p_ptt,
2941 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
2942 continue;
2943 if (!qed_rd(p_hwfn, p_ptt,
2944 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
2945 continue;
2946 if (!(qed_rd(p_hwfn, p_ptt,
2947 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2948 i * sizeof(u32)) & BIT(type)))
2949 continue;
2950 if (qed_rd(p_hwfn, p_ptt,
2951 NIG_REG_LLH_FUNC_FILTER_VALUE +
2952 2 * i * sizeof(u32)) != low)
2953 continue;
2954 if (qed_rd(p_hwfn, p_ptt,
2955 NIG_REG_LLH_FUNC_FILTER_VALUE +
2956 (2 * i + 1) * sizeof(u32)) != high)
2957 continue;
2958
2959 qed_wr(p_hwfn, p_ptt,
2960 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2961 qed_wr(p_hwfn, p_ptt,
2962 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2963 qed_wr(p_hwfn, p_ptt,
2964 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2965 i * sizeof(u32), 0);
2966 qed_wr(p_hwfn, p_ptt,
2967 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2968 qed_wr(p_hwfn, p_ptt,
2969 NIG_REG_LLH_FUNC_FILTER_VALUE +
2970 (2 * i + 1) * sizeof(u32), 0);
2971 break;
2972 }
2973
2974 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2975 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2976}
2977
722003ac
SRK		 2978static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2979 u32 hw_addr, void *p_eth_qzone,
2980 size_t eth_qzone_size, u8 timeset)
2981{
2982 struct coalescing_timeset *p_coal_timeset;
2983
2984 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2985 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2986 return -EINVAL;
2987 }
2988
2989 p_coal_timeset = p_eth_qzone;
2990 memset(p_coal_timeset, 0, eth_qzone_size);
2991 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2992 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2993 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2994
2995 return 0;
2996}
2997
2998int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2999 u16 coalesce, u8 qid, u16 sb_id)
3000{
3001 struct ustorm_eth_queue_zone eth_qzone;
3002 u8 timeset, timer_res;
3003 u16 fw_qid = 0;
3004 u32 address;
3005 int rc;
3006
3007 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3008 if (coalesce <= 0x7F) {
3009 timer_res = 0;
3010 } else if (coalesce <= 0xFF) {
3011 timer_res = 1;
3012 } else if (coalesce <= 0x1FF) {
3013 timer_res = 2;
3014 } else {
3015 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3016 return -EINVAL;
3017 }
3018 timeset = (u8)(coalesce >> timer_res);
3019
3020 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3021 if (rc)
3022 return rc;
3023
3024 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3025 if (rc)
3026 goto out;
3027
3028 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3029
3030 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3031 sizeof(struct ustorm_eth_queue_zone), timeset);
3032 if (rc)
3033 goto out;
3034
3035 p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3036out:
3037 return rc;
3038}
3039
3040int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3041 u16 coalesce, u8 qid, u16 sb_id)
3042{
3043 struct xstorm_eth_queue_zone eth_qzone;
3044 u8 timeset, timer_res;
3045 u16 fw_qid = 0;
3046 u32 address;
3047 int rc;
3048
3049 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3050 if (coalesce <= 0x7F) {
3051 timer_res = 0;
3052 } else if (coalesce <= 0xFF) {
3053 timer_res = 1;
3054 } else if (coalesce <= 0x1FF) {
3055 timer_res = 2;
3056 } else {
3057 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3058 return -EINVAL;
3059 }
3060 timeset = (u8)(coalesce >> timer_res);
3061
3062 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3063 if (rc)
3064 return rc;
3065
3066 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3067 if (rc)
3068 goto out;
3069
3070 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3071
3072 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3073 sizeof(struct xstorm_eth_queue_zone), timeset);
3074 if (rc)
3075 goto out;
3076
3077 p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3078out:
3079 return rc;
3080}
3081
bcd197c8
MC		 3082/* Calculate final WFQ values for all vports and configure them.
3083 * After this configuration each vport will have
3084 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3085 */
3086static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3087 struct qed_ptt *p_ptt,
3088 u32 min_pf_rate)
3089{
3090 struct init_qm_vport_params *vport_params;
3091 int i;
3092
3093 vport_params = p_hwfn->qm_info.qm_vport_params;
3094
3095 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3096 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3097
3098 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3099 min_pf_rate;
3100 qed_init_vport_wfq(p_hwfn, p_ptt,
3101 vport_params[i].first_tx_pq_id,
3102 vport_params[i].vport_wfq);
3103 }
3104}
3105
3106static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3107 u32 min_pf_rate)
3108
3109{
3110 int i;
3111
3112 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3113 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3114}
3115
3116static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3117 struct qed_ptt *p_ptt,
3118 u32 min_pf_rate)
3119{
3120 struct init_qm_vport_params *vport_params;
3121 int i;
3122
3123 vport_params = p_hwfn->qm_info.qm_vport_params;
3124
3125 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3126 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3127 qed_init_vport_wfq(p_hwfn, p_ptt,
3128 vport_params[i].first_tx_pq_id,
3129 vport_params[i].vport_wfq);
3130 }
3131}
3132
3133/* This function performs several validations for WFQ
3134 * configuration and required min rate for a given vport
3135 * 1. req_rate must be greater than one percent of min_pf_rate.
3136 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3137 * rates to get less than one percent of min_pf_rate.
3138 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3139 */
3140static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1a635e48 3141 u16 vport_id, u32 req_rate, u32 min_pf_rate)
bcd197c8
MC		 3142{
3143 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3144 int non_requested_count = 0, req_count = 0, i, num_vports;
3145
3146 num_vports = p_hwfn->qm_info.num_vports;
3147
3148 /* Accounting for the vports which are configured for WFQ explicitly */
3149 for (i = 0; i < num_vports; i++) {
3150 u32 tmp_speed;
3151
3152 if ((i != vport_id) &&
3153 p_hwfn->qm_info.wfq_data[i].configured) {
3154 req_count++;
3155 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3156 total_req_min_rate += tmp_speed;
3157 }
3158 }
3159
3160 /* Include current vport data as well */
3161 req_count++;
3162 total_req_min_rate += req_rate;
3163 non_requested_count = num_vports - req_count;
3164
3165 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3166 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3167 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3168 vport_id, req_rate, min_pf_rate);
3169 return -EINVAL;
3170 }
3171
3172 if (num_vports > QED_WFQ_UNIT) {
3173 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3174 "Number of vports is greater than %d\n",
3175 QED_WFQ_UNIT);
3176 return -EINVAL;
3177 }
3178
3179 if (total_req_min_rate > min_pf_rate) {
3180 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3181 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3182 total_req_min_rate, min_pf_rate);
3183 return -EINVAL;
3184 }
3185
3186 total_left_rate = min_pf_rate - total_req_min_rate;
3187
3188 left_rate_per_vp = total_left_rate / non_requested_count;
3189 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3190 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3191 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3192 left_rate_per_vp, min_pf_rate);
3193 return -EINVAL;
3194 }
3195
3196 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3197 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3198
3199 for (i = 0; i < num_vports; i++) {
3200 if (p_hwfn->qm_info.wfq_data[i].configured)
3201 continue;
3202
3203 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3204 }
3205
3206 return 0;
3207}
3208
733def6a
YM		 3209static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3210 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3211{
3212 struct qed_mcp_link_state *p_link;
3213 int rc = 0;
3214
3215 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3216
3217 if (!p_link->min_pf_rate) {
3218 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3219 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3220 return rc;
3221 }
3222
3223 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3224
1a635e48 3225 if (!rc)
733def6a
YM		 3226 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3227 p_link->min_pf_rate);
3228 else
3229 DP_NOTICE(p_hwfn,
3230 "Validation failed while configuring min rate\n");
3231
3232 return rc;
3233}
3234
bcd197c8
MC		 3235static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3236 struct qed_ptt *p_ptt,
3237 u32 min_pf_rate)
3238{
3239 bool use_wfq = false;
3240 int rc = 0;
3241 u16 i;
3242
3243 /* Validate all pre configured vports for wfq */
3244 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3245 u32 rate;
3246
3247 if (!p_hwfn->qm_info.wfq_data[i].configured)
3248 continue;
3249
3250 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3251 use_wfq = true;
3252
3253 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3254 if (rc) {
3255 DP_NOTICE(p_hwfn,
3256 "WFQ validation failed while configuring min rate\n");
3257 break;
3258 }
3259 }
3260
3261 if (!rc && use_wfq)
3262 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3263 else
3264 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3265
3266 return rc;
3267}
3268
733def6a
YM		 3269/* Main API for qed clients to configure vport min rate.
3270 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3271 * rate - Speed in Mbps needs to be assigned to a given vport.
3272 */
3273int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3274{
3275 int i, rc = -EINVAL;
3276
3277 /* Currently not supported; Might change in future */
3278 if (cdev->num_hwfns > 1) {
3279 DP_NOTICE(cdev,
3280 "WFQ configuration is not supported for this device\n");
3281 return rc;
3282 }
3283
3284 for_each_hwfn(cdev, i) {
3285 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3286 struct qed_ptt *p_ptt;
3287
3288 p_ptt = qed_ptt_acquire(p_hwfn);
3289 if (!p_ptt)
3290 return -EBUSY;
3291
3292 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3293
d572c430 3294 if (rc) {
733def6a
YM		 3295 qed_ptt_release(p_hwfn, p_ptt);
3296 return rc;
3297 }
3298
3299 qed_ptt_release(p_hwfn, p_ptt);
3300 }
3301
3302 return rc;
3303}
3304
bcd197c8 3305/* API to configure WFQ from mcp link change */
6f437d43
MY		 3306void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3307 struct qed_ptt *p_ptt, u32 min_pf_rate)
bcd197c8
MC		 3308{
3309 int i;
3310
3e7cfce2
YM		 3311 if (cdev->num_hwfns > 1) {
3312 DP_VERBOSE(cdev,
3313 NETIF_MSG_LINK,
3314 "WFQ configuration is not supported for this device\n");
3315 return;
3316 }
3317
bcd197c8
MC		 3318 for_each_hwfn(cdev, i) {
3319 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3320
6f437d43 3321 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
bcd197c8
MC		 3322 min_pf_rate);
3323 }
3324}
4b01e519
MC		 3325
3326int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3327 struct qed_ptt *p_ptt,
3328 struct qed_mcp_link_state *p_link,
3329 u8 max_bw)
3330{
3331 int rc = 0;
3332
3333 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3334
3335 if (!p_link->line_speed && (max_bw != 100))
3336 return rc;
3337
3338 p_link->speed = (p_link->line_speed * max_bw) / 100;
3339 p_hwfn->qm_info.pf_rl = p_link->speed;
3340
3341 /* Since the limiter also affects Tx-switched traffic, we don't want it
3342 * to limit such traffic in case there's no actual limit.
3343 * In that case, set limit to imaginary high boundary.
3344 */
3345 if (max_bw == 100)
3346 p_hwfn->qm_info.pf_rl = 100000;
3347
3348 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3349 p_hwfn->qm_info.pf_rl);
3350
3351 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3352 "Configured MAX bandwidth to be %08x Mb/sec\n",
3353 p_link->speed);
3354
3355 return rc;
3356}
3357
3358/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3359int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3360{
3361 int i, rc = -EINVAL;
3362
3363 if (max_bw < 1 || max_bw > 100) {
3364 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3365 return rc;
3366 }
3367
3368 for_each_hwfn(cdev, i) {
3369 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3370 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3371 struct qed_mcp_link_state *p_link;
3372 struct qed_ptt *p_ptt;
3373
3374 p_link = &p_lead->mcp_info->link_output;
3375
3376 p_ptt = qed_ptt_acquire(p_hwfn);
3377 if (!p_ptt)
3378 return -EBUSY;
3379
3380 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3381 p_link, max_bw);
3382
3383 qed_ptt_release(p_hwfn, p_ptt);
3384
3385 if (rc)
3386 break;
3387 }
3388
3389 return rc;
3390}
a64b02d5
MC		 3391
3392int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3393 struct qed_ptt *p_ptt,
3394 struct qed_mcp_link_state *p_link,
3395 u8 min_bw)
3396{
3397 int rc = 0;
3398
3399 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3400 p_hwfn->qm_info.pf_wfq = min_bw;
3401
3402 if (!p_link->line_speed)
3403 return rc;
3404
3405 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3406
3407 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3408
3409 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3410 "Configured MIN bandwidth to be %d Mb/sec\n",
3411 p_link->min_pf_rate);
3412
3413 return rc;
3414}
3415
3416/* Main API to configure PF min bandwidth where bw range is [1-100] */
3417int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
3418{
3419 int i, rc = -EINVAL;
3420
3421 if (min_bw < 1 || min_bw > 100) {
3422 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
3423 return rc;
3424 }
3425
3426 for_each_hwfn(cdev, i) {
3427 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3428 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3429 struct qed_mcp_link_state *p_link;
3430 struct qed_ptt *p_ptt;
3431
3432 p_link = &p_lead->mcp_info->link_output;
3433
3434 p_ptt = qed_ptt_acquire(p_hwfn);
3435 if (!p_ptt)
3436 return -EBUSY;
3437
3438 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3439 p_link, min_bw);
3440 if (rc) {
3441 qed_ptt_release(p_hwfn, p_ptt);
3442 return rc;
3443 }
3444
3445 if (p_link->min_pf_rate) {
3446 u32 min_rate = p_link->min_pf_rate;
3447
3448 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
3449 p_ptt,
3450 min_rate);
3451 }
3452
3453 qed_ptt_release(p_hwfn, p_ptt);
3454 }
3455
3456 return rc;
3457}
733def6a
YM		 3458
3459void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3460{
3461 struct qed_mcp_link_state *p_link;
3462
3463 p_link = &p_hwfn->mcp_info->link_output;
3464
3465 if (p_link->min_pf_rate)
3466 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3467 p_link->min_pf_rate);
3468
3469 memset(p_hwfn->qm_info.wfq_data, 0,
3470 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
3471}
9c79ddaa
MY		 3472
3473int qed_device_num_engines(struct qed_dev *cdev)
3474{
3475 return QED_IS_BB(cdev) ? 2 : 1;
3476}
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