[linux.git] / drivers / ssb / driver_gige.c

/*
 * Sonics Silicon Backplane
 * Broadcom Gigabit Ethernet core driver
 *
 * Copyright 2008, Broadcom Corporation
 * Copyright 2008, Michael Buesch <[email protected]>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_driver_gige.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/slab.h>


/*
MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
MODULE_AUTHOR("Michael Buesch");
MODULE_LICENSE("GPL");
*/

static const struct ssb_device_id ssb_gige_tbl[] = {
	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
	{},
};
/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */


static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
{
	return ssb_read8(dev->dev, offset);
}

static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
{
	return ssb_read16(dev->dev, offset);
}

static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
{
	return ssb_read32(dev->dev, offset);
}

static inline void gige_write8(struct ssb_gige *dev,
			       u16 offset, u8 value)
{
	ssb_write8(dev->dev, offset, value);
}

static inline void gige_write16(struct ssb_gige *dev,
				u16 offset, u16 value)
{
	ssb_write16(dev->dev, offset, value);
}

static inline void gige_write32(struct ssb_gige *dev,
				u16 offset, u32 value)
{
	ssb_write32(dev->dev, offset, value);
}

static inline
u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
{
	BUG_ON(offset >= 256);
	return gige_read8(dev, SSB_GIGE_PCICFG + offset);
}

static inline
u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
{
	BUG_ON(offset >= 256);
	return gige_read16(dev, SSB_GIGE_PCICFG + offset);
}

static inline
u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
{
	BUG_ON(offset >= 256);
	return gige_read32(dev, SSB_GIGE_PCICFG + offset);
}

static inline
void gige_pcicfg_write8(struct ssb_gige *dev,
			unsigned int offset, u8 value)
{
	BUG_ON(offset >= 256);
	gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
}

static inline
void gige_pcicfg_write16(struct ssb_gige *dev,
			 unsigned int offset, u16 value)
{
	BUG_ON(offset >= 256);
	gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
}

static inline
void gige_pcicfg_write32(struct ssb_gige *dev,
			 unsigned int offset, u32 value)
{
	BUG_ON(offset >= 256);
	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
}

static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
				    int reg, int size, u32 *val)
{
	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
	unsigned long flags;

	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (reg >= 256)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&dev->lock, flags);
	switch (size) {
	case 1:
		*val = gige_pcicfg_read8(dev, reg);
		break;
	case 2:
		*val = gige_pcicfg_read16(dev, reg);
		break;
	case 4:
		*val = gige_pcicfg_read32(dev, reg);
		break;
	default:
		WARN_ON(1);
	}
	spin_unlock_irqrestore(&dev->lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
				     int reg, int size, u32 val)
{
	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
	unsigned long flags;

	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (reg >= 256)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&dev->lock, flags);
	switch (size) {
	case 1:
		gige_pcicfg_write8(dev, reg, val);
		break;
	case 2:
		gige_pcicfg_write16(dev, reg, val);
		break;
	case 4:
		gige_pcicfg_write32(dev, reg, val);
		break;
	default:
		WARN_ON(1);
	}
	spin_unlock_irqrestore(&dev->lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int ssb_gige_probe(struct ssb_device *sdev,
			  const struct ssb_device_id *id)
{
	struct ssb_gige *dev;
	u32 base, tmslow, tmshigh;

	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	if (!dev)
		return -ENOMEM;
	dev->dev = sdev;

	spin_lock_init(&dev->lock);
	dev->pci_controller.pci_ops = &dev->pci_ops;
	dev->pci_controller.io_resource = &dev->io_resource;
	dev->pci_controller.mem_resource = &dev->mem_resource;
	dev->pci_controller.io_map_base = 0x800;
	dev->pci_ops.read = ssb_gige_pci_read_config;
	dev->pci_ops.write = ssb_gige_pci_write_config;

	dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
	dev->io_resource.start = 0x800;
	dev->io_resource.end = 0x8FF;
	dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;

	if (!ssb_device_is_enabled(sdev))
		ssb_device_enable(sdev, 0);

	/* Setup BAR0. This is a 64k MMIO region. */
	base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);

	dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
	dev->mem_resource.start = base;
	dev->mem_resource.end = base + 0x10000 - 1;
	dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;

	/* Enable the memory region. */
	gige_pcicfg_write16(dev, PCI_COMMAND,
			    gige_pcicfg_read16(dev, PCI_COMMAND)
			    | PCI_COMMAND_MEMORY);

	/* Write flushing is controlled by the Flush Status Control register.
	 * We want to flush every register write with a timeout and we want
	 * to disable the IRQ mask while flushing to avoid concurrency.
	 * Note that automatic write flushing does _not_ work from
	 * an IRQ handler. The driver must flush manually by reading a register.
	 */
	gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);

	/* Check if we have an RGMII or GMII PHY-bus.
	 * On RGMII do not bypass the DLLs */
	tmslow = ssb_read32(sdev, SSB_TMSLOW);
	tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
	if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
		tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
		tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
		dev->has_rgmii = 1;
	} else {
		tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
		tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
		dev->has_rgmii = 0;
	}
	tmslow |= SSB_GIGE_TMSLOW_DLLEN;
	ssb_write32(sdev, SSB_TMSLOW, tmslow);

	ssb_set_drvdata(sdev, dev);
	register_pci_controller(&dev->pci_controller);

	return 0;
}

bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
{
	if (!pdev->resource[0].name)
		return false;
	return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
}
EXPORT_SYMBOL(pdev_is_ssb_gige_core);

int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
				   struct pci_dev *pdev)
{
	struct ssb_gige *dev = ssb_get_drvdata(sdev);
	struct resource *res;

	if (pdev->bus->ops != &dev->pci_ops) {
		/* The PCI device is not on this SSB GigE bridge device. */
		return -ENODEV;
	}

	/* Fixup the PCI resources. */
	res = &(pdev->resource[0]);
	res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
	res->name = dev->mem_resource.name;
	res->start = dev->mem_resource.start;
	res->end = dev->mem_resource.end;

	/* Fixup interrupt lines. */
	pdev->irq = ssb_mips_irq(sdev) + 2;
	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);

	return 0;
}

int ssb_gige_map_irq(struct ssb_device *sdev,
		     const struct pci_dev *pdev)
{
	struct ssb_gige *dev = ssb_get_drvdata(sdev);

	if (pdev->bus->ops != &dev->pci_ops) {
		/* The PCI device is not on this SSB GigE bridge device. */
		return -ENODEV;
	}

	return ssb_mips_irq(sdev) + 2;
}

static struct ssb_driver ssb_gige_driver = {
	.name		= "BCM-GigE",
	.id_table	= ssb_gige_tbl,
	.probe		= ssb_gige_probe,
};

int ssb_gige_init(void)
{
	return ssb_driver_register(&ssb_gige_driver);
}
Commit	Line	Data
aab547ce MB	1	/*
	2	* Sonics Silicon Backplane
	3	* Broadcom Gigabit Ethernet core driver
	4	*
	5	* Copyright 2008, Broadcom Corporation
eb032b98	6	* Copyright 2008, Michael Buesch <[email protected]>
aab547ce MB	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
	11	#include <linux/ssb/ssb.h>
	12	#include <linux/ssb/ssb_driver_gige.h>
1014c22e	13	#include <linux/export.h>
aab547ce MB	14	#include <linux/pci.h>
aab547ce MB	15	#include <linux/pci_regs.h>
5a0e3ad6	16	#include <linux/slab.h>
aab547ce MB	17
	18
	19	/*
	20	MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
	21	MODULE_AUTHOR("Michael Buesch");
	22	MODULE_LICENSE("GPL");
	23	*/
	24
	25	static const struct ssb_device_id ssb_gige_tbl[] = {
	26	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
673e2baa	27	{},
aab547ce MB	28	};
	29	/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
	30
	31
	32	static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
	33	{
	34	return ssb_read8(dev->dev, offset);
	35	}
	36
	37	static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
	38	{
	39	return ssb_read16(dev->dev, offset);
	40	}
	41
	42	static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
	43	{
	44	return ssb_read32(dev->dev, offset);
	45	}
	46
	47	static inline void gige_write8(struct ssb_gige *dev,
	48	u16 offset, u8 value)
	49	{
	50	ssb_write8(dev->dev, offset, value);
	51	}
	52
	53	static inline void gige_write16(struct ssb_gige *dev,
	54	u16 offset, u16 value)
	55	{
	56	ssb_write16(dev->dev, offset, value);
	57	}
	58
	59	static inline void gige_write32(struct ssb_gige *dev,
	60	u16 offset, u32 value)
	61	{
	62	ssb_write32(dev->dev, offset, value);
	63	}
	64
	65	static inline
	66	u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
	67	{
	68	BUG_ON(offset >= 256);
	69	return gige_read8(dev, SSB_GIGE_PCICFG + offset);
	70	}
	71
	72	static inline
	73	u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
	74	{
	75	BUG_ON(offset >= 256);
	76	return gige_read16(dev, SSB_GIGE_PCICFG + offset);
	77	}
	78
	79	static inline
	80	u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
	81	{
	82	BUG_ON(offset >= 256);
	83	return gige_read32(dev, SSB_GIGE_PCICFG + offset);
	84	}
	85
	86	static inline
	87	void gige_pcicfg_write8(struct ssb_gige *dev,
	88	unsigned int offset, u8 value)
	89	{
	90	BUG_ON(offset >= 256);
	91	gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
92	}
93
94	static inline
95	void gige_pcicfg_write16(struct ssb_gige *dev,
96	unsigned int offset, u16 value)
97	{
98	BUG_ON(offset >= 256);
99	gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
100	}
101
102	static inline
103	void gige_pcicfg_write32(struct ssb_gige *dev,
104	unsigned int offset, u32 value)
105	{
106	BUG_ON(offset >= 256);
107	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
108	}
109
163247c1 GKH	110	static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
163247c1 GKH	111	int reg, int size, u32 *val)
aab547ce MB	112	{
	113	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
	114	unsigned long flags;
	115
	116	if ((PCI_SLOT(devfn) > 0) \|\| (PCI_FUNC(devfn) > 0))
	117	return PCIBIOS_DEVICE_NOT_FOUND;
	118	if (reg >= 256)
	119	return PCIBIOS_DEVICE_NOT_FOUND;
	120
	121	spin_lock_irqsave(&dev->lock, flags);
	122	switch (size) {
	123	case 1:
	124	*val = gige_pcicfg_read8(dev, reg);
	125	break;
	126	case 2:
	127	*val = gige_pcicfg_read16(dev, reg);
	128	break;
	129	case 4:
	130	*val = gige_pcicfg_read32(dev, reg);
	131	break;
	132	default:
	133	WARN_ON(1);
	134	}
	135	spin_unlock_irqrestore(&dev->lock, flags);
	136
	137	return PCIBIOS_SUCCESSFUL;
	138	}
	139
163247c1 GKH	140	static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
163247c1 GKH	141	int reg, int size, u32 val)
aab547ce MB	142	{
	143	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
	144	unsigned long flags;
	145
	146	if ((PCI_SLOT(devfn) > 0) \|\| (PCI_FUNC(devfn) > 0))
	147	return PCIBIOS_DEVICE_NOT_FOUND;
	148	if (reg >= 256)
	149	return PCIBIOS_DEVICE_NOT_FOUND;
	150
	151	spin_lock_irqsave(&dev->lock, flags);
	152	switch (size) {
	153	case 1:
	154	gige_pcicfg_write8(dev, reg, val);
	155	break;
	156	case 2:
	157	gige_pcicfg_write16(dev, reg, val);
	158	break;
	159	case 4:
	160	gige_pcicfg_write32(dev, reg, val);
	161	break;
	162	default:
	163	WARN_ON(1);
	164	}
	165	spin_unlock_irqrestore(&dev->lock, flags);
	166
	167	return PCIBIOS_SUCCESSFUL;
	168	}
	169
163247c1 GKH	170	static int ssb_gige_probe(struct ssb_device *sdev,
163247c1 GKH	171	const struct ssb_device_id *id)
aab547ce MB	172	{
	173	struct ssb_gige *dev;
	174	u32 base, tmslow, tmshigh;
	175
	176	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	177	if (!dev)
	178	return -ENOMEM;
	179	dev->dev = sdev;
	180
	181	spin_lock_init(&dev->lock);
	182	dev->pci_controller.pci_ops = &dev->pci_ops;
	183	dev->pci_controller.io_resource = &dev->io_resource;
	184	dev->pci_controller.mem_resource = &dev->mem_resource;
	185	dev->pci_controller.io_map_base = 0x800;
	186	dev->pci_ops.read = ssb_gige_pci_read_config;
	187	dev->pci_ops.write = ssb_gige_pci_write_config;
	188
	189	dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
	190	dev->io_resource.start = 0x800;
	191	dev->io_resource.end = 0x8FF;
	192	dev->io_resource.flags = IORESOURCE_IO \| IORESOURCE_PCI_FIXED;
	193
	194	if (!ssb_device_is_enabled(sdev))
	195	ssb_device_enable(sdev, 0);
	196
	197	/* Setup BAR0. This is a 64k MMIO region. */
	198	base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
	199	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
	200	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
	201
	202	dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
	203	dev->mem_resource.start = base;
	204	dev->mem_resource.end = base + 0x10000 - 1;
	205	dev->mem_resource.flags = IORESOURCE_MEM \| IORESOURCE_PCI_FIXED;
	206
	207	/* Enable the memory region. */
	208	gige_pcicfg_write16(dev, PCI_COMMAND,
	209	gige_pcicfg_read16(dev, PCI_COMMAND)
	210	\| PCI_COMMAND_MEMORY);
	211
	212	/* Write flushing is controlled by the Flush Status Control register.
	213	* We want to flush every register write with a timeout and we want
	214	* to disable the IRQ mask while flushing to avoid concurrency.
	215	* Note that automatic write flushing does _not_ work from
	216	* an IRQ handler. The driver must flush manually by reading a register.
	217	*/
	218	gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
	219
	220	/* Check if we have an RGMII or GMII PHY-bus.
	221	* On RGMII do not bypass the DLLs */
	222	tmslow = ssb_read32(sdev, SSB_TMSLOW);
	223	tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
	224	if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
	225	tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
	226	tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
	227	dev->has_rgmii = 1;
	228	} else {
	229	tmslow \|= SSB_GIGE_TMSLOW_TXBYPASS;
	230	tmslow \|= SSB_GIGE_TMSLOW_RXBYPASS;
	231	dev->has_rgmii = 0;
	232	}
	233	tmslow \|= SSB_GIGE_TMSLOW_DLLEN;
	234	ssb_write32(sdev, SSB_TMSLOW, tmslow);
	235
236	ssb_set_drvdata(sdev, dev);
237	register_pci_controller(&dev->pci_controller);
238
239	return 0;
240	}
241
242	bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
243	{
244	if (!pdev->resource[0].name)
c7743c42	245	return false;
aab547ce MB	246	return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
	247	}
	248	EXPORT_SYMBOL(pdev_is_ssb_gige_core);
	249
	250	int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
	251	struct pci_dev *pdev)
	252	{
	253	struct ssb_gige *dev = ssb_get_drvdata(sdev);
	254	struct resource *res;
	255
	256	if (pdev->bus->ops != &dev->pci_ops) {
	257	/* The PCI device is not on this SSB GigE bridge device. */
	258	return -ENODEV;
	259	}
	260
	261	/* Fixup the PCI resources. */
	262	res = &(pdev->resource[0]);
	263	res->flags = IORESOURCE_MEM \| IORESOURCE_PCI_FIXED;
	264	res->name = dev->mem_resource.name;
	265	res->start = dev->mem_resource.start;
	266	res->end = dev->mem_resource.end;
	267
	268	/* Fixup interrupt lines. */
	269	pdev->irq = ssb_mips_irq(sdev) + 2;
	270	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
	271
	272	return 0;
	273	}
	274
	275	int ssb_gige_map_irq(struct ssb_device *sdev,
	276	const struct pci_dev *pdev)
	277	{
	278	struct ssb_gige *dev = ssb_get_drvdata(sdev);
	279
	280	if (pdev->bus->ops != &dev->pci_ops) {
	281	/* The PCI device is not on this SSB GigE bridge device. */
	282	return -ENODEV;
	283	}
	284
	285	return ssb_mips_irq(sdev) + 2;
	286	}
	287
	288	static struct ssb_driver ssb_gige_driver = {
	289	.name = "BCM-GigE",
	290	.id_table = ssb_gige_tbl,
	291	.probe = ssb_gige_probe,
	292	};
	293
	294	int ssb_gige_init(void)
	295	{
	296	return ssb_driver_register(&ssb_gige_driver);
	297	}