[linux.git] / drivers / ata / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <[email protected]> and
 *		   Jeff Garzik <[email protected]>
 *  		    Please ALWAYS copy [email protected]
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <[email protected]>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi.h>
#include <linux/libata.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif /* CONFIG_PPC_OF */

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"2.3"

enum {
	/* ap->flags bits */
	K2_FLAG_SATA_8_PORTS		= (1 << 24),
	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
	K2_FLAG_BAR_POS_3			= (1 << 26),

	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,

	chip_svw4			= 0,
	chip_svw8			= 1,
	chip_svw42			= 2,	/* bar 3 */
	chip_svw43			= 3,	/* bar 5 */
};

static u8 k2_stat_check_status(struct ata_port *ap);


static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 cmnd = qc->scsicmd->cmnd[0];

	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
		return -1;	/* ATAPI DMA not supported */
	else {
		switch (cmnd) {
		case READ_10:
		case READ_12:
		case READ_16:
		case WRITE_10:
		case WRITE_12:
		case WRITE_16:
			return 0;

		default:
			return -1;
		}

	}
}

static int k2_sata_scr_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int k2_sata_scr_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* This works around possible data corruption.

	   On certain SATA controllers that can be seen when the r/w
	   command is given to the controller before the host DMA is
	   started.

	   On a Read command, the controller would initiate the
	   command to the drive even before it sees the DMA
	   start. When there are very fast drives connected to the
	   controller, or when the data request hits in the drive
	   cache, there is the possibility that the drive returns a
	   part or all of the requested data to the controller before
	   the DMA start is issued.  In this case, the controller
	   would become confused as to what to do with the data.  In
	   the worst case when all the data is returned back to the
	   controller, the controller could hang. In other cases it
	   could return partial data returning in data
	   corruption. This problem has been seen in PPC systems and
	   can also appear on an system with very fast disks, where
	   the SATA controller is sitting behind a number of bridges,
	   and hence there is significant latency between the r/w
	   command and the start command. */
	/* issue r/w command if the access is to ATA */
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
	return readl(ap->ioaddr.status_addr);
}

#ifdef CONFIG_PPC_OF
/*
 * k2_sata_proc_info
 * inout : decides on the direction of the dataflow and the meaning of the
 *	   variables
 * buffer: If inout==FALSE data is being written to it else read from it
 * *start: If inout==FALSE start of the valid data in the buffer
 * offset: If inout==FALSE offset from the beginning of the imaginary file
 *	   from which we start writing into the buffer
 * length: If inout==FALSE max number of bytes to be written into the buffer
 *	   else number of bytes in the buffer
 */
static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
			     off_t offset, int count, int inout)
{
	struct ata_port *ap;
	struct device_node *np;
	int len, index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		const u32 *reg = of_get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg)
			break;
	}
	if (np == NULL)
		return 0;

	len = sprintf(page, "devspec: %s\n", np->full_name);

	return len;
}
#endif /* CONFIG_PPC_OF */


static struct scsi_host_template k2_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
#ifdef CONFIG_PPC_OF
	.proc_info		= k2_sata_proc_info,
#endif
};


static struct ata_port_operations k2_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.sff_tf_load		= k2_sata_tf_load,
	.sff_tf_read		= k2_sata_tf_read,
	.sff_check_status	= k2_stat_check_status,
	.check_atapi_dma	= k2_sata_check_atapi_dma,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
};

static const struct ata_port_info k2_port_info[] = {
	/* chip_svw4 */
	{
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw8 */
	{
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
				  K2_FLAG_SATA_8_PORTS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw42 */
	{
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO | K2_FLAG_BAR_POS_3,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw43 */
	{
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
};

static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	const struct ata_port_info *ppi[] =
		{ &k2_port_info[ent->driver_data], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int n_ports, i, rc, bar_pos;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/* allocate host */
	n_ports = 4;
	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
		n_ports = 8;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host)
		return -ENOMEM;

	bar_pos = 5;
	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
		bar_pos = 3;
	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, bar_pos) == 0) {
		/* In IDE mode we need to pin the device to ensure that
			pcim_release does not clear the busmaster bit in config
			space, clearing causes busmaster DMA to fail on
			ports 3 & 4 */
		pcim_pin_device(pdev);
		return -ENODEV;
	}

	/* Request and iomap PCI regions */
	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[bar_pos];

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = i * K2_SATA_PORT_OFFSET;

		k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, 5, -1, "mmio");
		ata_port_pbar_desc(ap, 5, offset, "port");
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
				 IRQF_SHARED, &k2_sata_sht);
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },

	{ }
};

static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};

static int __init k2_sata_init(void)
{
	return pci_register_driver(&k2_sata_pci_driver);
}

static void __exit k2_sata_exit(void)
{
	pci_unregister_driver(&k2_sata_pci_driver);
}

MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(k2_sata_init);
module_exit(k2_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <[email protected]> and
	5	* Jeff Garzik <[email protected]>
	6	* Please ALWAYS copy [email protected]
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <[email protected]>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
1da177e4 LT	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/pci.h>
	42	#include <linux/init.h>
	43	#include <linux/blkdev.h>
	44	#include <linux/delay.h>
	45	#include <linux/interrupt.h>
a9524a76	46	#include <linux/device.h>
1da177e4	47	#include <scsi/scsi_host.h>
931506d3 AS	48	#include <scsi/scsi_cmnd.h>
931506d3 AS	49	#include <scsi/scsi.h>
1da177e4 LT	50	#include <linux/libata.h>
	51
	52	#ifdef CONFIG_PPC_OF
	53	#include <asm/prom.h>
	54	#include <asm/pci-bridge.h>
	55	#endif /* CONFIG_PPC_OF */
	56
	57	#define DRV_NAME "sata_svw"
2a3103ce	58	#define DRV_VERSION "2.3"
1da177e4	59
55cca65e	60	enum {
4447d351 TH	61	/* ap->flags bits */
	62	K2_FLAG_SATA_8_PORTS = (1 << 24),
	63	K2_FLAG_NO_ATAPI_DMA = (1 << 25),
931506d3	64	K2_FLAG_BAR_POS_3 = (1 << 26),
c10340ac	65
55cca65e JG	66	/* Taskfile registers offsets */
	67	K2_SATA_TF_CMD_OFFSET = 0x00,
	68	K2_SATA_TF_DATA_OFFSET = 0x00,
	69	K2_SATA_TF_ERROR_OFFSET = 0x04,
	70	K2_SATA_TF_NSECT_OFFSET = 0x08,
	71	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	72	K2_SATA_TF_LBAM_OFFSET = 0x10,
	73	K2_SATA_TF_LBAH_OFFSET = 0x14,
	74	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	75	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	76	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	77
55cca65e JG	78	/* DMA base */
55cca65e JG	79	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	80
55cca65e JG	81	/* SCRs base */
	82	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	83	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	84	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	85
55cca65e JG	86	/* Others */
	87	K2_SATA_SICR1_OFFSET = 0x80,
	88	K2_SATA_SICR2_OFFSET = 0x84,
	89	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	90
55cca65e JG	91	/* Port stride */
55cca65e JG	92	K2_SATA_PORT_OFFSET = 0x100,
c10340ac	93
931506d3 AS	94	chip_svw4 = 0,
	95	chip_svw8 = 1,
	96	chip_svw42 = 2, /* bar 3 */
	97	chip_svw43 = 3, /* bar 5 */
c10340ac JG	98	};
c10340ac JG	99
ac19bff2 JG	100	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	101
1da177e4	102
c10340ac JG	103	static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
c10340ac JG	104	{
931506d3 AS	105	u8 cmnd = qc->scsicmd->cmnd[0];
931506d3 AS	106
c10340ac JG	107	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
c10340ac JG	108	return -1; /* ATAPI DMA not supported */
931506d3 AS	109	else {
	110	switch (cmnd) {
	111	case READ_10:
	112	case READ_12:
	113	case READ_16:
	114	case WRITE_10:
	115	case WRITE_12:
	116	case WRITE_16:
	117	return 0;
	118
	119	default:
	120	return -1;
	121	}
c10340ac	122
931506d3	123	}
c10340ac JG	124	}
c10340ac JG	125
82ef04fb TH	126	static int k2_sata_scr_read(struct ata_link *link,
82ef04fb TH	127	unsigned int sc_reg, u32 *val)
1da177e4 LT	128	{
1da177e4 LT	129	if (sc_reg > SCR_CONTROL)
da3dbb17	130	return -EINVAL;
82ef04fb	131	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	132	return 0;
1da177e4 LT	133	}
	134
	135
82ef04fb TH	136	static int k2_sata_scr_write(struct ata_link *link,
82ef04fb TH	137	unsigned int sc_reg, u32 val)
1da177e4 LT	138	{
1da177e4 LT	139	if (sc_reg > SCR_CONTROL)
da3dbb17	140	return -EINVAL;
82ef04fb	141	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	142	return 0;
1da177e4 LT	143	}
	144
	145
057ace5e	146	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	147	{
	148	struct ata_ioports *ioaddr = &ap->ioaddr;
	149	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	150
	151	if (tf->ctl != ap->last_ctl) {
0d5ff566	152	writeb(tf->ctl, ioaddr->ctl_addr);
1da177e4 LT	153	ap->last_ctl = tf->ctl;
	154	ata_wait_idle(ap);
	155	}
	156	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	157	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	158	ioaddr->feature_addr);
850a9d8a	159	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	160	ioaddr->nsect_addr);
850a9d8a	161	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	162	ioaddr->lbal_addr);
850a9d8a	163	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	164	ioaddr->lbam_addr);
850a9d8a	165	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	166	ioaddr->lbah_addr);
1da177e4	167	} else if (is_addr) {
0d5ff566 TH	168	writew(tf->feature, ioaddr->feature_addr);
	169	writew(tf->nsect, ioaddr->nsect_addr);
	170	writew(tf->lbal, ioaddr->lbal_addr);
	171	writew(tf->lbam, ioaddr->lbam_addr);
	172	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	173	}
	174
	175	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	176	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	177
	178	ata_wait_idle(ap);
	179	}
	180
	181
	182	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	183	{
	184	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	185	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	186
ac19bff2	187	tf->command = k2_stat_check_status(ap);
0d5ff566 TH	188	tf->device = readw(ioaddr->device_addr);
	189	feature = readw(ioaddr->error_addr);
	190	nsect = readw(ioaddr->nsect_addr);
	191	lbal = readw(ioaddr->lbal_addr);
	192	lbam = readw(ioaddr->lbam_addr);
	193	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	194
	195	tf->feature = feature;
	196	tf->nsect = nsect;
	197	tf->lbal = lbal;
	198	tf->lbam = lbam;
	199	tf->lbah = lbah;
1da177e4 LT	200
1da177e4 LT	201	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	202	tf->hob_feature = feature >> 8;
1da177e4 LT	203	tf->hob_nsect = nsect >> 8;
	204	tf->hob_lbal = lbal >> 8;
	205	tf->hob_lbam = lbam >> 8;
	206	tf->hob_lbah = lbah >> 8;
5796d1c4	207	}
1da177e4 LT	208	}
	209
	210	/**
	211	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	212	* @qc: Info associated with this ATA transaction.
	213	*
	214	* LOCKING:
cca3974e	215	* spin_lock_irqsave(host lock)
1da177e4 LT	216	*/
1da177e4 LT	217
5796d1c4	218	static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	219	{
	220	struct ata_port *ap = qc->ap;
	221	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	222	u8 dmactl;
59f99880 JG	223	void __iomem *mmio = ap->ioaddr.bmdma_addr;
59f99880 JG	224
1da177e4 LT	225	/* load PRD table addr. */
	226	mb(); /* make sure PRD table writes are visible to controller */
	227	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
	228
	229	/* specify data direction, triple-check start bit is clear */
	230	dmactl = readb(mmio + ATA_DMA_CMD);
	231	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	232	if (!rw)
	233	dmactl \|= ATA_DMA_WR;
	234	writeb(dmactl, mmio + ATA_DMA_CMD);
	235
	236	/* issue r/w command if this is not a ATA DMA command*/
	237	if (qc->tf.protocol != ATA_PROT_DMA)
5682ed33	238	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	239	}
	240
	241	/**
	242	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	243	* @qc: Info associated with this ATA transaction.
	244	*
	245	* LOCKING:
cca3974e	246	* spin_lock_irqsave(host lock)
1da177e4 LT	247	*/
1da177e4 LT	248
5796d1c4	249	static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	250	{
1da177e4 LT	251	struct ata_port *ap = qc->ap;
59f99880	252	void __iomem *mmio = ap->ioaddr.bmdma_addr;
1da177e4 LT	253	u8 dmactl;
	254
	255	/* start host DMA transaction */
	256	dmactl = readb(mmio + ATA_DMA_CMD);
	257	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
ec6add99 PM	258	/* This works around possible data corruption.
	259
	260	On certain SATA controllers that can be seen when the r/w
	261	command is given to the controller before the host DMA is
	262	started.
	263
	264	On a Read command, the controller would initiate the
	265	command to the drive even before it sees the DMA
	266	start. When there are very fast drives connected to the
	267	controller, or when the data request hits in the drive
	268	cache, there is the possibility that the drive returns a
	269	part or all of the requested data to the controller before
	270	the DMA start is issued. In this case, the controller
	271	would become confused as to what to do with the data. In
	272	the worst case when all the data is returned back to the
	273	controller, the controller could hang. In other cases it
	274	could return partial data returning in data
	275	corruption. This problem has been seen in PPC systems and
	276	can also appear on an system with very fast disks, where
	277	the SATA controller is sitting behind a number of bridges,
	278	and hence there is significant latency between the r/w
	279	command and the start command. */
	280	/* issue r/w command if the access is to ATA */
1da177e4	281	if (qc->tf.protocol == ATA_PROT_DMA)
5682ed33	282	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	283	}
1da177e4 LT	284
8a60a071	285
1da177e4 LT	286	static u8 k2_stat_check_status(struct ata_port *ap)
1da177e4 LT	287	{
5796d1c4	288	return readl(ap->ioaddr.status_addr);
1da177e4 LT	289	}
	290
	291	#ifdef CONFIG_PPC_OF
	292	/*
	293	* k2_sata_proc_info
	294	* inout : decides on the direction of the dataflow and the meaning of the
	295	* variables
	296	* buffer: If inout==FALSE data is being written to it else read from it
	297	* *start: If inout==FALSE start of the valid data in the buffer
	298	* offset: If inout==FALSE offset from the beginning of the imaginary file
	299	* from which we start writing into the buffer
	300	* length: If inout==FALSE max number of bytes to be written into the buffer
	301	* else number of bytes in the buffer
	302	*/
	303	static int k2_sata_proc_info(struct Scsi_Host shost, char page, char **start,
	304	off_t offset, int count, int inout)
	305	{
	306	struct ata_port *ap;
	307	struct device_node *np;
	308	int len, index;
	309
	310	/* Find the ata_port */
35bb94b1	311	ap = ata_shost_to_port(shost);
1da177e4 LT	312	if (ap == NULL)
	313	return 0;
	314
	315	/* Find the OF node for the PCI device proper */
cca3974e	316	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
1da177e4 LT	317	if (np == NULL)
	318	return 0;
	319
	320	/* Match it to a port node */
cca3974e	321	index = (ap == ap->host->ports[0]) ? 0 : 1;
1da177e4	322	for (np = np->child; np != NULL; np = np->sibling) {
40cd3a45	323	const u32 *reg = of_get_property(np, "reg", NULL);
1da177e4 LT	324	if (!reg)
	325	continue;
	326	if (index == *reg)
	327	break;
	328	}
	329	if (np == NULL)
	330	return 0;
	331
	332	len = sprintf(page, "devspec: %s\n", np->full_name);
	333
	334	return len;
	335	}
	336	#endif /* CONFIG_PPC_OF */
	337
	338
193515d5	339	static struct scsi_host_template k2_sata_sht = {
68d1d07b	340	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	341	#ifdef CONFIG_PPC_OF
	342	.proc_info = k2_sata_proc_info,
	343	#endif
1da177e4 LT	344	};
	345
	346
029cfd6b TH	347	static struct ata_port_operations k2_sata_ops = {
029cfd6b TH	348	.inherits = &ata_bmdma_port_ops,
5682ed33 TH	349	.sff_tf_load = k2_sata_tf_load,
	350	.sff_tf_read = k2_sata_tf_read,
	351	.sff_check_status = k2_stat_check_status,
c10340ac	352	.check_atapi_dma = k2_sata_check_atapi_dma,
1da177e4 LT	353	.bmdma_setup = k2_bmdma_setup_mmio,
1da177e4 LT	354	.bmdma_start = k2_bmdma_start_mmio,
1da177e4 LT	355	.scr_read = k2_sata_scr_read,
1da177e4 LT	356	.scr_write = k2_sata_scr_write,
1da177e4 LT	357	};
1da177e4 LT	358
4447d351	359	static const struct ata_port_info k2_port_info[] = {
931506d3	360	/* chip_svw4 */
4447d351 TH	361	{
	362	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	363	ATA_FLAG_MMIO \| K2_FLAG_NO_ATAPI_DMA,
14bdef98 EIB	364	.pio_mask = ATA_PIO4,
14bdef98 EIB	365	.mwdma_mask = ATA_MWDMA2,
bf6263a8	366	.udma_mask = ATA_UDMA6,
4447d351 TH	367	.port_ops = &k2_sata_ops,
4447d351 TH	368	},
931506d3	369	/* chip_svw8 */
4447d351 TH	370	{
	371	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	372	ATA_FLAG_MMIO \| K2_FLAG_NO_ATAPI_DMA \|
	373	K2_FLAG_SATA_8_PORTS,
14bdef98 EIB	374	.pio_mask = ATA_PIO4,
14bdef98 EIB	375	.mwdma_mask = ATA_MWDMA2,
bf6263a8	376	.udma_mask = ATA_UDMA6,
4447d351 TH	377	.port_ops = &k2_sata_ops,
4447d351 TH	378	},
931506d3 AS	379	/* chip_svw42 */
	380	{
	381	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	382	ATA_FLAG_MMIO \| K2_FLAG_BAR_POS_3,
14bdef98 EIB	383	.pio_mask = ATA_PIO4,
14bdef98 EIB	384	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	385	.udma_mask = ATA_UDMA6,
	386	.port_ops = &k2_sata_ops,
	387	},
	388	/* chip_svw43 */
	389	{
	390	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	391	ATA_FLAG_MMIO,
14bdef98 EIB	392	.pio_mask = ATA_PIO4,
14bdef98 EIB	393	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	394	.udma_mask = ATA_UDMA6,
	395	.port_ops = &k2_sata_ops,
	396	},
4447d351 TH	397	};
4447d351 TH	398
0d5ff566	399	static void k2_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	400	{
	401	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	402	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	403	port->feature_addr =
	404	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	405	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	406	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	407	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	408	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	409	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	410	port->command_addr =
	411	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	412	port->altstatus_addr =
	413	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	414	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	415	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	416	}
	417
	418
5796d1c4	419	static int k2_sata_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4 LT	420	{
1da177e4 LT	421	static int printed_version;
4447d351 TH	422	const struct ata_port_info *ppi[] =
	423	{ &k2_port_info[ent->driver_data], NULL };
	424	struct ata_host *host;
ea6ba10b	425	void __iomem *mmio_base;
931506d3	426	int n_ports, i, rc, bar_pos;
1da177e4 LT	427
1da177e4 LT	428	if (!printed_version++)
a9524a76	429	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	430
4447d351 TH	431	/* allocate host */
	432	n_ports = 4;
	433	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
	434	n_ports = 8;
	435
	436	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	437	if (!host)
	438	return -ENOMEM;
	439
931506d3 AS	440	bar_pos = 5;
	441	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
	442	bar_pos = 3;
1da177e4 LT	443	/*
	444	* If this driver happens to only be useful on Apple's K2, then
	445	* we should check that here as it has a normal Serverworks ID
	446	*/
24dc5f33	447	rc = pcim_enable_device(pdev);
1da177e4 LT	448	if (rc)
1da177e4 LT	449	return rc;
4447d351	450
1da177e4 LT	451	/*
	452	* Check if we have resources mapped at all (second function may
	453	* have been disabled by firmware)
	454	*/
931506d3 AS	455	if (pci_resource_len(pdev, bar_pos) == 0) {
	456	/* In IDE mode we need to pin the device to ensure that
	457	pcim_release does not clear the busmaster bit in config
	458	space, clearing causes busmaster DMA to fail on
	459	ports 3 & 4 */
	460	pcim_pin_device(pdev);
1da177e4	461	return -ENODEV;
931506d3	462	}
1da177e4	463
0d5ff566	464	/* Request and iomap PCI regions */
931506d3	465	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0d5ff566	466	if (rc == -EBUSY)
24dc5f33	467	pcim_pin_device(pdev);
0d5ff566	468	if (rc)
24dc5f33	469	return rc;
4447d351	470	host->iomap = pcim_iomap_table(pdev);
931506d3	471	mmio_base = host->iomap[bar_pos];
4447d351 TH	472
	473	/* different controllers have different number of ports - currently 4 or 8 */
	474	/* All ports are on the same function. Multi-function device is no
	475	* longer available. This should not be seen in any system. */
cbcdd875 TH	476	for (i = 0; i < host->n_ports; i++) {
	477	struct ata_port *ap = host->ports[i];
	478	unsigned int offset = i * K2_SATA_PORT_OFFSET;
	479
	480	k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	481
	482	ata_port_pbar_desc(ap, 5, -1, "mmio");
	483	ata_port_pbar_desc(ap, 5, offset, "port");
	484	}
1da177e4 LT	485
	486	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	487	if (rc)
24dc5f33	488	return rc;
1da177e4 LT	489	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1da177e4 LT	490	if (rc)
24dc5f33	491	return rc;
1da177e4	492
0d5ff566 TH	493	/* Clear a magic bit in SCR1 according to Darwin, those help
	494	* some funky seagate drives (though so far, those were already
	495	* set by the firmware on the machines I had access to)
	496	*/
	497	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	498	mmio_base + K2_SATA_SICR1_OFFSET);
	499
	500	/* Clear SATA error & interrupts we don't use */
	501	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	502	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
1da177e4 LT	503
1da177e4 LT	504	pci_set_master(pdev);
9363c382 TH	505	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
9363c382 TH	506	IRQF_SHARED, &k2_sata_sht);
1da177e4 LT	507	}
1da177e4 LT	508
60bf09a3 NS	509	/* 0x240 is device ID for Apple K2 device
	510	* 0x241 is device ID for Serverworks Frodo4
	511	* 0x242 is device ID for Serverworks Frodo8
	512	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	513	* controller
	514	* */
3b7d697d	515	static const struct pci_device_id k2_sata_pci_tbl[] = {
931506d3	516	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
aeb74914 JG	517	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
aeb74914 JG	518	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
931506d3 AS	519	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	520	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	521	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	522	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
2d2744fc	523
1da177e4 LT	524	{ }
	525	};
	526
1da177e4 LT	527	static struct pci_driver k2_sata_pci_driver = {
	528	.name = DRV_NAME,
	529	.id_table = k2_sata_pci_tbl,
	530	.probe = k2_sata_init_one,
	531	.remove = ata_pci_remove_one,
	532	};
	533
1da177e4 LT	534	static int __init k2_sata_init(void)
1da177e4 LT	535	{
b7887196	536	return pci_register_driver(&k2_sata_pci_driver);
1da177e4 LT	537	}
1da177e4 LT	538
1da177e4 LT	539	static void __exit k2_sata_exit(void)
	540	{
	541	pci_unregister_driver(&k2_sata_pci_driver);
	542	}
	543
1da177e4 LT	544	MODULE_AUTHOR("Benjamin Herrenschmidt");
	545	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	546	MODULE_LICENSE("GPL");
	547	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	548	MODULE_VERSION(DRV_VERSION);
	549
	550	module_init(k2_sata_init);
	551	module_exit(k2_sata_exit);