[linux.git] / drivers / ssb / driver_mipscore.c

/*
 * Sonics Silicon Backplane
 * Broadcom MIPS core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <[email protected]>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/ssb/ssb.h>

#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/time.h>

#include "ssb_private.h"


static inline u32 mips_read32(struct ssb_mipscore *mcore,
			      u16 offset)
{
	return ssb_read32(mcore->dev, offset);
}

static inline void mips_write32(struct ssb_mipscore *mcore,
				u16 offset,
				u32 value)
{
	ssb_write32(mcore->dev, offset, value);
}

static const u32 ipsflag_irq_mask[] = {
	0,
	SSB_IPSFLAG_IRQ1,
	SSB_IPSFLAG_IRQ2,
	SSB_IPSFLAG_IRQ3,
	SSB_IPSFLAG_IRQ4,
};

static const u32 ipsflag_irq_shift[] = {
	0,
	SSB_IPSFLAG_IRQ1_SHIFT,
	SSB_IPSFLAG_IRQ2_SHIFT,
	SSB_IPSFLAG_IRQ3_SHIFT,
	SSB_IPSFLAG_IRQ4_SHIFT,
};

static inline u32 ssb_irqflag(struct ssb_device *dev)
{
	return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
}

/* Get the MIPS IRQ assignment for a specified device.
 * If unassigned, 0 is returned.
 */
unsigned int ssb_mips_irq(struct ssb_device *dev)
{
	struct ssb_bus *bus = dev->bus;
	u32 irqflag;
	u32 ipsflag;
	u32 tmp;
	unsigned int irq;

	irqflag = ssb_irqflag(dev);
	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	for (irq = 1; irq <= 4; irq++) {
		tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
		if (tmp == irqflag)
			break;
	}
	if (irq	== 5)
		irq = 0;

	return irq;
}

static void clear_irq(struct ssb_bus *bus, unsigned int irq)
{
	struct ssb_device *dev = bus->mipscore.dev;

	/* Clear the IRQ in the MIPScore backplane registers */
	if (irq == 0) {
		ssb_write32(dev, SSB_INTVEC, 0);
	} else {
		ssb_write32(dev, SSB_IPSFLAG,
			    ssb_read32(dev, SSB_IPSFLAG) |
			    ipsflag_irq_mask[irq]);
	}
}

static void set_irq(struct ssb_device *dev, unsigned int irq)
{
	unsigned int oldirq = ssb_mips_irq(dev);
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag = ssb_irqflag(dev);

	dev->irq = irq + 2;

	ssb_dprintk(KERN_INFO PFX
		    "set_irq: core 0x%04x, irq %d => %d\n",
		    dev->id.coreid, oldirq, irq);
	/* clear the old irq */
	if (oldirq == 0)
		ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
	else
		clear_irq(bus, oldirq);

	/* assign the new one */
	if (irq == 0) {
		ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
	} else {
		irqflag <<= ipsflag_irq_shift[irq];
		irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
		ssb_write32(mdev, SSB_IPSFLAG, irqflag);
	}
}

static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;

	if (bus->extif.dev)
		mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
	else if (bus->chipco.dev)
		mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	else
		mcore->nr_serial_ports = 0;
}

static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;

	mcore->flash_buswidth = 2;
	if (bus->chipco.dev) {
		mcore->flash_window = 0x1c000000;
		mcore->flash_window_size = 0x02000000;
		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
		               & SSB_CHIPCO_CFG_DS16) == 0)
			mcore->flash_buswidth = 1;
	} else {
		mcore->flash_window = 0x1fc00000;
		mcore->flash_window_size = 0x00400000;
	}
}

u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;
	u32 pll_type, n, m, rate = 0;

	if (bus->extif.dev) {
		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
	} else if (bus->chipco.dev) {
		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	} else
		return 0;

	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
		rate = 200000000;
	} else {
		rate = ssb_calc_clock_rate(pll_type, n, m);
	}

	if (pll_type == SSB_PLLTYPE_6) {
		rate *= 2;
	}

	return rate;
}

void ssb_mipscore_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus;
	struct ssb_device *dev;
	unsigned long hz, ns;
	unsigned int irq, i;

	if (!mcore->dev)
		return; /* We don't have a MIPS core */

	ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");

	bus = mcore->dev->bus;
	hz = ssb_clockspeed(bus);
	if (!hz)
		hz = 100000000;
	ns = 1000000000 / hz;

	if (bus->extif.dev)
		ssb_extif_timing_init(&bus->extif, ns);
	else if (bus->chipco.dev)
		ssb_chipco_timing_init(&bus->chipco, ns);

	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
		dev = &(bus->devices[i]);
		dev->irq = ssb_mips_irq(dev) + 2;
		switch (dev->id.coreid) {
		case SSB_DEV_USB11_HOST:
			/* shouldn't need a separate irq line for non-4710, most of them have a proper
			 * external usb controller on the pci */
			if ((bus->chip_id == 0x4710) && (irq <= 4)) {
				set_irq(dev, irq++);
				break;
			}
			/* fallthrough */
		case SSB_DEV_PCI:
		case SSB_DEV_ETHERNET:
		case SSB_DEV_ETHERNET_GBIT:
		case SSB_DEV_80211:
		case SSB_DEV_USB20_HOST:
			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
			if (irq <= 4) {
				set_irq(dev, irq++);
				break;
			}
		}
	}

	ssb_mips_serial_init(mcore);
	ssb_mips_flash_detect(mcore);
}
Commit	Line	Data
61e115a5 MB	1	/*
	2	* Sonics Silicon Backplane
	3	* Broadcom MIPS core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
	6	* Copyright 2006, 2007, Michael Buesch <[email protected]>
	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
	11	#include <linux/ssb/ssb.h>
	12
	13	#include <linux/serial.h>
	14	#include <linux/serial_core.h>
	15	#include <linux/serial_reg.h>
	16	#include <linux/time.h>
	17
	18	#include "ssb_private.h"
	19
	20
	21	static inline u32 mips_read32(struct ssb_mipscore *mcore,
	22	u16 offset)
	23	{
	24	return ssb_read32(mcore->dev, offset);
	25	}
	26
	27	static inline void mips_write32(struct ssb_mipscore *mcore,
	28	u16 offset,
	29	u32 value)
	30	{
	31	ssb_write32(mcore->dev, offset, value);
	32	}
	33
	34	static const u32 ipsflag_irq_mask[] = {
	35	0,
	36	SSB_IPSFLAG_IRQ1,
	37	SSB_IPSFLAG_IRQ2,
	38	SSB_IPSFLAG_IRQ3,
	39	SSB_IPSFLAG_IRQ4,
	40	};
	41
	42	static const u32 ipsflag_irq_shift[] = {
	43	0,
	44	SSB_IPSFLAG_IRQ1_SHIFT,
	45	SSB_IPSFLAG_IRQ2_SHIFT,
	46	SSB_IPSFLAG_IRQ3_SHIFT,
	47	SSB_IPSFLAG_IRQ4_SHIFT,
	48	};
	49
	50	static inline u32 ssb_irqflag(struct ssb_device *dev)
	51	{
	52	return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	53	}
	54
	55	/* Get the MIPS IRQ assignment for a specified device.
	56	* If unassigned, 0 is returned.
	57	*/
	58	unsigned int ssb_mips_irq(struct ssb_device *dev)
	59	{
	60	struct ssb_bus *bus = dev->bus;
	61	u32 irqflag;
	62	u32 ipsflag;
	63	u32 tmp;
	64	unsigned int irq;
65
66	irqflag = ssb_irqflag(dev);
67	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
68	for (irq = 1; irq <= 4; irq++) {
69	tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
70	if (tmp == irqflag)
71	break;
72	}
73	if (irq == 5)
74	irq = 0;
75
76	return irq;
77	}
78
79	static void clear_irq(struct ssb_bus *bus, unsigned int irq)
80	{
81	struct ssb_device *dev = bus->mipscore.dev;
82
83	/* Clear the IRQ in the MIPScore backplane registers */
84	if (irq == 0) {
85	ssb_write32(dev, SSB_INTVEC, 0);
86	} else {
87	ssb_write32(dev, SSB_IPSFLAG,
88	ssb_read32(dev, SSB_IPSFLAG) \|
89	ipsflag_irq_mask[irq]);
90	}
91	}
92
93	static void set_irq(struct ssb_device *dev, unsigned int irq)
94	{
95	unsigned int oldirq = ssb_mips_irq(dev);
96	struct ssb_bus *bus = dev->bus;
97	struct ssb_device *mdev = bus->mipscore.dev;
98	u32 irqflag = ssb_irqflag(dev);
99
100	dev->irq = irq + 2;
101
102	ssb_dprintk(KERN_INFO PFX
103	"set_irq: core 0x%04x, irq %d => %d\n",
104	dev->id.coreid, oldirq, irq);
105	/* clear the old irq */
106	if (oldirq == 0)
107	ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
108	else
109	clear_irq(bus, oldirq);
110
111	/* assign the new one */
2633da23 MB	112	if (irq == 0) {
	113	ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) \| ssb_read32(mdev, SSB_INTVEC)));
	114	} else {
	115	irqflag <<= ipsflag_irq_shift[irq];
	116	irqflag \|= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
	117	ssb_write32(mdev, SSB_IPSFLAG, irqflag);
	118	}
61e115a5 MB	119	}
	120
	121	static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
	122	{
	123	struct ssb_bus *bus = mcore->dev->bus;
	124
	125	if (bus->extif.dev)
	126	mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
	127	else if (bus->chipco.dev)
	128	mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	129	else
	130	mcore->nr_serial_ports = 0;
	131	}
	132
	133	static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
	134	{
	135	struct ssb_bus *bus = mcore->dev->bus;
	136
	137	mcore->flash_buswidth = 2;
	138	if (bus->chipco.dev) {
	139	mcore->flash_window = 0x1c000000;
	140	mcore->flash_window_size = 0x02000000;
	141	if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
	142	& SSB_CHIPCO_CFG_DS16) == 0)
	143	mcore->flash_buswidth = 1;
	144	} else {
	145	mcore->flash_window = 0x1fc00000;
	146	mcore->flash_window_size = 0x00400000;
	147	}
	148	}
	149
	150	u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
	151	{
	152	struct ssb_bus *bus = mcore->dev->bus;
	153	u32 pll_type, n, m, rate = 0;
	154
	155	if (bus->extif.dev) {
	156	ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
	157	} else if (bus->chipco.dev) {
	158	ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	159	} else
	160	return 0;
	161
	162	if ((pll_type == SSB_PLLTYPE_5) \|\| (bus->chip_id == 0x5365)) {
	163	rate = 200000000;
	164	} else {
	165	rate = ssb_calc_clock_rate(pll_type, n, m);
	166	}
	167
	168	if (pll_type == SSB_PLLTYPE_6) {
	169	rate *= 2;
	170	}
	171
	172	return rate;
	173	}
	174
	175	void ssb_mipscore_init(struct ssb_mipscore *mcore)
	176	{
7007d00c	177	struct ssb_bus *bus;
61e115a5 MB	178	struct ssb_device *dev;
	179	unsigned long hz, ns;
	180	unsigned int irq, i;
	181
	182	if (!mcore->dev)
	183	return; /* We don't have a MIPS core */
	184
	185	ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
	186
7007d00c	187	bus = mcore->dev->bus;
61e115a5 MB	188	hz = ssb_clockspeed(bus);
	189	if (!hz)
	190	hz = 100000000;
	191	ns = 1000000000 / hz;
	192
	193	if (bus->extif.dev)
	194	ssb_extif_timing_init(&bus->extif, ns);
	195	else if (bus->chipco.dev)
	196	ssb_chipco_timing_init(&bus->chipco, ns);
	197
	198	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	199	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
	200	dev = &(bus->devices[i]);
	201	dev->irq = ssb_mips_irq(dev) + 2;
	202	switch (dev->id.coreid) {
	203	case SSB_DEV_USB11_HOST:
	204	/* shouldn't need a separate irq line for non-4710, most of them have a proper
	205	* external usb controller on the pci */
	206	if ((bus->chip_id == 0x4710) && (irq <= 4)) {
	207	set_irq(dev, irq++);
	208	break;
	209	}
	210	/* fallthrough */
	211	case SSB_DEV_PCI:
	212	case SSB_DEV_ETHERNET:
aab547ce	213	case SSB_DEV_ETHERNET_GBIT:
61e115a5 MB	214	case SSB_DEV_80211:
	215	case SSB_DEV_USB20_HOST:
	216	/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
	217	if (irq <= 4) {
	218	set_irq(dev, irq++);
	219	break;
	220	}
	221	}
	222	}
	223
	224	ssb_mips_serial_init(mcore);
	225	ssb_mips_flash_detect(mcore);
	226	}