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Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc
[linux.git] / drivers / net / wireless / rtlwifi / wifi.h
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <[email protected]>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <[email protected]>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_WIFI_H__
31#define __RTL_WIFI_H__
32
33#include <linux/sched.h>
34#include <linux/firmware.h>
0c817338 35#include <linux/etherdevice.h>
b08cd667 36#include <linux/vmalloc.h>
62e63975 37#include <linux/usb.h>
0c817338
LF		 38#include <net/mac80211.h>
39#include "debug.h"
40
41#define RF_CHANGE_BY_INIT 0
42#define RF_CHANGE_BY_IPS BIT(28)
43#define RF_CHANGE_BY_PS BIT(29)
44#define RF_CHANGE_BY_HW BIT(30)
45#define RF_CHANGE_BY_SW BIT(31)
46
47#define IQK_ADDA_REG_NUM 16
48#define IQK_MAC_REG_NUM 4
49
50#define MAX_KEY_LEN 61
51#define KEY_BUF_SIZE 5
52
53/* QoS related. */
54/*aci: 0x00 Best Effort*/
55/*aci: 0x01 Background*/
56/*aci: 0x10 Video*/
57/*aci: 0x11 Voice*/
58/*Max: define total number.*/
59#define AC0_BE 0
60#define AC1_BK 1
61#define AC2_VI 2
62#define AC3_VO 3
63#define AC_MAX 4
64#define QOS_QUEUE_NUM 4
65#define RTL_MAC80211_NUM_QUEUE 5
66
67#define QBSS_LOAD_SIZE 5
68#define MAX_WMMELE_LENGTH 64
69
3dad618b
C		 70#define TOTAL_CAM_ENTRY 32
71
0c817338
LF		 72/*slot time for 11g. */
73#define RTL_SLOT_TIME_9 9
74#define RTL_SLOT_TIME_20 20
75
76/*related with tcp/ip. */
77/*if_ehther.h*/
78#define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
79#define ETH_P_IP 0x0800 /*Internet Protocol packet */
80#define ETH_P_ARP 0x0806 /*Address Resolution packet */
81#define SNAP_SIZE 6
82#define PROTOC_TYPE_SIZE 2
83
84/*related with 802.11 frame*/
85#define MAC80211_3ADDR_LEN 24
86#define MAC80211_4ADDR_LEN 30
87
e97b775d
LF		 88#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
89#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
90#define MAX_PG_GROUP 13
91#define CHANNEL_GROUP_MAX_2G 3
92#define CHANNEL_GROUP_IDX_5GL 3
93#define CHANNEL_GROUP_IDX_5GM 6
94#define CHANNEL_GROUP_IDX_5GH 9
95#define CHANNEL_GROUP_MAX_5G 9
96#define CHANNEL_MAX_NUMBER_2G 14
97#define AVG_THERMAL_NUM 8
3dad618b 98#define MAX_TID_COUNT 9
e97b775d
LF		 99
100/* for early mode */
3dad618b 101#define FCS_LEN 4
e97b775d 102#define EM_HDR_LEN 8
0c817338
LF		 103enum intf_type {
104 INTF_PCI = 0,
105 INTF_USB = 1,
106};
107
108enum radio_path {
109 RF90_PATH_A = 0,
110 RF90_PATH_B = 1,
111 RF90_PATH_C = 2,
112 RF90_PATH_D = 3,
113};
114
115enum rt_eeprom_type {
116 EEPROM_93C46,
117 EEPROM_93C56,
118 EEPROM_BOOT_EFUSE,
119};
120
121enum rtl_status {
122 RTL_STATUS_INTERFACE_START = 0,
123};
124
125enum hardware_type {
126 HARDWARE_TYPE_RTL8192E,
127 HARDWARE_TYPE_RTL8192U,
128 HARDWARE_TYPE_RTL8192SE,
129 HARDWARE_TYPE_RTL8192SU,
130 HARDWARE_TYPE_RTL8192CE,
131 HARDWARE_TYPE_RTL8192CU,
132 HARDWARE_TYPE_RTL8192DE,
133 HARDWARE_TYPE_RTL8192DU,
e97b775d 134 HARDWARE_TYPE_RTL8723E,
18d30067 135 HARDWARE_TYPE_RTL8723U,
0c817338 136
e97b775d 137 /* keep it last */
0c817338
LF		 138 HARDWARE_TYPE_NUM
139};
140
e97b775d
LF		 141#define IS_HARDWARE_TYPE_8192SU(rtlhal) \
142 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
143#define IS_HARDWARE_TYPE_8192SE(rtlhal) \
144 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
62e63975
LF		 145#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
18d30067
G		 147#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
e97b775d
LF		 149#define IS_HARDWARE_TYPE_8192DE(rtlhal) \
150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
151#define IS_HARDWARE_TYPE_8192DU(rtlhal) \
152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
153#define IS_HARDWARE_TYPE_8723E(rtlhal) \
154 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
18d30067
G		 155#define IS_HARDWARE_TYPE_8723U(rtlhal) \
156 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
e97b775d
LF		 157#define IS_HARDWARE_TYPE_8192S(rtlhal) \
158(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
159#define IS_HARDWARE_TYPE_8192C(rtlhal) \
160(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
161#define IS_HARDWARE_TYPE_8192D(rtlhal) \
162(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
163#define IS_HARDWARE_TYPE_8723(rtlhal) \
164(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
3dad618b
C		 165#define IS_HARDWARE_TYPE_8723U(rtlhal) \
166 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
62e63975 167
da3ba88a
LF		 168#define RX_HAL_IS_CCK_RATE(_pdesc)\
169 (_pdesc->rxmcs == DESC92_RATE1M || \
170 _pdesc->rxmcs == DESC92_RATE2M || \
171 _pdesc->rxmcs == DESC92_RATE5_5M || \
172 _pdesc->rxmcs == DESC92_RATE11M)
173
0c817338
LF		 174enum scan_operation_backup_opt {
175 SCAN_OPT_BACKUP = 0,
176 SCAN_OPT_RESTORE,
177 SCAN_OPT_MAX
178};
179
180/*RF state.*/
181enum rf_pwrstate {
182 ERFON,
183 ERFSLEEP,
184 ERFOFF
185};
186
187struct bb_reg_def {
188 u32 rfintfs;
189 u32 rfintfi;
190 u32 rfintfo;
191 u32 rfintfe;
192 u32 rf3wire_offset;
193 u32 rflssi_select;
194 u32 rftxgain_stage;
195 u32 rfhssi_para1;
196 u32 rfhssi_para2;
197 u32 rfswitch_control;
198 u32 rfagc_control1;
199 u32 rfagc_control2;
200 u32 rfrxiq_imbalance;
201 u32 rfrx_afe;
202 u32 rftxiq_imbalance;
203 u32 rftx_afe;
204 u32 rflssi_readback;
205 u32 rflssi_readbackpi;
206};
207
208enum io_type {
209 IO_CMD_PAUSE_DM_BY_SCAN = 0,
210 IO_CMD_RESUME_DM_BY_SCAN = 1,
211};
212
213enum hw_variables {
214 HW_VAR_ETHER_ADDR,
215 HW_VAR_MULTICAST_REG,
216 HW_VAR_BASIC_RATE,
217 HW_VAR_BSSID,
218 HW_VAR_MEDIA_STATUS,
219 HW_VAR_SECURITY_CONF,
220 HW_VAR_BEACON_INTERVAL,
221 HW_VAR_ATIM_WINDOW,
222 HW_VAR_LISTEN_INTERVAL,
223 HW_VAR_CS_COUNTER,
224 HW_VAR_DEFAULTKEY0,
225 HW_VAR_DEFAULTKEY1,
226 HW_VAR_DEFAULTKEY2,
227 HW_VAR_DEFAULTKEY3,
228 HW_VAR_SIFS,
229 HW_VAR_DIFS,
230 HW_VAR_EIFS,
231 HW_VAR_SLOT_TIME,
232 HW_VAR_ACK_PREAMBLE,
233 HW_VAR_CW_CONFIG,
234 HW_VAR_CW_VALUES,
235 HW_VAR_RATE_FALLBACK_CONTROL,
236 HW_VAR_CONTENTION_WINDOW,
237 HW_VAR_RETRY_COUNT,
238 HW_VAR_TR_SWITCH,
239 HW_VAR_COMMAND,
240 HW_VAR_WPA_CONFIG,
241 HW_VAR_AMPDU_MIN_SPACE,
242 HW_VAR_SHORTGI_DENSITY,
243 HW_VAR_AMPDU_FACTOR,
244 HW_VAR_MCS_RATE_AVAILABLE,
245 HW_VAR_AC_PARAM,
246 HW_VAR_ACM_CTRL,
247 HW_VAR_DIS_Req_Qsize,
248 HW_VAR_CCX_CHNL_LOAD,
249 HW_VAR_CCX_NOISE_HISTOGRAM,
250 HW_VAR_CCX_CLM_NHM,
251 HW_VAR_TxOPLimit,
252 HW_VAR_TURBO_MODE,
253 HW_VAR_RF_STATE,
254 HW_VAR_RF_OFF_BY_HW,
255 HW_VAR_BUS_SPEED,
256 HW_VAR_SET_DEV_POWER,
257
258 HW_VAR_RCR,
259 HW_VAR_RATR_0,
260 HW_VAR_RRSR,
261 HW_VAR_CPU_RST,
262 HW_VAR_CECHK_BSSID,
263 HW_VAR_LBK_MODE,
264 HW_VAR_AES_11N_FIX,
265 HW_VAR_USB_RX_AGGR,
266 HW_VAR_USER_CONTROL_TURBO_MODE,
267 HW_VAR_RETRY_LIMIT,
268 HW_VAR_INIT_TX_RATE,
269 HW_VAR_TX_RATE_REG,
270 HW_VAR_EFUSE_USAGE,
271 HW_VAR_EFUSE_BYTES,
272 HW_VAR_AUTOLOAD_STATUS,
273 HW_VAR_RF_2R_DISABLE,
274 HW_VAR_SET_RPWM,
275 HW_VAR_H2C_FW_PWRMODE,
276 HW_VAR_H2C_FW_JOINBSSRPT,
277 HW_VAR_FW_PSMODE_STATUS,
278 HW_VAR_1X1_RECV_COMBINE,
279 HW_VAR_STOP_SEND_BEACON,
280 HW_VAR_TSF_TIMER,
281 HW_VAR_IO_CMD,
282
283 HW_VAR_RF_RECOVERY,
284 HW_VAR_H2C_FW_UPDATE_GTK,
285 HW_VAR_WF_MASK,
286 HW_VAR_WF_CRC,
287 HW_VAR_WF_IS_MAC_ADDR,
288 HW_VAR_H2C_FW_OFFLOAD,
289 HW_VAR_RESET_WFCRC,
290
291 HW_VAR_HANDLE_FW_C2H,
292 HW_VAR_DL_FW_RSVD_PAGE,
293 HW_VAR_AID,
294 HW_VAR_HW_SEQ_ENABLE,
295 HW_VAR_CORRECT_TSF,
296 HW_VAR_BCN_VALID,
297 HW_VAR_FWLPS_RF_ON,
298 HW_VAR_DUAL_TSF_RST,
299 HW_VAR_SWITCH_EPHY_WoWLAN,
300 HW_VAR_INT_MIGRATION,
301 HW_VAR_INT_AC,
302 HW_VAR_RF_TIMING,
303
304 HW_VAR_MRC,
305
306 HW_VAR_MGT_FILTER,
307 HW_VAR_CTRL_FILTER,
308 HW_VAR_DATA_FILTER,
309};
310
311enum _RT_MEDIA_STATUS {
312 RT_MEDIA_DISCONNECT = 0,
313 RT_MEDIA_CONNECT = 1
314};
315
316enum rt_oem_id {
317 RT_CID_DEFAULT = 0,
318 RT_CID_8187_ALPHA0 = 1,
319 RT_CID_8187_SERCOMM_PS = 2,
320 RT_CID_8187_HW_LED = 3,
321 RT_CID_8187_NETGEAR = 4,
322 RT_CID_WHQL = 5,
323 RT_CID_819x_CAMEO = 6,
324 RT_CID_819x_RUNTOP = 7,
325 RT_CID_819x_Senao = 8,
326 RT_CID_TOSHIBA = 9,
327 RT_CID_819x_Netcore = 10,
328 RT_CID_Nettronix = 11,
329 RT_CID_DLINK = 12,
330 RT_CID_PRONET = 13,
331 RT_CID_COREGA = 14,
332 RT_CID_819x_ALPHA = 15,
333 RT_CID_819x_Sitecom = 16,
334 RT_CID_CCX = 17,
335 RT_CID_819x_Lenovo = 18,
336 RT_CID_819x_QMI = 19,
337 RT_CID_819x_Edimax_Belkin = 20,
338 RT_CID_819x_Sercomm_Belkin = 21,
339 RT_CID_819x_CAMEO1 = 22,
340 RT_CID_819x_MSI = 23,
341 RT_CID_819x_Acer = 24,
342 RT_CID_819x_HP = 27,
343 RT_CID_819x_CLEVO = 28,
344 RT_CID_819x_Arcadyan_Belkin = 29,
345 RT_CID_819x_SAMSUNG = 30,
346 RT_CID_819x_WNC_COREGA = 31,
347 RT_CID_819x_Foxcoon = 32,
348 RT_CID_819x_DELL = 33,
349};
350
351enum hw_descs {
352 HW_DESC_OWN,
353 HW_DESC_RXOWN,
354 HW_DESC_TX_NEXTDESC_ADDR,
355 HW_DESC_TXBUFF_ADDR,
356 HW_DESC_RXBUFF_ADDR,
357 HW_DESC_RXPKT_LEN,
358 HW_DESC_RXERO,
359};
360
361enum prime_sc {
362 PRIME_CHNL_OFFSET_DONT_CARE = 0,
363 PRIME_CHNL_OFFSET_LOWER = 1,
364 PRIME_CHNL_OFFSET_UPPER = 2,
365};
366
367enum rf_type {
368 RF_1T1R = 0,
369 RF_1T2R = 1,
370 RF_2T2R = 2,
e97b775d 371 RF_2T2R_GREEN = 3,
0c817338
LF		 372};
373
374enum ht_channel_width {
375 HT_CHANNEL_WIDTH_20 = 0,
376 HT_CHANNEL_WIDTH_20_40 = 1,
377};
378
379/* Ref: 802.11i sepc D10.0 7.3.2.25.1
380Cipher Suites Encryption Algorithms */
381enum rt_enc_alg {
382 NO_ENCRYPTION = 0,
383 WEP40_ENCRYPTION = 1,
384 TKIP_ENCRYPTION = 2,
385 RSERVED_ENCRYPTION = 3,
386 AESCCMP_ENCRYPTION = 4,
387 WEP104_ENCRYPTION = 5,
388};
389
390enum rtl_hal_state {
391 _HAL_STATE_STOP = 0,
392 _HAL_STATE_START = 1,
393};
394
7ad0ce35
LF		 395enum rtl_desc92_rate {
396 DESC92_RATE1M = 0x00,
397 DESC92_RATE2M = 0x01,
398 DESC92_RATE5_5M = 0x02,
399 DESC92_RATE11M = 0x03,
400
401 DESC92_RATE6M = 0x04,
402 DESC92_RATE9M = 0x05,
403 DESC92_RATE12M = 0x06,
404 DESC92_RATE18M = 0x07,
405 DESC92_RATE24M = 0x08,
406 DESC92_RATE36M = 0x09,
407 DESC92_RATE48M = 0x0a,
408 DESC92_RATE54M = 0x0b,
409
410 DESC92_RATEMCS0 = 0x0c,
411 DESC92_RATEMCS1 = 0x0d,
412 DESC92_RATEMCS2 = 0x0e,
413 DESC92_RATEMCS3 = 0x0f,
414 DESC92_RATEMCS4 = 0x10,
415 DESC92_RATEMCS5 = 0x11,
416 DESC92_RATEMCS6 = 0x12,
417 DESC92_RATEMCS7 = 0x13,
418 DESC92_RATEMCS8 = 0x14,
419 DESC92_RATEMCS9 = 0x15,
420 DESC92_RATEMCS10 = 0x16,
421 DESC92_RATEMCS11 = 0x17,
422 DESC92_RATEMCS12 = 0x18,
423 DESC92_RATEMCS13 = 0x19,
424 DESC92_RATEMCS14 = 0x1a,
425 DESC92_RATEMCS15 = 0x1b,
426 DESC92_RATEMCS15_SG = 0x1c,
427 DESC92_RATEMCS32 = 0x20,
428};
429
0c817338
LF		 430enum rtl_var_map {
431 /*reg map */
432 SYS_ISO_CTRL = 0,
433 SYS_FUNC_EN,
434 SYS_CLK,
435 MAC_RCR_AM,
436 MAC_RCR_AB,
437 MAC_RCR_ACRC32,
438 MAC_RCR_ACF,
439 MAC_RCR_AAP,
440
441 /*efuse map */
442 EFUSE_TEST,
443 EFUSE_CTRL,
444 EFUSE_CLK,
445 EFUSE_CLK_CTRL,
446 EFUSE_PWC_EV12V,
447 EFUSE_FEN_ELDR,
448 EFUSE_LOADER_CLK_EN,
449 EFUSE_ANA8M,
450 EFUSE_HWSET_MAX_SIZE,
18d30067
G		 451 EFUSE_MAX_SECTION_MAP,
452 EFUSE_REAL_CONTENT_SIZE,
5c079d88 453 EFUSE_OOB_PROTECT_BYTES_LEN,
0c817338
LF		 454
455 /*CAM map */
456 RWCAM,
457 WCAMI,
458 RCAMO,
459 CAMDBG,
460 SECR,
461 SEC_CAM_NONE,
462 SEC_CAM_WEP40,
463 SEC_CAM_TKIP,
464 SEC_CAM_AES,
465 SEC_CAM_WEP104,
466
467 /*IMR map */
468 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
469 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
470 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
471 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
472 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
473 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
474 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
475 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
476 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
477 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
478 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
479 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
480 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
481 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
482 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
483 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
484 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
485 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
486 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
487 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
488 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
489 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
490 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
491 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
e97b775d 492 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
0c817338
LF		 493 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
494 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
495 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
496 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
497 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
498 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
499 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
500 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
e97b775d
LF		 501 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
502 * RTL_IMR_TBDER) */
0c817338
LF		 503
504 /*CCK Rates, TxHT = 0 */
505 RTL_RC_CCK_RATE1M,
506 RTL_RC_CCK_RATE2M,
507 RTL_RC_CCK_RATE5_5M,
508 RTL_RC_CCK_RATE11M,
509
510 /*OFDM Rates, TxHT = 0 */
511 RTL_RC_OFDM_RATE6M,
512 RTL_RC_OFDM_RATE9M,
513 RTL_RC_OFDM_RATE12M,
514 RTL_RC_OFDM_RATE18M,
515 RTL_RC_OFDM_RATE24M,
516 RTL_RC_OFDM_RATE36M,
517 RTL_RC_OFDM_RATE48M,
518 RTL_RC_OFDM_RATE54M,
519
520 RTL_RC_HT_RATEMCS7,
521 RTL_RC_HT_RATEMCS15,
522
523 /*keep it last */
524 RTL_VAR_MAP_MAX,
525};
526
527/*Firmware PS mode for control LPS.*/
528enum _fw_ps_mode {
529 FW_PS_ACTIVE_MODE = 0,
530 FW_PS_MIN_MODE = 1,
531 FW_PS_MAX_MODE = 2,
532 FW_PS_DTIM_MODE = 3,
533 FW_PS_VOIP_MODE = 4,
534 FW_PS_UAPSD_WMM_MODE = 5,
535 FW_PS_UAPSD_MODE = 6,
536 FW_PS_IBSS_MODE = 7,
537 FW_PS_WWLAN_MODE = 8,
538 FW_PS_PM_Radio_Off = 9,
539 FW_PS_PM_Card_Disable = 10,
540};
541
542enum rt_psmode {
543 EACTIVE, /*Active/Continuous access. */
544 EMAXPS, /*Max power save mode. */
545 EFASTPS, /*Fast power save mode. */
546 EAUTOPS, /*Auto power save mode. */
547};
548
549/*LED related.*/
550enum led_ctl_mode {
551 LED_CTL_POWER_ON = 1,
552 LED_CTL_LINK = 2,
553 LED_CTL_NO_LINK = 3,
554 LED_CTL_TX = 4,
555 LED_CTL_RX = 5,
556 LED_CTL_SITE_SURVEY = 6,
557 LED_CTL_POWER_OFF = 7,
558 LED_CTL_START_TO_LINK = 8,
559 LED_CTL_START_WPS = 9,
560 LED_CTL_STOP_WPS = 10,
561};
562
563enum rtl_led_pin {
564 LED_PIN_GPIO0,
565 LED_PIN_LED0,
566 LED_PIN_LED1,
567 LED_PIN_LED2
568};
569
570/*QoS related.*/
571/*acm implementation method.*/
572enum acm_method {
573 eAcmWay0_SwAndHw = 0,
574 eAcmWay1_HW = 1,
575 eAcmWay2_SW = 2,
576};
577
e97b775d
LF		 578enum macphy_mode {
579 SINGLEMAC_SINGLEPHY = 0,
580 DUALMAC_DUALPHY,
581 DUALMAC_SINGLEPHY,
582};
583
584enum band_type {
585 BAND_ON_2_4G = 0,
586 BAND_ON_5G,
587 BAND_ON_BOTH,
588 BANDMAX
589};
590
0c817338
LF		 591/*aci/aifsn Field.
592Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
593union aci_aifsn {
594 u8 char_data;
595
596 struct {
597 u8 aifsn:4;
598 u8 acm:1;
599 u8 aci:2;
600 u8 reserved:1;
601 } f; /* Field */
602};
603
604/*mlme related.*/
605enum wireless_mode {
606 WIRELESS_MODE_UNKNOWN = 0x00,
607 WIRELESS_MODE_A = 0x01,
608 WIRELESS_MODE_B = 0x02,
609 WIRELESS_MODE_G = 0x04,
610 WIRELESS_MODE_AUTO = 0x08,
611 WIRELESS_MODE_N_24G = 0x10,
612 WIRELESS_MODE_N_5G = 0x20
613};
614
18d30067
G		 615#define IS_WIRELESS_MODE_A(wirelessmode) \
616 (wirelessmode == WIRELESS_MODE_A)
617#define IS_WIRELESS_MODE_B(wirelessmode) \
618 (wirelessmode == WIRELESS_MODE_B)
619#define IS_WIRELESS_MODE_G(wirelessmode) \
620 (wirelessmode == WIRELESS_MODE_G)
621#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
622 (wirelessmode == WIRELESS_MODE_N_24G)
623#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
624 (wirelessmode == WIRELESS_MODE_N_5G)
625
0c817338
LF		 626enum ratr_table_mode {
627 RATR_INX_WIRELESS_NGB = 0,
628 RATR_INX_WIRELESS_NG = 1,
629 RATR_INX_WIRELESS_NB = 2,
630 RATR_INX_WIRELESS_N = 3,
631 RATR_INX_WIRELESS_GB = 4,
632 RATR_INX_WIRELESS_G = 5,
633 RATR_INX_WIRELESS_B = 6,
634 RATR_INX_WIRELESS_MC = 7,
635 RATR_INX_WIRELESS_A = 8,
636};
637
638enum rtl_link_state {
639 MAC80211_NOLINK = 0,
640 MAC80211_LINKING = 1,
641 MAC80211_LINKED = 2,
642 MAC80211_LINKED_SCANNING = 3,
643};
644
645enum act_category {
646 ACT_CAT_QOS = 1,
647 ACT_CAT_DLS = 2,
648 ACT_CAT_BA = 3,
649 ACT_CAT_HT = 7,
650 ACT_CAT_WMM = 17,
651};
652
653enum ba_action {
654 ACT_ADDBAREQ = 0,
655 ACT_ADDBARSP = 1,
656 ACT_DELBA = 2,
657};
658
659struct octet_string {
660 u8 *octet;
661 u16 length;
662};
663
664struct rtl_hdr_3addr {
665 __le16 frame_ctl;
666 __le16 duration_id;
667 u8 addr1[ETH_ALEN];
668 u8 addr2[ETH_ALEN];
669 u8 addr3[ETH_ALEN];
670 __le16 seq_ctl;
671 u8 payload[0];
e137478b 672} __packed;
0c817338
LF		 673
674struct rtl_info_element {
675 u8 id;
676 u8 len;
677 u8 data[0];
e137478b 678} __packed;
0c817338
LF		 679
680struct rtl_probe_rsp {
681 struct rtl_hdr_3addr header;
682 u32 time_stamp[2];
683 __le16 beacon_interval;
684 __le16 capability;
685 /*SSID, supported rates, FH params, DS params,
686 CF params, IBSS params, TIM (if beacon), RSN */
687 struct rtl_info_element info_element[0];
e137478b 688} __packed;
0c817338
LF		 689
690/*LED related.*/
691/*ledpin Identify how to implement this SW led.*/
692struct rtl_led {
693 void *hw;
694 enum rtl_led_pin ledpin;
7ea47240 695 bool ledon;
0c817338
LF		 696};
697
698struct rtl_led_ctl {
7ea47240 699 bool led_opendrain;
0c817338
LF		 700 struct rtl_led sw_led0;
701 struct rtl_led sw_led1;
702};
703
704struct rtl_qos_parameters {
705 __le16 cw_min;
706 __le16 cw_max;
707 u8 aifs;
708 u8 flag;
709 __le16 tx_op;
e137478b 710} __packed;
0c817338
LF		 711
712struct rt_smooth_data {
713 u32 elements[100]; /*array to store values */
714 u32 index; /*index to current array to store */
715 u32 total_num; /*num of valid elements */
716 u32 total_val; /*sum of valid elements */
717};
718
719struct false_alarm_statistics {
720 u32 cnt_parity_fail;
721 u32 cnt_rate_illegal;
722 u32 cnt_crc8_fail;
723 u32 cnt_mcs_fail;
e97b775d
LF		 724 u32 cnt_fast_fsync_fail;
725 u32 cnt_sb_search_fail;
0c817338
LF		 726 u32 cnt_ofdm_fail;
727 u32 cnt_cck_fail;
728 u32 cnt_all;
729};
730
731struct init_gain {
732 u8 xaagccore1;
733 u8 xbagccore1;
734 u8 xcagccore1;
735 u8 xdagccore1;
736 u8 cca;
737
738};
739
740struct wireless_stats {
741 unsigned long txbytesunicast;
742 unsigned long txbytesmulticast;
743 unsigned long txbytesbroadcast;
744 unsigned long rxbytesunicast;
745
746 long rx_snr_db[4];
747 /*Correct smoothed ss in Dbm, only used
748 in driver to report real power now. */
749 long recv_signal_power;
750 long signal_quality;
751 long last_sigstrength_inpercent;
752
753 u32 rssi_calculate_cnt;
754
755 /*Transformed, in dbm. Beautified signal
756 strength for UI, not correct. */
757 long signal_strength;
758
759 u8 rx_rssi_percentage[4];
760 u8 rx_evm_percentage[2];
761
762 struct rt_smooth_data ui_rssi;
763 struct rt_smooth_data ui_link_quality;
764};
765
766struct rate_adaptive {
767 u8 rate_adaptive_disabled;
768 u8 ratr_state;
769 u16 reserve;
770
771 u32 high_rssi_thresh_for_ra;
772 u32 high2low_rssi_thresh_for_ra;
773 u8 low2high_rssi_thresh_for_ra40m;
774 u32 low_rssi_thresh_for_ra40M;
775 u8 low2high_rssi_thresh_for_ra20m;
776 u32 low_rssi_thresh_for_ra20M;
777 u32 upper_rssi_threshold_ratr;
778 u32 middleupper_rssi_threshold_ratr;
779 u32 middle_rssi_threshold_ratr;
780 u32 middlelow_rssi_threshold_ratr;
781 u32 low_rssi_threshold_ratr;
782 u32 ultralow_rssi_threshold_ratr;
783 u32 low_rssi_threshold_ratr_40m;
784 u32 low_rssi_threshold_ratr_20m;
785 u8 ping_rssi_enable;
786 u32 ping_rssi_ratr;
787 u32 ping_rssi_thresh_for_ra;
788 u32 last_ratr;
789 u8 pre_ratr_state;
790};
791
792struct regd_pair_mapping {
793 u16 reg_dmnenum;
794 u16 reg_5ghz_ctl;
795 u16 reg_2ghz_ctl;
796};
797
798struct rtl_regulatory {
799 char alpha2[2];
800 u16 country_code;
801 u16 max_power_level;
802 u32 tp_scale;
803 u16 current_rd;
804 u16 current_rd_ext;
805 int16_t power_limit;
806 struct regd_pair_mapping *regpair;
807};
808
809struct rtl_rfkill {
810 bool rfkill_state; /*0 is off, 1 is on */
811};
812
e97b775d
LF		 813#define IQK_MATRIX_REG_NUM 8
814#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
815struct iqk_matrix_regs {
32473284 816 bool iqk_done;
e97b775d
LF		 817 long value[1][IQK_MATRIX_REG_NUM];
818};
819
18d30067
G		 820struct phy_parameters {
821 u16 length;
822 u32 *pdata;
823};
824
825enum hw_param_tab_index {
826 PHY_REG_2T,
827 PHY_REG_1T,
828 PHY_REG_PG,
829 RADIOA_2T,
830 RADIOB_2T,
831 RADIOA_1T,
832 RADIOB_1T,
833 MAC_REG,
834 AGCTAB_2T,
835 AGCTAB_1T,
836 MAX_TAB
837};
838
0c817338
LF		 839struct rtl_phy {
840 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
841 struct init_gain initgain_backup;
842 enum io_type current_io_type;
843
844 u8 rf_mode;
845 u8 rf_type;
846 u8 current_chan_bw;
847 u8 set_bwmode_inprogress;
848 u8 sw_chnl_inprogress;
849 u8 sw_chnl_stage;
850 u8 sw_chnl_step;
851 u8 current_channel;
852 u8 h2c_box_num;
853 u8 set_io_inprogress;
e97b775d 854 u8 lck_inprogress;
0c817338 855
e97b775d 856 /* record for power tracking */
0c817338
LF		 857 s32 reg_e94;
858 s32 reg_e9c;
859 s32 reg_ea4;
860 s32 reg_eac;
861 s32 reg_eb4;
862 s32 reg_ebc;
863 s32 reg_ec4;
864 s32 reg_ecc;
865 u8 rfpienable;
866 u8 reserve_0;
867 u16 reserve_1;
868 u32 reg_c04, reg_c08, reg_874;
869 u32 adda_backup[16];
870 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
871 u32 iqk_bb_backup[10];
872
e97b775d
LF		 873 /* Dual mac */
874 bool need_iqk;
875 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
876
7ea47240 877 bool rfpi_enable;
0c817338
LF		 878
879 u8 pwrgroup_cnt;
7ea47240 880 u8 cck_high_power;
e97b775d
LF		 881 /* MAX_PG_GROUP groups of pwr diff by rates */
882 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
0c817338
LF		 883 u8 default_initialgain[4];
884
e97b775d 885 /* the current Tx power level */
0c817338
LF		 886 u8 cur_cck_txpwridx;
887 u8 cur_ofdm24g_txpwridx;
888
889 u32 rfreg_chnlval[2];
7ea47240 890 bool apk_done;
e97b775d 891 u32 reg_rf3c[2]; /* pathA / pathB */
0c817338 892
3dad618b 893 /* bfsync */
0c817338
LF		 894 u8 framesync;
895 u32 framesync_c34;
896
897 u8 num_total_rfpath;
18d30067 898 struct phy_parameters hwparam_tables[MAX_TAB];
e97b775d 899 u16 rf_pathmap;
0c817338
LF		 900};
901
902#define MAX_TID_COUNT 9
3dad618b
C		 903#define RTL_AGG_STOP 0
904#define RTL_AGG_PROGRESS 1
905#define RTL_AGG_START 2
906#define RTL_AGG_OPERATIONAL 3
0c817338
LF		 907#define RTL_AGG_OFF 0
908#define RTL_AGG_ON 1
909#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
910#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
911
912struct rtl_ht_agg {
913 u16 txq_id;
914 u16 wait_for_ba;
915 u16 start_idx;
916 u64 bitmap;
917 u32 rate_n_flags;
918 u8 agg_state;
919};
920
921struct rtl_tid_data {
922 u16 seq_number;
923 struct rtl_ht_agg agg;
924};
925
3dad618b
C		 926struct rtl_sta_info {
927 u8 ratr_index;
928 u8 wireless_mode;
929 u8 mimo_ps;
930 struct rtl_tid_data tids[MAX_TID_COUNT];
931} __packed;
932
0c817338
LF		 933struct rtl_priv;
934struct rtl_io {
935 struct device *dev;
62e63975 936 struct mutex bb_mutex;
0c817338
LF		 937
938 /*PCI MEM map */
939 unsigned long pci_mem_end; /*shared mem end */
940 unsigned long pci_mem_start; /*shared mem start */
941
942 /*PCI IO map */
943 unsigned long pci_base_addr; /*device I/O address */
944
945 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
ffca2871
LF		 946 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, __le16 val);
947 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, __le32 val);
0c817338 948
e97b775d
LF		 949 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
950 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
951 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
3dad618b 952
0c817338
LF		 953};
954
955struct rtl_mac {
956 u8 mac_addr[ETH_ALEN];
957 u8 mac80211_registered;
958 u8 beacon_enabled;
959
960 u32 tx_ss_num;
961 u32 rx_ss_num;
962
963 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
964 struct ieee80211_hw *hw;
965 struct ieee80211_vif *vif;
966 enum nl80211_iftype opmode;
967
968 /*Probe Beacon management */
969 struct rtl_tid_data tids[MAX_TID_COUNT];
970 enum rtl_link_state link_state;
971
972 int n_channels;
973 int n_bitrates;
974
9c050440 975 bool offchan_delay;
3dad618b 976
0c817338
LF		 977 /*filters */
978 u32 rx_conf;
979 u16 rx_mgt_filter;
980 u16 rx_ctrl_filter;
981 u16 rx_data_filter;
982
983 bool act_scanning;
984 u8 cnt_after_linked;
985
e97b775d
LF		 986 /* early mode */
987 /* skb wait queue */
988 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
989 u8 earlymode_threshold;
990
991 /*RDG*/
992 bool rdg_en;
0c817338 993
e97b775d
LF		 994 /*AP*/
995 u8 bssid[6];
996 u32 vendor;
997 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
998 u32 basic_rates; /* b/g rates */
0c817338
LF		 999 u8 ht_enable;
1000 u8 sgi_40;
1001 u8 sgi_20;
1002 u8 bw_40;
e97b775d 1003 u8 mode; /* wireless mode */
0c817338
LF		 1004 u8 slot_time;
1005 u8 short_preamble;
1006 u8 use_cts_protect;
1007 u8 cur_40_prime_sc;
1008 u8 cur_40_prime_sc_bk;
1009 u64 tsf;
1010 u8 retry_short;
1011 u8 retry_long;
1012 u16 assoc_id;
1013
e97b775d
LF		 1014 /*IBSS*/
1015 int beacon_interval;
0c817338 1016
e97b775d
LF		 1017 /*AMPDU*/
1018 u8 min_space_cfg; /*For Min spacing configurations */
0c817338
LF		 1019 u8 max_mss_density;
1020 u8 current_ampdu_factor;
1021 u8 current_ampdu_density;
1022
1023 /*QOS & EDCA */
1024 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1025 struct rtl_qos_parameters ac[AC_MAX];
1026};
1027
1028struct rtl_hal {
1029 struct ieee80211_hw *hw;
1030
1031 enum intf_type interface;
1032 u16 hw_type; /*92c or 92d or 92s and so on */
e97b775d 1033 u8 ic_class;
0c817338 1034 u8 oem_id;
18d30067 1035 u32 version; /*version of chip */
0c817338
LF		 1036 u8 state; /*stop 0, start 1 */
1037
1038 /*firmware */
e97b775d 1039 u32 fwsize;
0c817338 1040 u8 *pfirmware;
18d30067
G		 1041 u16 fw_version;
1042 u16 fw_subversion;
7ea47240 1043 bool h2c_setinprogress;
0c817338 1044 u8 last_hmeboxnum;
7ea47240 1045 bool fw_ready;
0c817338
LF		 1046 /*Reserve page start offset except beacon in TxQ. */
1047 u8 fw_rsvdpage_startoffset;
e97b775d
LF		 1048 u8 h2c_txcmd_seq;
1049
1050 /* FW Cmd IO related */
1051 u16 fwcmd_iomap;
1052 u32 fwcmd_ioparam;
1053 bool set_fwcmd_inprogress;
1054 u8 current_fwcmd_io;
1055
1056 /**/
1057 bool driver_going2unload;
1058
1059 /*AMPDU init min space*/
1060 u8 minspace_cfg; /*For Min spacing configurations */
1061
1062 /* Dual mac */
1063 enum macphy_mode macphymode;
1064 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1065 enum band_type current_bandtypebackup;
1066 enum band_type bandset;
1067 /* dual MAC 0--Mac0 1--Mac1 */
1068 u32 interfaceindex;
1069 /* just for DualMac S3S4 */
1070 u8 macphyctl_reg;
1071 bool earlymode_enable;
1072 /* Dual mac*/
1073 bool during_mac0init_radiob;
1074 bool during_mac1init_radioa;
1075 bool reloadtxpowerindex;
1076 /* True if IMR or IQK have done
1077 for 2.4G in scan progress */
1078 bool load_imrandiqk_setting_for2g;
1079
1080 bool disable_amsdu_8k;
0c817338
LF		 1081};
1082
1083struct rtl_security {
1084 /*default 0 */
1085 bool use_sw_sec;
1086
1087 bool being_setkey;
1088 bool use_defaultkey;
1089 /*Encryption Algorithm for Unicast Packet */
1090 enum rt_enc_alg pairwise_enc_algorithm;
1091 /*Encryption Algorithm for Brocast/Multicast */
1092 enum rt_enc_alg group_enc_algorithm;
3dad618b
C		 1093 /*Cam Entry Bitmap */
1094 u32 hwsec_cam_bitmap;
1095 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
0c817338
LF		 1096 /*local Key buffer, indx 0 is for
1097 pairwise key 1-4 is for agoup key. */
1098 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1099 u8 key_len[KEY_BUF_SIZE];
1100
1101 /*The pointer of Pairwise Key,
1102 it always points to KeyBuf[4] */
1103 u8 *pairwise_key;
1104};
1105
1106struct rtl_dm {
e97b775d 1107 /*PHY status for Dynamic Management */
0c817338
LF		 1108 long entry_min_undecoratedsmoothed_pwdb;
1109 long undecorated_smoothed_pwdb; /*out dm */
1110 long entry_max_undecoratedsmoothed_pwdb;
7ea47240
LF		 1111 bool dm_initialgain_enable;
1112 bool dynamic_txpower_enable;
1113 bool current_turbo_edca;
1114 bool is_any_nonbepkts; /*out dm */
1115 bool is_cur_rdlstate;
3dad618b 1116 bool txpower_trackinginit;
7ea47240
LF		 1117 bool disable_framebursting;
1118 bool cck_inch14;
1119 bool txpower_tracking;
1120 bool useramask;
1121 bool rfpath_rxenable[4];
e97b775d
LF		 1122 bool inform_fw_driverctrldm;
1123 bool current_mrc_switch;
1124 u8 txpowercount;
0c817338 1125
e97b775d 1126 u8 thermalvalue_rxgain;
0c817338
LF		 1127 u8 thermalvalue_iqk;
1128 u8 thermalvalue_lck;
1129 u8 thermalvalue;
1130 u8 last_dtp_lvl;
e97b775d
LF		 1131 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1132 u8 thermalvalue_avg_index;
1133 bool done_txpower;
0c817338 1134 u8 dynamic_txhighpower_lvl; /*Tx high power level */
e97b775d 1135 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
0c817338
LF		 1136 u8 dm_type;
1137 u8 txpower_track_control;
e97b775d
LF		 1138 bool interrupt_migration;
1139 bool disable_tx_int;
0c817338
LF		 1140 char ofdm_index[2];
1141 char cck_index;
1142};
1143
e97b775d 1144#define EFUSE_MAX_LOGICAL_SIZE 256
0c817338
LF		 1145
1146struct rtl_efuse {
e97b775d 1147 bool autoLoad_ok;
0c817338
LF		 1148 bool bootfromefuse;
1149 u16 max_physical_size;
0c817338
LF		 1150
1151 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1152 u16 efuse_usedbytes;
1153 u8 efuse_usedpercentage;
e97b775d
LF		 1154#ifdef EFUSE_REPG_WORKAROUND
1155 bool efuse_re_pg_sec1flag;
1156 u8 efuse_re_pg_data[8];
1157#endif
0c817338
LF		 1158
1159 u8 autoload_failflag;
e97b775d 1160 u8 autoload_status;
0c817338
LF		 1161
1162 short epromtype;
1163 u16 eeprom_vid;
1164 u16 eeprom_did;
1165 u16 eeprom_svid;
1166 u16 eeprom_smid;
1167 u8 eeprom_oemid;
1168 u16 eeprom_channelplan;
1169 u8 eeprom_version;
18d30067
G		 1170 u8 board_type;
1171 u8 external_pa;
0c817338
LF		 1172
1173 u8 dev_addr[6];
1174
7ea47240 1175 bool txpwr_fromeprom;
e97b775d 1176 u8 eeprom_crystalcap;
0c817338 1177 u8 eeprom_tssi[2];
e97b775d
LF		 1178 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1179 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1180 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1181 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1182 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1183 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1184 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1185 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1186 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1187
1188 u8 internal_pa_5g[2]; /* pathA / pathB */
1189 u8 eeprom_c9;
1190 u8 eeprom_cc;
0c817338
LF		 1191
1192 /*For power group */
e97b775d
LF		 1193 u8 eeprom_pwrgroup[2][3];
1194 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1195 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1196
1197 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1198 /*For HT<->legacy pwr diff*/
1199 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1200 u8 txpwr_safetyflag; /* Band edge enable flag */
1201 u16 eeprom_txpowerdiff;
1202 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1203 u8 antenna_txpwdiff[3];
0c817338
LF		 1204
1205 u8 eeprom_regulatory;
1206 u8 eeprom_thermalmeter;
e97b775d
LF		 1207 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1208 u16 tssi_13dbm;
1209 u8 crystalcap; /* CrystalCap. */
1210 u8 delta_iqk;
1211 u8 delta_lck;
0c817338
LF		 1212
1213 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
7ea47240 1214 bool apk_thermalmeterignore;
e97b775d
LF		 1215
1216 bool b1x1_recvcombine;
1217 bool b1ss_support;
1218
1219 /*channel plan */
1220 u8 channel_plan;
0c817338
LF		 1221};
1222
1223struct rtl_ps_ctl {
e97b775d 1224 bool pwrdomain_protect;
7ea47240 1225 bool in_powersavemode;
0c817338 1226 bool rfchange_inprogress;
7ea47240
LF		 1227 bool swrf_processing;
1228 bool hwradiooff;
0c817338 1229
0c817338
LF		 1230 /*
1231 * just for PCIE ASPM
1232 * If it supports ASPM, Offset[560h] = 0x40,
1233 * otherwise Offset[560h] = 0x00.
1234 * */
7ea47240 1235 bool support_aspm;
3dad618b 1236
7ea47240 1237 bool support_backdoor;
0c817338
LF		 1238
1239 /*for LPS */
1240 enum rt_psmode dot11_psmode; /*Power save mode configured. */
e97b775d 1241 bool swctrl_lps;
7ea47240
LF		 1242 bool leisure_ps;
1243 bool fwctrl_lps;
0c817338
LF		 1244 u8 fwctrl_psmode;
1245 /*For Fw control LPS mode */
7ea47240 1246 u8 reg_fwctrl_lps;
0c817338 1247 /*Record Fw PS mode status. */
7ea47240 1248 bool fw_current_inpsmode;
0c817338
LF		 1249 u8 reg_max_lps_awakeintvl;
1250 bool report_linked;
1251
1252 /*for IPS */
7ea47240 1253 bool inactiveps;
0c817338
LF		 1254
1255 u32 rfoff_reason;
1256
1257 /*RF OFF Level */
1258 u32 cur_ps_level;
1259 u32 reg_rfps_level;
1260
1261 /*just for PCIE ASPM */
1262 u8 const_amdpci_aspm;
18d30067 1263 bool pwrdown_mode;
e97b775d 1264
0c817338
LF		 1265 enum rf_pwrstate inactive_pwrstate;
1266 enum rf_pwrstate rfpwr_state; /*cur power state */
e97b775d
LF		 1267
1268 /* for SW LPS*/
1269 bool sw_ps_enabled;
1270 bool state;
1271 bool state_inap;
1272 bool multi_buffered;
1273 u16 nullfunc_seq;
1274 unsigned int dtim_counter;
1275 unsigned int sleep_ms;
1276 unsigned long last_sleep_jiffies;
1277 unsigned long last_awake_jiffies;
1278 unsigned long last_delaylps_stamp_jiffies;
1279 unsigned long last_dtim;
1280 unsigned long last_beacon;
1281 unsigned long last_action;
1282 unsigned long last_slept;
0c817338
LF		 1283};
1284
1285struct rtl_stats {
1286 u32 mac_time[2];
1287 s8 rssi;
1288 u8 signal;
1289 u8 noise;
1290 u16 rate; /*in 100 kbps */
1291 u8 received_channel;
1292 u8 control;
1293 u8 mask;
1294 u8 freq;
1295 u16 len;
1296 u64 tsf;
1297 u32 beacon_time;
1298 u8 nic_type;
1299 u16 length;
1300 u8 signalquality; /*in 0-100 index. */
1301 /*
1302 * Real power in dBm for this packet,
1303 * no beautification and aggregation.
1304 * */
1305 s32 recvsignalpower;
1306 s8 rxpower; /*in dBm Translate from PWdB */
1307 u8 signalstrength; /*in 0-100 index. */
7ea47240
LF		 1308 u16 hwerror:1;
1309 u16 crc:1;
1310 u16 icv:1;
1311 u16 shortpreamble:1;
0c817338
LF		 1312 u16 antenna:1;
1313 u16 decrypted:1;
1314 u16 wakeup:1;
1315 u32 timestamp_low;
1316 u32 timestamp_high;
1317
1318 u8 rx_drvinfo_size;
1319 u8 rx_bufshift;
7ea47240 1320 bool isampdu;
e97b775d 1321 bool isfirst_ampdu;
0c817338
LF		 1322 bool rx_is40Mhzpacket;
1323 u32 rx_pwdb_all;
1324 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1325 s8 rx_mimo_signalquality[2];
7ea47240
LF		 1326 bool packet_matchbssid;
1327 bool is_cck;
5c079d88 1328 bool is_ht;
7ea47240
LF		 1329 bool packet_toself;
1330 bool packet_beacon; /*for rssi */
0c817338
LF		 1331 char cck_adc_pwdb[4]; /*for rx path selection */
1332};
1333
1334struct rt_link_detect {
1335 u32 num_tx_in4period[4];
1336 u32 num_rx_in4period[4];
1337
1338 u32 num_tx_inperiod;
1339 u32 num_rx_inperiod;
1340
7ea47240
LF		 1341 bool busytraffic;
1342 bool higher_busytraffic;
1343 bool higher_busyrxtraffic;
3dad618b
C		 1344
1345 u32 tidtx_in4period[MAX_TID_COUNT][4];
1346 u32 tidtx_inperiod[MAX_TID_COUNT];
1347 bool higher_busytxtraffic[MAX_TID_COUNT];
0c817338
LF		 1348};
1349
1350struct rtl_tcb_desc {
7ea47240
LF		 1351 u8 packet_bw:1;
1352 u8 multicast:1;
1353 u8 broadcast:1;
1354
1355 u8 rts_stbc:1;
1356 u8 rts_enable:1;
1357 u8 cts_enable:1;
1358 u8 rts_use_shortpreamble:1;
1359 u8 rts_use_shortgi:1;
0c817338 1360 u8 rts_sc:1;
7ea47240 1361 u8 rts_bw:1;
0c817338
LF		 1362 u8 rts_rate;
1363
1364 u8 use_shortgi:1;
1365 u8 use_shortpreamble:1;
1366 u8 use_driver_rate:1;
1367 u8 disable_ratefallback:1;
1368
1369 u8 ratr_index;
1370 u8 mac_id;
1371 u8 hw_rate;
e97b775d
LF		 1372
1373 u8 last_inipkt:1;
1374 u8 cmd_or_init:1;
1375 u8 queue_index;
1376
1377 /* early mode */
1378 u8 empkt_num;
1379 /* The max value by HW */
1380 u32 empkt_len[5];
0c817338
LF		 1381};
1382
1383struct rtl_hal_ops {
1384 int (*init_sw_vars) (struct ieee80211_hw *hw);
1385 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
62e63975 1386 void (*read_chip_version)(struct ieee80211_hw *hw);
0c817338
LF		 1387 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1388 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1389 u32 *p_inta, u32 *p_intb);
1390 int (*hw_init) (struct ieee80211_hw *hw);
1391 void (*hw_disable) (struct ieee80211_hw *hw);
e97b775d
LF		 1392 void (*hw_suspend) (struct ieee80211_hw *hw);
1393 void (*hw_resume) (struct ieee80211_hw *hw);
0c817338
LF		 1394 void (*enable_interrupt) (struct ieee80211_hw *hw);
1395 void (*disable_interrupt) (struct ieee80211_hw *hw);
1396 int (*set_network_type) (struct ieee80211_hw *hw,
1397 enum nl80211_iftype type);
18d30067
G		 1398 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1399 bool check_bssid);
0c817338
LF		 1400 void (*set_bw_mode) (struct ieee80211_hw *hw,
1401 enum nl80211_channel_type ch_type);
e97b775d 1402 u8(*switch_channel) (struct ieee80211_hw *hw);
0c817338
LF		 1403 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1404 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1405 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1406 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1407 u32 add_msr, u32 rm_msr);
1408 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1409 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
3dad618b
C		 1410 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1411 struct ieee80211_sta *sta, u8 rssi_level);
0c817338
LF		 1412 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1413 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1414 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1415 struct ieee80211_tx_info *info,
3dad618b
C		 1416 struct sk_buff *skb, u8 hw_queue,
1417 struct rtl_tcb_desc *ptcb_desc);
3dad618b 1418 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
18d30067 1419 u32 buffer_len, bool bIsPsPoll);
0c817338 1420 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
7ea47240 1421 bool firstseg, bool lastseg,
0c817338 1422 struct sk_buff *skb);
62e63975 1423 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
7ea47240 1424 bool (*query_rx_desc) (struct ieee80211_hw *hw,
0c817338
LF		 1425 struct rtl_stats *stats,
1426 struct ieee80211_rx_status *rx_status,
1427 u8 *pdesc, struct sk_buff *skb);
1428 void (*set_channel_access) (struct ieee80211_hw *hw);
7ea47240 1429 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
0c817338
LF		 1430 void (*dm_watchdog) (struct ieee80211_hw *hw);
1431 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
7ea47240 1432 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
0c817338
LF		 1433 enum rf_pwrstate rfpwr_state);
1434 void (*led_control) (struct ieee80211_hw *hw,
1435 enum led_ctl_mode ledaction);
1436 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
7ea47240 1437 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
3dad618b 1438 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
0c817338
LF		 1439 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1440 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
3dad618b 1441 u8 *macaddr, bool is_group, u8 enc_algo,
0c817338
LF		 1442 bool is_wepkey, bool clear_all);
1443 void (*init_sw_leds) (struct ieee80211_hw *hw);
1444 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
7ea47240 1445 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
0c817338
LF		 1446 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1447 u32 data);
7ea47240 1448 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
0c817338
LF		 1449 u32 regaddr, u32 bitmask);
1450 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1451 u32 regaddr, u32 bitmask, u32 data);
3dad618b 1452 void (*linked_set_reg) (struct ieee80211_hw *hw);
1472d3a8
LF		 1453 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1454 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1455 u8 *powerlevel);
1456 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1457 u8 *ppowerlevel, u8 channel);
1458 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1459 u8 configtype);
1460 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1461 u8 configtype);
1462 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1463 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1464 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
0c817338
LF		 1465};
1466
1467struct rtl_intf_ops {
1468 /*com */
e97b775d 1469 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
0c817338
LF		 1470 int (*adapter_start) (struct ieee80211_hw *hw);
1471 void (*adapter_stop) (struct ieee80211_hw *hw);
1472
3dad618b
C		 1473 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1474 struct rtl_tcb_desc *ptcb_desc);
3dad618b 1475 void (*flush)(struct ieee80211_hw *hw, bool drop);
0c817338 1476 int (*reset_trx_ring) (struct ieee80211_hw *hw);
62e63975 1477 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
0c817338
LF		 1478
1479 /*pci */
1480 void (*disable_aspm) (struct ieee80211_hw *hw);
1481 void (*enable_aspm) (struct ieee80211_hw *hw);
1482
1483 /*usb */
1484};
1485
1486struct rtl_mod_params {
1487 /* default: 0 = using hardware encryption */
1488 int sw_crypto;
3dad618b 1489
73a253ca
LF		 1490 /* default: 0 = DBG_EMERG (0)*/
1491 int debug;
1492
3dad618b
C		 1493 /* default: 1 = using no linked power save */
1494 bool inactiveps;
1495
1496 /* default: 1 = using linked sw power save */
1497 bool swctrl_lps;
1498
1499 /* default: 1 = using linked fw power save */
1500 bool fwctrl_lps;
0c817338
LF		 1501};
1502
62e63975
LF		 1503struct rtl_hal_usbint_cfg {
1504 /* data - rx */
1505 u32 in_ep_num;
1506 u32 rx_urb_num;
1507 u32 rx_max_size;
1508
1509 /* op - rx */
1510 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1511 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1512 struct sk_buff_head *);
1513
1514 /* tx */
1515 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1516 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1517 struct sk_buff *);
1518 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1519 struct sk_buff_head *);
1520
1521 /* endpoint mapping */
1522 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
17c9ac62 1523 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
62e63975
LF		 1524};
1525
0c817338 1526struct rtl_hal_cfg {
e97b775d 1527 u8 bar_id;
3dad618b 1528 bool write_readback;
0c817338
LF		 1529 char *name;
1530 char *fw_name;
1531 struct rtl_hal_ops *ops;
1532 struct rtl_mod_params *mod_params;
62e63975 1533 struct rtl_hal_usbint_cfg *usb_interface_cfg;
0c817338
LF		 1534
1535 /*this map used for some registers or vars
1536 defined int HAL but used in MAIN */
1537 u32 maps[RTL_VAR_MAP_MAX];
1538
1539};
1540
1541struct rtl_locks {
d704300f 1542 /* mutex */
8a09d6d8 1543 struct mutex conf_mutex;
0c817338
LF		 1544
1545 /*spin lock */
d704300f 1546 spinlock_t ips_lock;
0c817338
LF		 1547 spinlock_t irq_th_lock;
1548 spinlock_t h2c_lock;
1549 spinlock_t rf_ps_lock;
1550 spinlock_t rf_lock;
1551 spinlock_t lps_lock;
e97b775d 1552 spinlock_t waitq_lock;
e97b775d
LF		 1553
1554 /*Dual mac*/
1555 spinlock_t cck_and_rw_pagea_lock;
0c817338
LF		 1556};
1557
1558struct rtl_works {
1559 struct ieee80211_hw *hw;
1560
1561 /*timer */
1562 struct timer_list watchdog_timer;
1563
1564 /*task */
1565 struct tasklet_struct irq_tasklet;
1566 struct tasklet_struct irq_prepare_bcn_tasklet;
1567
1568 /*work queue */
1569 struct workqueue_struct *rtl_wq;
1570 struct delayed_work watchdog_wq;
1571 struct delayed_work ips_nic_off_wq;
e97b775d
LF		 1572
1573 /* For SW LPS */
1574 struct delayed_work ps_work;
1575 struct delayed_work ps_rfon_wq;
67fc6052 1576 struct tasklet_struct ips_leave_tasklet;
0c817338
LF		 1577};
1578
1579struct rtl_debug {
1580 u32 dbgp_type[DBGP_TYPE_MAX];
1581 u32 global_debuglevel;
1582 u64 global_debugcomponents;
e97b775d
LF		 1583
1584 /* add for proc debug */
1585 struct proc_dir_entry *proc_dir;
1586 char proc_name[20];
0c817338
LF		 1587};
1588
1589struct rtl_priv {
1590 struct rtl_locks locks;
1591 struct rtl_works works;
1592 struct rtl_mac mac80211;
1593 struct rtl_hal rtlhal;
1594 struct rtl_regulatory regd;
1595 struct rtl_rfkill rfkill;
1596 struct rtl_io io;
1597 struct rtl_phy phy;
1598 struct rtl_dm dm;
1599 struct rtl_security sec;
1600 struct rtl_efuse efuse;
1601
1602 struct rtl_ps_ctl psc;
1603 struct rate_adaptive ra;
1604 struct wireless_stats stats;
1605 struct rt_link_detect link_info;
1606 struct false_alarm_statistics falsealm_cnt;
1607
1608 struct rtl_rate_priv *rate_priv;
1609
1610 struct rtl_debug dbg;
1611
1612 /*
1613 *hal_cfg : for diff cards
1614 *intf_ops : for diff interrface usb/pcie
1615 */
1616 struct rtl_hal_cfg *cfg;
1617 struct rtl_intf_ops *intf_ops;
1618
1619 /*this var will be set by set_bit,
1620 and was used to indicate status of
1621 interface or hardware */
1622 unsigned long status;
1623
1624 /*This must be the last item so
1625 that it points to the data allocated
1626 beyond this structure like:
1627 rtl_pci_priv or rtl_usb_priv */
1628 u8 priv[0];
1629};
1630
1631#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1632#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1633#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1634#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1635#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1636
e97b775d 1637
18d30067 1638/***************************************
25985edc 1639 Bluetooth Co-existence Related
18d30067
G		 1640****************************************/
1641
1642enum bt_ant_num {
1643 ANT_X2 = 0,
1644 ANT_X1 = 1,
1645};
1646
1647enum bt_co_type {
1648 BT_2WIRE = 0,
1649 BT_ISSC_3WIRE = 1,
1650 BT_ACCEL = 2,
1651 BT_CSR_BC4 = 3,
1652 BT_CSR_BC8 = 4,
1653 BT_RTL8756 = 5,
1654};
1655
1656enum bt_cur_state {
1657 BT_OFF = 0,
1658 BT_ON = 1,
1659};
1660
1661enum bt_service_type {
1662 BT_SCO = 0,
1663 BT_A2DP = 1,
1664 BT_HID = 2,
1665 BT_HID_IDLE = 3,
1666 BT_SCAN = 4,
1667 BT_IDLE = 5,
1668 BT_OTHER_ACTION = 6,
1669 BT_BUSY = 7,
1670 BT_OTHERBUSY = 8,
1671 BT_PAN = 9,
1672};
1673
1674enum bt_radio_shared {
1675 BT_RADIO_SHARED = 0,
1676 BT_RADIO_INDIVIDUAL = 1,
1677};
1678
1679struct bt_coexist_info {
1680
1681 /* EEPROM BT info. */
1682 u8 eeprom_bt_coexist;
1683 u8 eeprom_bt_type;
1684 u8 eeprom_bt_ant_num;
1685 u8 eeprom_bt_ant_isolation;
1686 u8 eeprom_bt_radio_shared;
1687
1688 u8 bt_coexistence;
1689 u8 bt_ant_num;
1690 u8 bt_coexist_type;
1691 u8 bt_state;
1692 u8 bt_cur_state; /* 0:on, 1:off */
1693 u8 bt_ant_isolation; /* 0:good, 1:bad */
1694 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1695 u8 bt_service;
1696 u8 bt_radio_shared_type;
1697 u8 bt_rfreg_origin_1e;
1698 u8 bt_rfreg_origin_1f;
1699 u8 bt_rssi_state;
1700 u32 ratio_tx;
1701 u32 ratio_pri;
1702 u32 bt_edca_ul;
1703 u32 bt_edca_dl;
1704
32473284
LF		 1705 bool init_set;
1706 bool bt_busy_traffic;
1707 bool bt_traffic_mode_set;
1708 bool bt_non_traffic_mode_set;
18d30067 1709
32473284
LF		 1710 bool fw_coexist_all_off;
1711 bool sw_coexist_all_off;
18d30067
G		 1712 u32 current_state;
1713 u32 previous_state;
1714 u8 bt_pre_rssi_state;
1715
32473284
LF		 1716 u8 reg_bt_iso;
1717 u8 reg_bt_sco;
18d30067
G		 1718
1719};
1720
e97b775d 1721
0c817338
LF		 1722/****************************************
1723 mem access macro define start
1724 Call endian free function when
1725 1. Read/write packet content.
1726 2. Before write integer to IO.
1727 3. After read integer from IO.
1728****************************************/
9e0bc671 1729/* Convert little data endian to host ordering */
0c817338
LF		 1730#define EF1BYTE(_val) \
1731 ((u8)(_val))
1732#define EF2BYTE(_val) \
1733 (le16_to_cpu(_val))
1734#define EF4BYTE(_val) \
1735 (le32_to_cpu(_val))
1736
3dad618b
C		 1737/* Read data from memory */
1738#define READEF1BYTE(_ptr) \
1739 EF1BYTE(*((u8 *)(_ptr)))
9e0bc671 1740/* Read le16 data from memory and convert to host ordering */
0c817338
LF		 1741#define READEF2BYTE(_ptr) \
1742 EF2BYTE(*((u16 *)(_ptr)))
3dad618b
C		 1743#define READEF4BYTE(_ptr) \
1744 EF4BYTE(*((u32 *)(_ptr)))
0c817338 1745
3dad618b
C		 1746/* Write data to memory */
1747#define WRITEEF1BYTE(_ptr, _val) \
1748 (*((u8 *)(_ptr))) = EF1BYTE(_val)
9e0bc671 1749/* Write le16 data to memory in host ordering */
0c817338
LF		 1750#define WRITEEF2BYTE(_ptr, _val) \
1751 (*((u16 *)(_ptr))) = EF2BYTE(_val)
3dad618b
C		 1752#define WRITEEF4BYTE(_ptr, _val) \
1753 (*((u16 *)(_ptr))) = EF2BYTE(_val)
9e0bc671
LF		 1754
1755/* Create a bit mask
1756 * Examples:
1757 * BIT_LEN_MASK_32(0) => 0x00000000
1758 * BIT_LEN_MASK_32(1) => 0x00000001
1759 * BIT_LEN_MASK_32(2) => 0x00000003
1760 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1761 */
0c817338
LF		 1762#define BIT_LEN_MASK_32(__bitlen) \
1763 (0xFFFFFFFF >> (32 - (__bitlen)))
1764#define BIT_LEN_MASK_16(__bitlen) \
1765 (0xFFFF >> (16 - (__bitlen)))
1766#define BIT_LEN_MASK_8(__bitlen) \
1767 (0xFF >> (8 - (__bitlen)))
1768
9e0bc671
LF		 1769/* Create an offset bit mask
1770 * Examples:
1771 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1772 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1773 */
0c817338
LF		 1774#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1775 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1776#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1777 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1778#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1779 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1780
1781/*Description:
9e0bc671
LF		 1782 * Return 4-byte value in host byte ordering from
1783 * 4-byte pointer in little-endian system.
1784 */
0c817338
LF		 1785#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1786 (EF4BYTE(*((u32 *)(__pstart))))
1787#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1788 (EF2BYTE(*((u16 *)(__pstart))))
1789#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1790 (EF1BYTE(*((u8 *)(__pstart))))
1791
3dad618b
C		 1792/*Description:
1793Translate subfield (continuous bits in little-endian) of 4-byte
1794value to host byte ordering.*/
1795#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1796 ( \
1797 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1798 BIT_LEN_MASK_32(__bitlen) \
1799 )
1800#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1801 ( \
1802 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1803 BIT_LEN_MASK_16(__bitlen) \
1804 )
1805#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1806 ( \
1807 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1808 BIT_LEN_MASK_8(__bitlen) \
1809 )
1810
9e0bc671
LF		 1811/* Description:
1812 * Mask subfield (continuous bits in little-endian) of 4-byte value
1813 * and return the result in 4-byte value in host byte ordering.
1814 */
0c817338
LF		 1815#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1816 ( \
1817 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1818 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1819 )
1820#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1821 ( \
1822 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1823 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1824 )
1825#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1826 ( \
1827 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1828 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1829 )
1830
9e0bc671
LF		 1831/* Description:
1832 * Set subfield of little-endian 4-byte value to specified value.
1833 */
3dad618b
C		 1834#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1835 *((u32 *)(__pstart)) = EF4BYTE \
1836 ( \
1837 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1838 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1839 );
1840#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1841 *((u16 *)(__pstart)) = EF2BYTE \
1842 ( \
1843 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1844 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1845 );
0c817338
LF		 1846#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1847 *((u8 *)(__pstart)) = EF1BYTE \
1848 ( \
1849 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1850 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1851 );
1852
3dad618b
C		 1853#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1854 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1855
0c817338
LF		 1856/****************************************
1857 mem access macro define end
1858****************************************/
1859
e97b775d
LF		 1860#define byte(x, n) ((x >> (8 * n)) & 0xff)
1861
3dad618b 1862#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
0c817338
LF		 1863#define RTL_WATCH_DOG_TIME 2000
1864#define MSECS(t) msecs_to_jiffies(t)
17c9ac62
LF		 1865#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1866#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1867#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1868#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
0c817338
LF		 1869#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1870#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1871#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1872
1873#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1874#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1875#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1876/*NIC halt, re-initialize hw parameters*/
1877#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1878#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1879#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1880/*Always enable ASPM and Clock Req in initialization.*/
1881#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
e97b775d
LF		 1882/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1883#define RT_PS_LEVEL_ASPM BIT(7)
0c817338
LF		 1884/*When LPS is on, disable 2R if no packet is received or transmittd.*/
1885#define RT_RF_LPS_DISALBE_2R BIT(30)
1886#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1887#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1888 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1889#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1890 (ppsc->cur_ps_level &= (~(_ps_flg)))
1891#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1892 (ppsc->cur_ps_level |= _ps_flg)
1893
1894#define container_of_dwork_rtl(x, y, z) \
1895 container_of(container_of(x, struct delayed_work, work), y, z)
1896
3dad618b
C		 1897#define FILL_OCTET_STRING(_os, _octet, _len) \
1898 (_os).octet = (u8 *)(_octet); \
1899 (_os).length = (_len);
1900
1901#define CP_MACADDR(des, src) \
1902 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1903 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1904 (des)[4] = (src)[4], (des)[5] = (src)[5])
1905
0c817338
LF		 1906static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1907{
1908 return rtlpriv->io.read8_sync(rtlpriv, addr);
1909}
1910
1911static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1912{
1913 return rtlpriv->io.read16_sync(rtlpriv, addr);
1914}
1915
1916static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1917{
1918 return rtlpriv->io.read32_sync(rtlpriv, addr);
1919}
1920
1921static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1922{
1923 rtlpriv->io.write8_async(rtlpriv, addr, val8);
3dad618b
C		 1924
1925 if (rtlpriv->cfg->write_readback)
1926 rtlpriv->io.read8_sync(rtlpriv, addr);
0c817338
LF		 1927}
1928
1929static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1930{
1931 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3dad618b
C		 1932
1933 if (rtlpriv->cfg->write_readback)
1934 rtlpriv->io.read16_sync(rtlpriv, addr);
0c817338
LF		 1935}
1936
1937static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1938 u32 addr, u32 val32)
1939{
1940 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3dad618b
C		 1941
1942 if (rtlpriv->cfg->write_readback)
1943 rtlpriv->io.read32_sync(rtlpriv, addr);
0c817338
LF		 1944}
1945
1946static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1947 u32 regaddr, u32 bitmask)
1948{
1949 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1950 regaddr,
1951 bitmask);
1952}
1953
1954static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1955 u32 bitmask, u32 data)
1956{
1957 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1958 regaddr, bitmask,
1959 data);
1960
1961}
1962
1963static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1964 enum radio_path rfpath, u32 regaddr,
1965 u32 bitmask)
1966{
1967 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1968 rfpath,
1969 regaddr,
1970 bitmask);
1971}
1972
1973static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1974 enum radio_path rfpath, u32 regaddr,
1975 u32 bitmask, u32 data)
1976{
1977 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1978 rfpath, regaddr,
1979 bitmask, data);
1980}
1981
1982static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1983{
1984 return (_HAL_STATE_STOP == rtlhal->state);
1985}
1986
1987static inline void set_hal_start(struct rtl_hal *rtlhal)
1988{
1989 rtlhal->state = _HAL_STATE_START;
1990}
1991
1992static inline void set_hal_stop(struct rtl_hal *rtlhal)
1993{
1994 rtlhal->state = _HAL_STATE_STOP;
1995}
1996
1997static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1998{
1999 return rtlphy->rf_type;
2000}
2001
3dad618b
C		 2002static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2003{
2004 return (struct ieee80211_hdr *)(skb->data);
2005}
2006
d3bb1429 2007static inline __le16 rtl_get_fc(struct sk_buff *skb)
3dad618b 2008{
d3bb1429 2009 return rtl_get_hdr(skb)->frame_control;
3dad618b
C		 2010}
2011
2012static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2013{
2014 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2015}
2016
2017static inline u16 rtl_get_tid(struct sk_buff *skb)
2018{
2019 return rtl_get_tid_h(rtl_get_hdr(skb));
2020}
2021
2022static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2023 struct ieee80211_vif *vif,
7101f404 2024 const u8 *bssid)
3dad618b
C		 2025{
2026 return ieee80211_find_sta(vif, bssid);
2027}
2028
0c817338 2029#endif
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