]> Git Repo - linux.git/blame - drivers/video/sm501fb.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
atmel_lcdfb: avoid division by zero
[linux.git] / drivers / video / sm501fb.c
CommitLineData
5fc404e4
BD		 1/* linux/drivers/video/sm501fb.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Vincent Sanders <[email protected]>
5 * Ben Dooks <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Framebuffer driver for the Silicon Motion SM501
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/fb.h>
23#include <linux/init.h>
24#include <linux/vmalloc.h>
25#include <linux/dma-mapping.h>
26#include <linux/interrupt.h>
27#include <linux/workqueue.h>
28#include <linux/wait.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
f22e521f 31#include <linux/console.h>
5fc404e4
BD		 32
33#include <asm/io.h>
34#include <asm/uaccess.h>
35#include <asm/div64.h>
36
37#ifdef CONFIG_PM
38#include <linux/pm.h>
39#endif
40
41#include <linux/sm501.h>
42#include <linux/sm501-regs.h>
43
44#define NR_PALETTE 256
45
46enum sm501_controller {
47 HEAD_CRT = 0,
48 HEAD_PANEL = 1,
49};
50
44363f14 51/* SM501 memory address */
5fc404e4
BD		 52struct sm501_mem {
53 unsigned long size;
54 unsigned long sm_addr;
55 void __iomem *k_addr;
56};
57
58/* private data that is shared between all frambuffers* */
59struct sm501fb_info {
60 struct device *dev;
61 struct fb_info *fb[2]; /* fb info for both heads */
62 struct resource *fbmem_res; /* framebuffer resource */
63 struct resource *regs_res; /* registers resource */
64 struct sm501_platdata_fb *pdata; /* our platform data */
65
c1f303bb
BD		 66 unsigned long pm_crt_ctrl; /* pm: crt ctrl save */
67
5fc404e4
BD		 68 int irq;
69 int swap_endian; /* set to swap rgb=>bgr */
70 void __iomem *regs; /* remapped registers */
71 void __iomem *fbmem; /* remapped framebuffer */
72 size_t fbmem_len; /* length of remapped region */
73};
74
75/* per-framebuffer private data */
76struct sm501fb_par {
77 u32 pseudo_palette[16];
78
79 enum sm501_controller head;
80 struct sm501_mem cursor;
81 struct sm501_mem screen;
82 struct fb_ops ops;
83
84 void *store_fb;
85 void *store_cursor;
86 void __iomem *cursor_regs;
87 struct sm501fb_info *info;
88};
89
90/* Helper functions */
91
92static inline int h_total(struct fb_var_screeninfo *var)
93{
94 return var->xres + var->left_margin +
95 var->right_margin + var->hsync_len;
96}
97
98static inline int v_total(struct fb_var_screeninfo *var)
99{
100 return var->yres + var->upper_margin +
101 var->lower_margin + var->vsync_len;
102}
103
104/* sm501fb_sync_regs()
105 *
106 * This call is mainly for PCI bus systems where we need to
107 * ensure that any writes to the bus are completed before the
108 * next phase, or after completing a function.
109*/
110
111static inline void sm501fb_sync_regs(struct sm501fb_info *info)
112{
113 readl(info->regs);
114}
115
116/* sm501_alloc_mem
117 *
118 * This is an attempt to lay out memory for the two framebuffers and
119 * everything else
120 *
121 * |fbmem_res->start fbmem_res->end|
122 * | |
123 * |fb[0].fix.smem_start | |fb[1].fix.smem_start | 2K |
124 * |-> fb[0].fix.smem_len <-| spare |-> fb[1].fix.smem_len <-|-> cursors <-|
125 *
126 * The "spare" space is for the 2d engine data
127 * the fixed is space for the cursors (2x1Kbyte)
128 *
129 * we need to allocate memory for the 2D acceleration engine
130 * command list and the data for the engine to deal with.
131 *
132 * - all allocations must be 128bit aligned
133 * - cursors are 64x64x2 bits (1Kbyte)
134 *
135 */
136
137#define SM501_MEMF_CURSOR (1)
138#define SM501_MEMF_PANEL (2)
139#define SM501_MEMF_CRT (4)
140#define SM501_MEMF_ACCEL (8)
141
9540f75b
AB		 142static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
143 unsigned int why, size_t size)
5fc404e4
BD		 144{
145 unsigned int ptr = 0;
146
147 switch (why) {
148 case SM501_MEMF_CURSOR:
149 ptr = inf->fbmem_len - size;
150 inf->fbmem_len = ptr;
151 break;
152
153 case SM501_MEMF_PANEL:
154 ptr = inf->fbmem_len - size;
155 if (ptr < inf->fb[0]->fix.smem_len)
156 return -ENOMEM;
157
158 break;
159
160 case SM501_MEMF_CRT:
161 ptr = 0;
162 break;
163
164 case SM501_MEMF_ACCEL:
165 ptr = inf->fb[0]->fix.smem_len;
166
167 if ((ptr + size) >
168 (inf->fb[1]->fix.smem_start - inf->fbmem_res->start))
169 return -ENOMEM;
170 break;
171
172 default:
173 return -EINVAL;
174 }
175
176 mem->size = size;
177 mem->sm_addr = ptr;
178 mem->k_addr = inf->fbmem + ptr;
179
180 dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
181 __func__, mem->sm_addr, mem->k_addr, why, size);
182
183 return 0;
184}
185
186/* sm501fb_ps_to_hz
187 *
188 * Converts a period in picoseconds to Hz.
189 *
190 * Note, we try to keep this in Hz to minimise rounding with
191 * the limited PLL settings on the SM501.
192*/
193
194static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
195{
196 unsigned long long numerator=1000000000000ULL;
197
198 /* 10^12 / picosecond period gives frequency in Hz */
199 do_div(numerator, psvalue);
200 return (unsigned long)numerator;
201}
202
203/* sm501fb_hz_to_ps is identical to the oposite transform */
204
205#define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
206
207/* sm501fb_setup_gamma
208 *
209 * Programs a linear 1.0 gamma ramp in case the gamma
210 * correction is enabled without programming anything else.
211*/
212
213static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
214 unsigned long palette)
215{
216 unsigned long value = 0;
217 int offset;
218
219 /* set gamma values */
220 for (offset = 0; offset < 256 * 4; offset += 4) {
221 writel(value, fbi->regs + palette + offset);
222 value += 0x010101; /* Advance RGB by 1,1,1.*/
223 }
224}
225
226/* sm501fb_check_var
227 *
228 * check common variables for both panel and crt
229*/
230
231static int sm501fb_check_var(struct fb_var_screeninfo *var,
232 struct fb_info *info)
233{
234 struct sm501fb_par *par = info->par;
235 struct sm501fb_info *sm = par->info;
236 unsigned long tmp;
237
238 /* check we can fit these values into the registers */
239
7e533705 240 if (var->hsync_len > 255 || var->vsync_len > 63)
5fc404e4
BD		 241 return -EINVAL;
242
7e533705
VS		 243 /* hdisplay end and hsync start */
244 if ((var->xres + var->right_margin) > 4096)
5fc404e4
BD		 245 return -EINVAL;
246
7e533705 247 /* vdisplay end and vsync start */
5fc404e4
BD		 248 if ((var->yres + var->lower_margin) > 2048)
249 return -EINVAL;
250
251 /* hard limits of device */
252
253 if (h_total(var) > 4096 || v_total(var) > 2048)
254 return -EINVAL;
255
256 /* check our line length is going to be 128 bit aligned */
257
258 tmp = (var->xres * var->bits_per_pixel) / 8;
259 if ((tmp & 15) != 0)
260 return -EINVAL;
261
262 /* check the virtual size */
263
264 if (var->xres_virtual > 4096 || var->yres_virtual > 2048)
265 return -EINVAL;
266
267 /* can cope with 8,16 or 32bpp */
268
269 if (var->bits_per_pixel <= 8)
270 var->bits_per_pixel = 8;
271 else if (var->bits_per_pixel <= 16)
272 var->bits_per_pixel = 16;
273 else if (var->bits_per_pixel == 24)
274 var->bits_per_pixel = 32;
275
276 /* set r/g/b positions and validate bpp */
277 switch(var->bits_per_pixel) {
278 case 8:
279 var->red.length = var->bits_per_pixel;
280 var->red.offset = 0;
281 var->green.length = var->bits_per_pixel;
282 var->green.offset = 0;
283 var->blue.length = var->bits_per_pixel;
284 var->blue.offset = 0;
285 var->transp.length = 0;
19d06eff 286 var->transp.offset = 0;
5fc404e4
BD		 287
288 break;
289
290 case 16:
291 if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
5fc404e4
BD		 292 var->blue.offset = 11;
293 var->green.offset = 5;
294 var->red.offset = 0;
fedbb362
VS		 295 } else {
296 var->red.offset = 11;
297 var->green.offset = 5;
298 var->blue.offset = 0;
5fc404e4 299 }
19d06eff 300 var->transp.offset = 0;
5fc404e4
BD		 301
302 var->red.length = 5;
303 var->green.length = 6;
304 var->blue.length = 5;
305 var->transp.length = 0;
306 break;
307
308 case 32:
309 if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
310 var->transp.offset = 0;
311 var->red.offset = 8;
312 var->green.offset = 16;
313 var->blue.offset = 24;
314 } else {
315 var->transp.offset = 24;
316 var->red.offset = 16;
317 var->green.offset = 8;
318 var->blue.offset = 0;
319 }
320
321 var->red.length = 8;
322 var->green.length = 8;
323 var->blue.length = 8;
324 var->transp.length = 0;
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return 0;
332}
333
334/*
335 * sm501fb_check_var_crt():
336 *
337 * check the parameters for the CRT head, and either bring them
338 * back into range, or return -EINVAL.
339*/
340
341static int sm501fb_check_var_crt(struct fb_var_screeninfo *var,
342 struct fb_info *info)
343{
344 return sm501fb_check_var(var, info);
345}
346
347/* sm501fb_check_var_pnl():
348 *
349 * check the parameters for the CRT head, and either bring them
350 * back into range, or return -EINVAL.
351*/
352
353static int sm501fb_check_var_pnl(struct fb_var_screeninfo *var,
354 struct fb_info *info)
355{
356 return sm501fb_check_var(var, info);
357}
358
359/* sm501fb_set_par_common
360 *
361 * set common registers for framebuffers
362*/
363
364static int sm501fb_set_par_common(struct fb_info *info,
365 struct fb_var_screeninfo *var)
366{
367 struct sm501fb_par *par = info->par;
368 struct sm501fb_info *fbi = par->info;
369 unsigned long pixclock; /* pixelclock in Hz */
370 unsigned long sm501pixclock; /* pixelclock the 501 can achive in Hz */
371 unsigned int mem_type;
372 unsigned int clock_type;
373 unsigned int head_addr;
374
375 dev_dbg(fbi->dev, "%s: %dx%d, bpp = %d, virtual %dx%d\n",
376 __func__, var->xres, var->yres, var->bits_per_pixel,
377 var->xres_virtual, var->yres_virtual);
378
379 switch (par->head) {
380 case HEAD_CRT:
381 mem_type = SM501_MEMF_CRT;
382 clock_type = SM501_CLOCK_V2XCLK;
383 head_addr = SM501_DC_CRT_FB_ADDR;
384 break;
385
386 case HEAD_PANEL:
387 mem_type = SM501_MEMF_PANEL;
388 clock_type = SM501_CLOCK_P2XCLK;
389 head_addr = SM501_DC_PANEL_FB_ADDR;
390 break;
391
392 default:
393 mem_type = 0; /* stop compiler warnings */
394 head_addr = 0;
395 clock_type = 0;
396 }
397
398 switch (var->bits_per_pixel) {
399 case 8:
400 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
401 break;
402
403 case 16:
5619d823 404 info->fix.visual = FB_VISUAL_TRUECOLOR;
5fc404e4
BD		 405 break;
406
407 case 32:
408 info->fix.visual = FB_VISUAL_TRUECOLOR;
409 break;
410 }
411
412 /* allocate fb memory within 501 */
413 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
414 info->fix.smem_len = info->fix.line_length * var->yres_virtual;
415
416 dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
417 info->fix.line_length);
418
419 if (sm501_alloc_mem(fbi, &par->screen, mem_type,
420 info->fix.smem_len)) {
421 dev_err(fbi->dev, "no memory available\n");
422 return -ENOMEM;
423 }
424
425 info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
426
427 info->screen_base = fbi->fbmem + par->screen.sm_addr;
428 info->screen_size = info->fix.smem_len;
429
430 /* set start of framebuffer to the screen */
431
432 writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr);
433
434 /* program CRT clock */
435
436 pixclock = sm501fb_ps_to_hz(var->pixclock);
437
438 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
439 pixclock);
440
441 /* update fb layer with actual clock used */
442 var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
443
444 dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz) = %lu, "
445 "sm501pixclock = %lu, error = %ld%%\n",
446 __func__, var->pixclock, pixclock, sm501pixclock,
447 ((pixclock - sm501pixclock)*100)/pixclock);
448
449 return 0;
450}
451
452/* sm501fb_set_par_geometry
453 *
454 * set the geometry registers for specified framebuffer.
455*/
456
457static void sm501fb_set_par_geometry(struct fb_info *info,
458 struct fb_var_screeninfo *var)
459{
460 struct sm501fb_par *par = info->par;
461 struct sm501fb_info *fbi = par->info;
462 void __iomem *base = fbi->regs;
463 unsigned long reg;
464
465 if (par->head == HEAD_CRT)
466 base += SM501_DC_CRT_H_TOT;
467 else
468 base += SM501_DC_PANEL_H_TOT;
469
470 /* set framebuffer width and display width */
471
472 reg = info->fix.line_length;
473 reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
474
475 writel(reg, fbi->regs + (par->head == HEAD_CRT ?
476 SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET));
477
478 /* program horizontal total */
479
480 reg = (h_total(var) - 1) << 16;
481 reg |= (var->xres - 1);
482
483 writel(reg, base + SM501_OFF_DC_H_TOT);
484
485 /* program horizontal sync */
486
487 reg = var->hsync_len << 16;
488 reg |= var->xres + var->right_margin - 1;
489
490 writel(reg, base + SM501_OFF_DC_H_SYNC);
491
492 /* program vertical total */
493
494 reg = (v_total(var) - 1) << 16;
495 reg |= (var->yres - 1);
496
497 writel(reg, base + SM501_OFF_DC_V_TOT);
498
499 /* program vertical sync */
500 reg = var->vsync_len << 16;
501 reg |= var->yres + var->lower_margin - 1;
502
503 writel(reg, base + SM501_OFF_DC_V_SYNC);
504}
505
506/* sm501fb_pan_crt
507 *
508 * pan the CRT display output within an virtual framebuffer
509*/
510
511static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
512 struct fb_info *info)
513{
514 struct sm501fb_par *par = info->par;
515 struct sm501fb_info *fbi = par->info;
516 unsigned int bytes_pixel = var->bits_per_pixel / 8;
517 unsigned long reg;
518 unsigned long xoffs;
519
520 xoffs = var->xoffset * bytes_pixel;
521
522 reg = readl(fbi->regs + SM501_DC_CRT_CONTROL);
523
524 reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
525 reg |= ((xoffs & 15) / bytes_pixel) << 4;
526 writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
527
528 reg = (par->screen.sm_addr + xoffs +
529 var->yoffset * info->fix.line_length);
530 writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
531
532 sm501fb_sync_regs(fbi);
533 return 0;
534}
535
536/* sm501fb_pan_pnl
537 *
538 * pan the panel display output within an virtual framebuffer
539*/
540
541static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
542 struct fb_info *info)
543{
544 struct sm501fb_par *par = info->par;
545 struct sm501fb_info *fbi = par->info;
546 unsigned long reg;
547
548 reg = var->xoffset | (var->xres_virtual << 16);
549 writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
550
551 reg = var->yoffset | (var->yres_virtual << 16);
552 writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
553
554 sm501fb_sync_regs(fbi);
555 return 0;
556}
557
558/* sm501fb_set_par_crt
559 *
560 * Set the CRT video mode from the fb_info structure
561*/
562
563static int sm501fb_set_par_crt(struct fb_info *info)
564{
565 struct sm501fb_par *par = info->par;
566 struct sm501fb_info *fbi = par->info;
567 struct fb_var_screeninfo *var = &info->var;
568 unsigned long control; /* control register */
569 int ret;
570
571 /* activate new configuration */
572
573 dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
574
575 /* enable CRT DAC - note 0 is on!*/
576 sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
577
578 control = readl(fbi->regs + SM501_DC_CRT_CONTROL);
579
580 control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
581 SM501_DC_CRT_CONTROL_GAMMA |
582 SM501_DC_CRT_CONTROL_BLANK |
583 SM501_DC_CRT_CONTROL_SEL |
584 SM501_DC_CRT_CONTROL_CP |
585 SM501_DC_CRT_CONTROL_TVP);
586
587 /* set the sync polarities before we check data source */
588
589 if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
590 control |= SM501_DC_CRT_CONTROL_HSP;
591
592 if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
593 control |= SM501_DC_CRT_CONTROL_VSP;
594
595 if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
596 /* the head is displaying panel data... */
597
598 sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0);
599 goto out_update;
600 }
601
602 ret = sm501fb_set_par_common(info, var);
603 if (ret) {
604 dev_err(fbi->dev, "failed to set common parameters\n");
605 return ret;
606 }
607
608 sm501fb_pan_crt(var, info);
609 sm501fb_set_par_geometry(info, var);
610
611 control |= SM501_FIFO_3; /* fill if >3 free slots */
612
613 switch(var->bits_per_pixel) {
614 case 8:
615 control |= SM501_DC_CRT_CONTROL_8BPP;
616 break;
617
618 case 16:
619 control |= SM501_DC_CRT_CONTROL_16BPP;
5619d823 620 sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
5fc404e4
BD		 621 break;
622
623 case 32:
624 control |= SM501_DC_CRT_CONTROL_32BPP;
625 sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
626 break;
627
628 default:
629 BUG();
630 }
631
632 control |= SM501_DC_CRT_CONTROL_SEL; /* CRT displays CRT data */
633 control |= SM501_DC_CRT_CONTROL_TE; /* enable CRT timing */
634 control |= SM501_DC_CRT_CONTROL_ENABLE; /* enable CRT plane */
635
636 out_update:
637 dev_dbg(fbi->dev, "new control is %08lx\n", control);
638
639 writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
640 sm501fb_sync_regs(fbi);
641
642 return 0;
643}
644
645static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
646{
647 unsigned long control;
648 void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
dfcffa46 649 struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl;
5fc404e4
BD		 650
651 control = readl(ctrl_reg);
652
653 if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
654 /* enable panel power */
655
656 control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */
657 writel(control, ctrl_reg);
658 sm501fb_sync_regs(fbi);
659 mdelay(10);
660
661 control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
662 writel(control, ctrl_reg);
663 sm501fb_sync_regs(fbi);
664 mdelay(10);
665
cdc83ae2 666 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
dfcffa46
MD		 667 control |= SM501_DC_PANEL_CONTROL_BIAS; /* VBIASEN */
668 writel(control, ctrl_reg);
669 sm501fb_sync_regs(fbi);
670 mdelay(10);
671 }
5fc404e4 672
cdc83ae2 673 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
dfcffa46
MD		 674 control |= SM501_DC_PANEL_CONTROL_FPEN;
675 writel(control, ctrl_reg);
676 sm501fb_sync_regs(fbi);
677 mdelay(10);
678 }
5fc404e4
BD		 679 } else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
680 /* disable panel power */
cdc83ae2 681 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
dfcffa46
MD		 682 control &= ~SM501_DC_PANEL_CONTROL_FPEN;
683 writel(control, ctrl_reg);
684 sm501fb_sync_regs(fbi);
685 mdelay(10);
686 }
5fc404e4 687
cdc83ae2 688 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
dfcffa46
MD		 689 control &= ~SM501_DC_PANEL_CONTROL_BIAS;
690 writel(control, ctrl_reg);
691 sm501fb_sync_regs(fbi);
692 mdelay(10);
693 }
5fc404e4
BD		 694
695 control &= ~SM501_DC_PANEL_CONTROL_DATA;
696 writel(control, ctrl_reg);
697 sm501fb_sync_regs(fbi);
698 mdelay(10);
699
700 control &= ~SM501_DC_PANEL_CONTROL_VDD;
701 writel(control, ctrl_reg);
702 sm501fb_sync_regs(fbi);
703 mdelay(10);
704 }
705
706 sm501fb_sync_regs(fbi);
707}
708
709/* sm501fb_set_par_pnl
710 *
711 * Set the panel video mode from the fb_info structure
712*/
713
714static int sm501fb_set_par_pnl(struct fb_info *info)
715{
716 struct sm501fb_par *par = info->par;
717 struct sm501fb_info *fbi = par->info;
718 struct fb_var_screeninfo *var = &info->var;
719 unsigned long control;
720 unsigned long reg;
721 int ret;
722
723 dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
724
725 /* activate this new configuration */
726
727 ret = sm501fb_set_par_common(info, var);
728 if (ret)
729 return ret;
730
731 sm501fb_pan_pnl(var, info);
732 sm501fb_set_par_geometry(info, var);
733
734 /* update control register */
735
736 control = readl(fbi->regs + SM501_DC_PANEL_CONTROL);
737 control &= (SM501_DC_PANEL_CONTROL_GAMMA |
738 SM501_DC_PANEL_CONTROL_VDD |
739 SM501_DC_PANEL_CONTROL_DATA |
740 SM501_DC_PANEL_CONTROL_BIAS |
741 SM501_DC_PANEL_CONTROL_FPEN |
742 SM501_DC_PANEL_CONTROL_CP |
743 SM501_DC_PANEL_CONTROL_CK |
744 SM501_DC_PANEL_CONTROL_HP |
745 SM501_DC_PANEL_CONTROL_VP |
746 SM501_DC_PANEL_CONTROL_HPD |
747 SM501_DC_PANEL_CONTROL_VPD);
748
749 control |= SM501_FIFO_3; /* fill if >3 free slots */
750
751 switch(var->bits_per_pixel) {
752 case 8:
753 control |= SM501_DC_PANEL_CONTROL_8BPP;
754 break;
755
756 case 16:
757 control |= SM501_DC_PANEL_CONTROL_16BPP;
5619d823 758 sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
5fc404e4
BD		 759 break;
760
761 case 32:
762 control |= SM501_DC_PANEL_CONTROL_32BPP;
763 sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
764 break;
765
766 default:
767 BUG();
768 }
769
770 writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
771
772 /* panel plane top left and bottom right location */
773
774 writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
775
776 reg = var->xres - 1;
777 reg |= (var->yres - 1) << 16;
778
779 writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
780
781 /* program panel control register */
782
783 control |= SM501_DC_PANEL_CONTROL_TE; /* enable PANEL timing */
784 control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */
785
786 if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
787 control |= SM501_DC_PANEL_CONTROL_HSP;
788
789 if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
790 control |= SM501_DC_PANEL_CONTROL_VSP;
791
792 writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
793 sm501fb_sync_regs(fbi);
794
eb78f9b3
BD		 795 /* ensure the panel interface is not tristated at this point */
796
797 sm501_modify_reg(fbi->dev->parent, SM501_SYSTEM_CONTROL,
798 0, SM501_SYSCTRL_PANEL_TRISTATE);
799
5fc404e4
BD		 800 /* power the panel up */
801 sm501fb_panel_power(fbi, 1);
802 return 0;
803}
804
805
806/* chan_to_field
807 *
808 * convert a colour value into a field position
809 *
810 * from pxafb.c
811*/
812
813static inline unsigned int chan_to_field(unsigned int chan,
814 struct fb_bitfield *bf)
815{
816 chan &= 0xffff;
817 chan >>= 16 - bf->length;
818 return chan << bf->offset;
819}
820
821/* sm501fb_setcolreg
822 *
823 * set the colour mapping for modes that support palettised data
824*/
825
826static int sm501fb_setcolreg(unsigned regno,
827 unsigned red, unsigned green, unsigned blue,
828 unsigned transp, struct fb_info *info)
829{
830 struct sm501fb_par *par = info->par;
831 struct sm501fb_info *fbi = par->info;
832 void __iomem *base = fbi->regs;
833 unsigned int val;
834
835 if (par->head == HEAD_CRT)
836 base += SM501_DC_CRT_PALETTE;
837 else
838 base += SM501_DC_PANEL_PALETTE;
839
840 switch (info->fix.visual) {
841 case FB_VISUAL_TRUECOLOR:
842 /* true-colour, use pseuo-palette */
843
844 if (regno < 16) {
845 u32 *pal = par->pseudo_palette;
846
847 val = chan_to_field(red, &info->var.red);
848 val |= chan_to_field(green, &info->var.green);
849 val |= chan_to_field(blue, &info->var.blue);
850
851 pal[regno] = val;
852 }
853 break;
854
855 case FB_VISUAL_PSEUDOCOLOR:
856 if (regno < 256) {
857 val = (red >> 8) << 16;
858 val |= (green >> 8) << 8;
859 val |= blue >> 8;
860
861 writel(val, base + (regno * 4));
862 }
863
864 break;
865
866 default:
867 return 1; /* unknown type */
868 }
869
870 return 0;
871}
872
873/* sm501fb_blank_pnl
874 *
875 * Blank or un-blank the panel interface
876*/
877
878static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
879{
880 struct sm501fb_par *par = info->par;
881 struct sm501fb_info *fbi = par->info;
882
883 dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
884
885 switch (blank_mode) {
886 case FB_BLANK_POWERDOWN:
887 sm501fb_panel_power(fbi, 0);
888 break;
889
890 case FB_BLANK_UNBLANK:
891 sm501fb_panel_power(fbi, 1);
892 break;
893
894 case FB_BLANK_NORMAL:
895 case FB_BLANK_VSYNC_SUSPEND:
896 case FB_BLANK_HSYNC_SUSPEND:
897 default:
898 return 1;
899 }
900
901 return 0;
902}
903
904/* sm501fb_blank_crt
905 *
906 * Blank or un-blank the crt interface
907*/
908
909static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
910{
911 struct sm501fb_par *par = info->par;
912 struct sm501fb_info *fbi = par->info;
913 unsigned long ctrl;
914
915 dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
916
917 ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL);
918
919 switch (blank_mode) {
920 case FB_BLANK_POWERDOWN:
921 ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
922 sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
923
924 case FB_BLANK_NORMAL:
925 ctrl |= SM501_DC_CRT_CONTROL_BLANK;
926 break;
927
928 case FB_BLANK_UNBLANK:
929 ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
930 ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
931 sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
932 break;
933
934 case FB_BLANK_VSYNC_SUSPEND:
935 case FB_BLANK_HSYNC_SUSPEND:
936 default:
937 return 1;
938
939 }
940
941 writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
942 sm501fb_sync_regs(fbi);
943
944 return 0;
945}
946
947/* sm501fb_cursor
948 *
949 * set or change the hardware cursor parameters
950*/
951
9540f75b 952static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
5fc404e4
BD		 953{
954 struct sm501fb_par *par = info->par;
955 struct sm501fb_info *fbi = par->info;
956 void __iomem *base = fbi->regs;
957 unsigned long hwc_addr;
958 unsigned long fg, bg;
959
960 dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
961
962 if (par->head == HEAD_CRT)
963 base += SM501_DC_CRT_HWC_BASE;
964 else
965 base += SM501_DC_PANEL_HWC_BASE;
966
967 /* check not being asked to exceed capabilities */
968
969 if (cursor->image.width > 64)
970 return -EINVAL;
971
972 if (cursor->image.height > 64)
973 return -EINVAL;
974
975 if (cursor->image.depth > 1)
976 return -EINVAL;
977
978 hwc_addr = readl(base + SM501_OFF_HWC_ADDR);
979
980 if (cursor->enable)
981 writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
982 else
983 writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
984
985 /* set data */
986 if (cursor->set & FB_CUR_SETPOS) {
987 unsigned int x = cursor->image.dx;
988 unsigned int y = cursor->image.dy;
989
990 if (x >= 2048 || y >= 2048 )
991 return -EINVAL;
992
993 dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
994
995 //y += cursor->image.height;
996
997 writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
998 }
999
1000 if (cursor->set & FB_CUR_SETCMAP) {
1001 unsigned int bg_col = cursor->image.bg_color;
1002 unsigned int fg_col = cursor->image.fg_color;
1003
1004 dev_dbg(fbi->dev, "%s: update cmap (%08x,%08x)\n",
1005 __func__, bg_col, fg_col);
1006
1007 bg = ((info->cmap.red[bg_col] & 0xF8) << 8) |
1008 ((info->cmap.green[bg_col] & 0xFC) << 3) |
1009 ((info->cmap.blue[bg_col] & 0xF8) >> 3);
1010
1011 fg = ((info->cmap.red[fg_col] & 0xF8) << 8) |
1012 ((info->cmap.green[fg_col] & 0xFC) << 3) |
1013 ((info->cmap.blue[fg_col] & 0xF8) >> 3);
1014
be3478dd 1015 dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
5fc404e4
BD		 1016
1017 writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
1018 writel(fg, base + SM501_OFF_HWC_COLOR_3);
1019 }
1020
1021 if (cursor->set & FB_CUR_SETSIZE ||
1022 cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1023 /* SM501 cursor is a two bpp 64x64 bitmap this routine
1024 * clears it to transparent then combines the cursor
1025 * shape plane with the colour plane to set the
1026 * cursor */
1027 int x, y;
1028 const unsigned char *pcol = cursor->image.data;
1029 const unsigned char *pmsk = cursor->mask;
1030 void __iomem *dst = par->cursor.k_addr;
1031 unsigned char dcol = 0;
1032 unsigned char dmsk = 0;
1033 unsigned int op;
1034
1035 dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
1036 __func__, cursor->image.width, cursor->image.height);
1037
1038 for (op = 0; op < (64*64*2)/8; op+=4)
1039 writel(0x0, dst + op);
1040
1041 for (y = 0; y < cursor->image.height; y++) {
1042 for (x = 0; x < cursor->image.width; x++) {
1043 if ((x % 8) == 0) {
1044 dcol = *pcol++;
1045 dmsk = *pmsk++;
1046 } else {
1047 dcol >>= 1;
1048 dmsk >>= 1;
1049 }
1050
1051 if (dmsk & 1) {
1052 op = (dcol & 1) ? 1 : 3;
1053 op <<= ((x % 4) * 2);
1054
1055 op |= readb(dst + (x / 4));
1056 writeb(op, dst + (x / 4));
1057 }
1058 }
1059 dst += (64*2)/8;
1060 }
1061 }
1062
1063 sm501fb_sync_regs(fbi); /* ensure cursor data flushed */
1064 return 0;
1065}
1066
1067/* sm501fb_crtsrc_show
1068 *
1069 * device attribute code to show where the crt output is sourced from
1070*/
1071
1072static ssize_t sm501fb_crtsrc_show(struct device *dev,
1073 struct device_attribute *attr, char *buf)
1074{
1075 struct sm501fb_info *info = dev_get_drvdata(dev);
1076 unsigned long ctrl;
1077
1078 ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
1079 ctrl &= SM501_DC_CRT_CONTROL_SEL;
1080
1081 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel");
1082}
1083
1084/* sm501fb_crtsrc_show
1085 *
1086 * device attribute code to set where the crt output is sourced from
1087*/
1088
1089static ssize_t sm501fb_crtsrc_store(struct device *dev,
1090 struct device_attribute *attr,
1091 const char *buf, size_t len)
1092{
1093 struct sm501fb_info *info = dev_get_drvdata(dev);
1094 enum sm501_controller head;
1095 unsigned long ctrl;
1096
1097 if (len < 1)
1098 return -EINVAL;
1099
1f2b69f9 1100 if (strnicmp(buf, "crt", 3) == 0)
5fc404e4 1101 head = HEAD_CRT;
1f2b69f9 1102 else if (strnicmp(buf, "panel", 5) == 0)
5fc404e4
BD		 1103 head = HEAD_PANEL;
1104 else
1105 return -EINVAL;
1106
1107 dev_info(dev, "setting crt source to head %d\n", head);
1108
1109 ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
1110
1111 if (head == HEAD_CRT) {
1112 ctrl |= SM501_DC_CRT_CONTROL_SEL;
1113 ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
1114 ctrl |= SM501_DC_CRT_CONTROL_TE;
1115 } else {
1116 ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
1117 ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
1118 ctrl &= ~SM501_DC_CRT_CONTROL_TE;
1119 }
1120
1121 writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
1122 sm501fb_sync_regs(info);
1123
1f2b69f9 1124 return len;
5fc404e4
BD		 1125}
1126
1127/* Prepare the device_attr for registration with sysfs later */
1128static DEVICE_ATTR(crt_src, 0666, sm501fb_crtsrc_show, sm501fb_crtsrc_store);
1129
1130/* sm501fb_show_regs
1131 *
1132 * show the primary sm501 registers
1133*/
1134static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
1135 unsigned int start, unsigned int len)
1136{
1137 void __iomem *mem = info->regs;
1138 char *buf = ptr;
1139 unsigned int reg;
1140
1141 for (reg = start; reg < (len + start); reg += 4)
1142 ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg));
1143
1144 return ptr - buf;
1145}
1146
1147/* sm501fb_debug_show_crt
1148 *
1149 * show the crt control and cursor registers
1150*/
1151
1152static ssize_t sm501fb_debug_show_crt(struct device *dev,
1153 struct device_attribute *attr, char *buf)
1154{
1155 struct sm501fb_info *info = dev_get_drvdata(dev);
1156 char *ptr = buf;
1157
1158 ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
1159 ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
1160
1161 return ptr - buf;
1162}
1163
1164static DEVICE_ATTR(fbregs_crt, 0444, sm501fb_debug_show_crt, NULL);
1165
1166/* sm501fb_debug_show_pnl
1167 *
1168 * show the panel control and cursor registers
1169*/
1170
1171static ssize_t sm501fb_debug_show_pnl(struct device *dev,
1172 struct device_attribute *attr, char *buf)
1173{
1174 struct sm501fb_info *info = dev_get_drvdata(dev);
1175 char *ptr = buf;
1176
1177 ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
1178 ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
1179
1180 return ptr - buf;
1181}
1182
1183static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
1184
1185/* framebuffer ops */
1186
1187static struct fb_ops sm501fb_ops_crt = {
1188 .owner = THIS_MODULE,
1189 .fb_check_var = sm501fb_check_var_crt,
1190 .fb_set_par = sm501fb_set_par_crt,
1191 .fb_blank = sm501fb_blank_crt,
1192 .fb_setcolreg = sm501fb_setcolreg,
1193 .fb_pan_display = sm501fb_pan_crt,
1194 .fb_cursor = sm501fb_cursor,
1195 .fb_fillrect = cfb_fillrect,
1196 .fb_copyarea = cfb_copyarea,
1197 .fb_imageblit = cfb_imageblit,
1198};
1199
1200static struct fb_ops sm501fb_ops_pnl = {
1201 .owner = THIS_MODULE,
1202 .fb_check_var = sm501fb_check_var_pnl,
1203 .fb_set_par = sm501fb_set_par_pnl,
1204 .fb_pan_display = sm501fb_pan_pnl,
1205 .fb_blank = sm501fb_blank_pnl,
1206 .fb_setcolreg = sm501fb_setcolreg,
1207 .fb_cursor = sm501fb_cursor,
1208 .fb_fillrect = cfb_fillrect,
1209 .fb_copyarea = cfb_copyarea,
1210 .fb_imageblit = cfb_imageblit,
1211};
1212
1213/* sm501fb_info_alloc
1214 *
1215 * creates and initialises an sm501fb_info structure
1216*/
1217
1218static struct sm501fb_info *sm501fb_info_alloc(struct fb_info *fbinfo_crt,
1219 struct fb_info *fbinfo_pnl)
1220{
1221 struct sm501fb_info *info;
1222 struct sm501fb_par *par;
1223
1224 info = kzalloc(sizeof(struct sm501fb_info), GFP_KERNEL);
1225 if (info) {
1226 /* set the references back */
1227
1228 par = fbinfo_crt->par;
1229 par->info = info;
1230 par->head = HEAD_CRT;
1231 fbinfo_crt->pseudo_palette = &par->pseudo_palette;
1232
1233 par = fbinfo_pnl->par;
1234 par->info = info;
1235 par->head = HEAD_PANEL;
1236 fbinfo_pnl->pseudo_palette = &par->pseudo_palette;
1237
1238 /* store the two fbs into our info */
1239 info->fb[HEAD_CRT] = fbinfo_crt;
1240 info->fb[HEAD_PANEL] = fbinfo_pnl;
1241 }
1242
1243 return info;
1244}
1245
1246/* sm501_init_cursor
1247 *
1248 * initialise hw cursor parameters
1249*/
1250
9540f75b 1251static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
5fc404e4
BD		 1252{
1253 struct sm501fb_par *par = fbi->par;
1254 struct sm501fb_info *info = par->info;
1255 int ret;
1256
1257 par->cursor_regs = info->regs + reg_base;
1258
1259 ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024);
1260 if (ret < 0)
1261 return ret;
1262
1263 /* initialise the colour registers */
1264
1265 writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR);
1266
1267 writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
1268 writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
1269 writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
1270 sm501fb_sync_regs(info);
1271
1272 return 0;
1273}
1274
1275/* sm501fb_info_start
1276 *
1277 * fills the par structure claiming resources and remapping etc.
1278*/
1279
1280static int sm501fb_start(struct sm501fb_info *info,
1281 struct platform_device *pdev)
1282{
1283 struct resource *res;
1284 struct device *dev;
b1230ee5 1285 int k;
5fc404e4
BD		 1286 int ret;
1287
1288 info->dev = dev = &pdev->dev;
1289 platform_set_drvdata(pdev, info);
1290
1291 info->irq = ret = platform_get_irq(pdev, 0);
1292 if (ret < 0) {
1293 /* we currently do not use the IRQ */
1294 dev_warn(dev, "no irq for device\n");
1295 }
1296
1297 /* allocate, reserve and remap resources for registers */
1298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299 if (res == NULL) {
1300 dev_err(dev, "no resource definition for registers\n");
1301 ret = -ENOENT;
1302 goto err_release;
1303 }
1304
1305 info->regs_res = request_mem_region(res->start,
1306 res->end - res->start,
1307 pdev->name);
1308
1309 if (info->regs_res == NULL) {
1310 dev_err(dev, "cannot claim registers\n");
1311 ret = -ENXIO;
1312 goto err_release;
1313 }
1314
1315 info->regs = ioremap(res->start, (res->end - res->start)+1);
1316 if (info->regs == NULL) {
1317 dev_err(dev, "cannot remap registers\n");
1318 ret = -ENXIO;
1319 goto err_regs_res;
1320 }
1321
1322 /* allocate, reserve resources for framebuffer */
1323 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1324 if (res == NULL) {
1325 dev_err(dev, "no memory resource defined\n");
1326 ret = -ENXIO;
1327 goto err_regs_map;
1328 }
1329
1330 info->fbmem_res = request_mem_region(res->start,
1331 (res->end - res->start)+1,
1332 pdev->name);
1333 if (info->fbmem_res == NULL) {
1334 dev_err(dev, "cannot claim framebuffer\n");
1335 ret = -ENXIO;
1336 goto err_regs_map;
1337 }
1338
1339 info->fbmem = ioremap(res->start, (res->end - res->start)+1);
1340 if (info->fbmem == NULL) {
1341 dev_err(dev, "cannot remap framebuffer\n");
1342 goto err_mem_res;
1343 }
1344
1345 info->fbmem_len = (res->end - res->start)+1;
1346
b1230ee5
MD		 1347 /* clear framebuffer memory - avoids garbage data on unused fb */
1348 memset(info->fbmem, 0, info->fbmem_len);
1349
1350 /* clear palette ram - undefined at power on */
1351 for (k = 0; k < (256 * 3); k++)
1352 writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
1353
5fc404e4
BD		 1354 /* enable display controller */
1355 sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
1356
1357 /* setup cursors */
1358
1359 sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
1360 sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
1361
1362 return 0; /* everything is setup */
1363
1364 err_mem_res:
1365 release_resource(info->fbmem_res);
1366 kfree(info->fbmem_res);
1367
1368 err_regs_map:
1369 iounmap(info->regs);
1370
1371 err_regs_res:
1372 release_resource(info->regs_res);
1373 kfree(info->regs_res);
1374
1375 err_release:
1376 return ret;
1377}
1378
1379static void sm501fb_stop(struct sm501fb_info *info)
1380{
1381 /* disable display controller */
1382 sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
1383
1384 iounmap(info->fbmem);
1385 release_resource(info->fbmem_res);
1386 kfree(info->fbmem_res);
1387
1388 iounmap(info->regs);
1389 release_resource(info->regs_res);
1390 kfree(info->regs_res);
1391}
1392
1393static void sm501fb_info_release(struct sm501fb_info *info)
1394{
1395 kfree(info);
1396}
1397
1398static int sm501fb_init_fb(struct fb_info *fb,
1399 enum sm501_controller head,
1400 const char *fbname)
1401{
1402 struct sm501_platdata_fbsub *pd;
1403 struct sm501fb_par *par = fb->par;
1404 struct sm501fb_info *info = par->info;
1405 unsigned long ctrl;
1406 unsigned int enable;
1407 int ret;
1408
1409 switch (head) {
1410 case HEAD_CRT:
1411 pd = info->pdata->fb_crt;
1412 ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
1413 enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
1414
1415 /* ensure we set the correct source register */
1416 if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
1417 ctrl |= SM501_DC_CRT_CONTROL_SEL;
1418 writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
1419 }
1420
1421 break;
1422
1423 case HEAD_PANEL:
1424 pd = info->pdata->fb_pnl;
1425 ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL);
1426 enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
1427 break;
1428
1429 default:
1430 pd = NULL; /* stop compiler warnings */
1431 ctrl = 0;
1432 enable = 0;
1433 BUG();
1434 }
1435
1436 dev_info(info->dev, "fb %s %sabled at start\n",
1437 fbname, enable ? "en" : "dis");
1438
1439 /* check to see if our routing allows this */
1440
1441 if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
1442 ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
1443 writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
1444 enable = 0;
1445 }
1446
1447 strlcpy(fb->fix.id, fbname, sizeof(fb->fix.id));
1448
1449 memcpy(&par->ops,
1450 (head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
1451 sizeof(struct fb_ops));
1452
1453 /* update ops dependant on what we've been passed */
1454
1455 if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
1456 par->ops.fb_cursor = NULL;
1457
1458 fb->fbops = &par->ops;
1459 fb->flags = FBINFO_FLAG_DEFAULT |
1460 FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
1461
1462 /* fixed data */
1463
1464 fb->fix.type = FB_TYPE_PACKED_PIXELS;
1465 fb->fix.type_aux = 0;
1466 fb->fix.xpanstep = 1;
1467 fb->fix.ypanstep = 1;
1468 fb->fix.ywrapstep = 0;
1469 fb->fix.accel = FB_ACCEL_NONE;
1470
1471 /* screenmode */
1472
1473 fb->var.nonstd = 0;
1474 fb->var.activate = FB_ACTIVATE_NOW;
1475 fb->var.accel_flags = 0;
1476 fb->var.vmode = FB_VMODE_NONINTERLACED;
1477 fb->var.bits_per_pixel = 16;
1478
1479 if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
1480 /* TODO read the mode from the current display */
1481
1482 } else {
1483 if (pd->def_mode) {
1484 dev_info(info->dev, "using supplied mode\n");
1485 fb_videomode_to_var(&fb->var, pd->def_mode);
1486
1487 fb->var.bits_per_pixel = pd->def_bpp ? pd->def_bpp : 8;
1488 fb->var.xres_virtual = fb->var.xres;
1489 fb->var.yres_virtual = fb->var.yres;
1490 } else {
1491 ret = fb_find_mode(&fb->var, fb,
1492 NULL, NULL, 0, NULL, 8);
1493
1494 if (ret == 0 || ret == 4) {
1495 dev_err(info->dev,
1496 "failed to get initial mode\n");
1497 return -EINVAL;
1498 }
1499 }
1500 }
1501
1502 /* initialise and set the palette */
1503 fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0);
1504 fb_set_cmap(&fb->cmap, fb);
1505
1506 ret = (fb->fbops->fb_check_var)(&fb->var, fb);
1507 if (ret)
1508 dev_err(info->dev, "check_var() failed on initial setup?\n");
1509
1510 /* ensure we've activated our new configuration */
1511 (fb->fbops->fb_set_par)(fb);
1512
1513 return 0;
1514}
1515
1516/* default platform data if none is supplied (ie, PCI device) */
1517
1518static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
1519 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1520 SM501FB_FLAG_USE_HWCURSOR |
1521 SM501FB_FLAG_USE_HWACCEL |
1522 SM501FB_FLAG_DISABLE_AT_EXIT),
1523
1524};
1525
1526static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
1527 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1528 SM501FB_FLAG_USE_HWCURSOR |
1529 SM501FB_FLAG_USE_HWACCEL |
1530 SM501FB_FLAG_DISABLE_AT_EXIT),
1531};
1532
1533static struct sm501_platdata_fb sm501fb_def_pdata = {
1534 .fb_route = SM501_FB_OWN,
1535 .fb_crt = &sm501fb_pdata_crt,
1536 .fb_pnl = &sm501fb_pdata_pnl,
1537};
1538
1539static char driver_name_crt[] = "sm501fb-crt";
1540static char driver_name_pnl[] = "sm501fb-panel";
1541
1542static int __init sm501fb_probe(struct platform_device *pdev)
1543{
1544 struct sm501fb_info *info;
1545 struct device *dev = &pdev->dev;
1546 struct fb_info *fbinfo_crt;
1547 struct fb_info *fbinfo_pnl;
1548 int ret;
1549
1550 /* allocate our framebuffers */
1551
1552 fbinfo_crt = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
1553 if (fbinfo_crt == NULL) {
1554 dev_err(dev, "cannot allocate crt framebuffer\n");
1555 return -ENOMEM;
1556 }
1557
1558 fbinfo_pnl = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
1559 if (fbinfo_pnl == NULL) {
1560 dev_err(dev, "cannot allocate panel framebuffer\n");
1561 ret = -ENOMEM;
1562 goto fbinfo_crt_alloc_fail;
1563 }
1564
1565 info = sm501fb_info_alloc(fbinfo_crt, fbinfo_pnl);
1566 if (info == NULL) {
1567 dev_err(dev, "cannot allocate par\n");
1568 ret = -ENOMEM;
1569 goto sm501fb_alloc_fail;
1570 }
1571
1572 if (dev->parent->platform_data) {
1573 struct sm501_platdata *pd = dev->parent->platform_data;
1574 info->pdata = pd->fb;
1575 }
1576
1577 if (info->pdata == NULL) {
1578 dev_info(dev, "using default configuration data\n");
1579 info->pdata = &sm501fb_def_pdata;
1580 }
1581
1582 /* start the framebuffers */
1583
1584 ret = sm501fb_start(info, pdev);
1585 if (ret) {
1586 dev_err(dev, "cannot initialise SM501\n");
1587 goto sm501fb_start_fail;
1588 }
1589
1590 /* CRT framebuffer setup */
1591
1592 ret = sm501fb_init_fb(fbinfo_crt, HEAD_CRT, driver_name_crt);
1593 if (ret) {
1594 dev_err(dev, "cannot initialise CRT fb\n");
1595 goto sm501fb_start_fail;
1596 }
1597
1598 /* Panel framebuffer setup */
1599
1600 ret = sm501fb_init_fb(fbinfo_pnl, HEAD_PANEL, driver_name_pnl);
1601 if (ret) {
1602 dev_err(dev, "cannot initialise Panel fb\n");
1603 goto sm501fb_start_fail;
1604 }
1605
1606 /* register framebuffers */
1607
1608 ret = register_framebuffer(fbinfo_crt);
1609 if (ret < 0) {
1610 dev_err(dev, "failed to register CRT fb (%d)\n", ret);
1611 goto register_crt_fail;
1612 }
1613
1614 ret = register_framebuffer(fbinfo_pnl);
1615 if (ret < 0) {
1616 dev_err(dev, "failed to register panel fb (%d)\n", ret);
1617 goto register_pnl_fail;
1618 }
1619
1620 dev_info(dev, "fb%d: %s frame buffer device\n",
1621 fbinfo_crt->node, fbinfo_crt->fix.id);
1622
1623 dev_info(dev, "fb%d: %s frame buffer device\n",
1624 fbinfo_pnl->node, fbinfo_pnl->fix.id);
1625
1626 /* create device files */
1627
1628 ret = device_create_file(dev, &dev_attr_crt_src);
1629 if (ret)
1630 goto crtsrc_fail;
1631
1632 ret = device_create_file(dev, &dev_attr_fbregs_pnl);
1633 if (ret)
1634 goto fbregs_pnl_fail;
1635
1636 ret = device_create_file(dev, &dev_attr_fbregs_crt);
1637 if (ret)
1638 goto fbregs_crt_fail;
1639
1640 /* we registered, return ok */
1641 return 0;
1642
1643 fbregs_crt_fail:
1644 device_remove_file(dev, &dev_attr_fbregs_pnl);
1645
1646 fbregs_pnl_fail:
1647 device_remove_file(dev, &dev_attr_crt_src);
1648
1649 crtsrc_fail:
1650 unregister_framebuffer(fbinfo_pnl);
1651
1652 register_pnl_fail:
1653 unregister_framebuffer(fbinfo_crt);
1654
1655 register_crt_fail:
1656 sm501fb_stop(info);
1657
1658 sm501fb_start_fail:
1659 sm501fb_info_release(info);
1660
1661 sm501fb_alloc_fail:
1662 framebuffer_release(fbinfo_pnl);
1663
1664 fbinfo_crt_alloc_fail:
1665 framebuffer_release(fbinfo_crt);
1666
1667 return ret;
1668}
1669
1670
1671/*
1672 * Cleanup
1673 */
1674static int sm501fb_remove(struct platform_device *pdev)
1675{
1676 struct sm501fb_info *info = platform_get_drvdata(pdev);
1677 struct fb_info *fbinfo_crt = info->fb[0];
1678 struct fb_info *fbinfo_pnl = info->fb[1];
1679
1680 device_remove_file(&pdev->dev, &dev_attr_fbregs_crt);
1681 device_remove_file(&pdev->dev, &dev_attr_fbregs_pnl);
1682 device_remove_file(&pdev->dev, &dev_attr_crt_src);
1683
1684 unregister_framebuffer(fbinfo_crt);
1685 unregister_framebuffer(fbinfo_pnl);
1686
1687 sm501fb_stop(info);
1688 sm501fb_info_release(info);
1689
1690 framebuffer_release(fbinfo_pnl);
1691 framebuffer_release(fbinfo_crt);
1692
1693 return 0;
1694}
1695
1696#ifdef CONFIG_PM
1697
1698static int sm501fb_suspend_fb(struct sm501fb_info *info,
1699 enum sm501_controller head)
1700{
1701 struct fb_info *fbi = info->fb[head];
1702 struct sm501fb_par *par = fbi->par;
1703
1704 if (par->screen.size == 0)
1705 return 0;
1706
40488db2
BD		 1707 /* blank the relevant interface to ensure unit power minimised */
1708 (par->ops.fb_blank)(FB_BLANK_POWERDOWN, fbi);
1709
1710 /* tell console/fb driver we are suspending */
1711
1712 acquire_console_sem();
1713 fb_set_suspend(fbi, 1);
1714 release_console_sem();
1715
5fc404e4
BD		 1716 /* backup copies in case chip is powered down over suspend */
1717
1718 par->store_fb = vmalloc(par->screen.size);
1719 if (par->store_fb == NULL) {
1720 dev_err(info->dev, "no memory to store screen\n");
1721 return -ENOMEM;
1722 }
1723
1724 par->store_cursor = vmalloc(par->cursor.size);
1725 if (par->store_cursor == NULL) {
1726 dev_err(info->dev, "no memory to store cursor\n");
1727 goto err_nocursor;
1728 }
1729
c1f303bb
BD		 1730 dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
1731 dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
1732
5fc404e4
BD		 1733 memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
1734 memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
f22e521f 1735
5fc404e4
BD		 1736 return 0;
1737
1738 err_nocursor:
1739 vfree(par->store_fb);
c1f303bb 1740 par->store_fb = NULL;
5fc404e4
BD		 1741
1742 return -ENOMEM;
5fc404e4
BD		 1743}
1744
1745static void sm501fb_resume_fb(struct sm501fb_info *info,
1746 enum sm501_controller head)
1747{
1748 struct fb_info *fbi = info->fb[head];
1749 struct sm501fb_par *par = fbi->par;
1750
1751 if (par->screen.size == 0)
1752 return;
1753
1754 /* re-activate the configuration */
1755
1756 (par->ops.fb_set_par)(fbi);
1757
1758 /* restore the data */
1759
c1f303bb
BD		 1760 dev_dbg(info->dev, "restoring screen from %p\n", par->store_fb);
1761 dev_dbg(info->dev, "restoring cursor from %p\n", par->store_cursor);
1762
1763 if (par->store_fb)
1764 memcpy_toio(par->screen.k_addr, par->store_fb,
1765 par->screen.size);
1766
1767 if (par->store_cursor)
1768 memcpy_toio(par->cursor.k_addr, par->store_cursor,
1769 par->cursor.size);
5fc404e4 1770
f22e521f
BD		 1771 acquire_console_sem();
1772 fb_set_suspend(fbi, 0);
1773 release_console_sem();
1774
5fc404e4
BD		 1775 vfree(par->store_fb);
1776 vfree(par->store_cursor);
1777}
1778
1779
1780/* suspend and resume support */
1781
1782static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
1783{
1784 struct sm501fb_info *info = platform_get_drvdata(pdev);
1785
c1f303bb
BD		 1786 /* store crt control to resume with */
1787 info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
1788
5fc404e4
BD		 1789 sm501fb_suspend_fb(info, HEAD_CRT);
1790 sm501fb_suspend_fb(info, HEAD_PANEL);
1791
1792 /* turn off the clocks, in case the device is not powered down */
1793 sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
1794
1795 return 0;
1796}
1797
c1f303bb
BD		 1798#define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP | \
1799 SM501_DC_CRT_CONTROL_SEL)
1800
1801
5fc404e4
BD		 1802static int sm501fb_resume(struct platform_device *pdev)
1803{
1804 struct sm501fb_info *info = platform_get_drvdata(pdev);
c1f303bb 1805 unsigned long crt_ctrl;
5fc404e4
BD		 1806
1807 sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
1808
c1f303bb
BD		 1809 /* restore the items we want to be saved for crt control */
1810
1811 crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
1812 crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
1813 crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
1814 writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
1815
5fc404e4
BD		 1816 sm501fb_resume_fb(info, HEAD_CRT);
1817 sm501fb_resume_fb(info, HEAD_PANEL);
1818
1819 return 0;
1820}
1821
1822#else
1823#define sm501fb_suspend NULL
1824#define sm501fb_resume NULL
1825#endif
1826
1827static struct platform_driver sm501fb_driver = {
1828 .probe = sm501fb_probe,
1829 .remove = sm501fb_remove,
1830 .suspend = sm501fb_suspend,
1831 .resume = sm501fb_resume,
1832 .driver = {
1833 .name = "sm501-fb",
1834 .owner = THIS_MODULE,
1835 },
1836};
1837
9540f75b 1838static int __devinit sm501fb_init(void)
5fc404e4
BD		 1839{
1840 return platform_driver_register(&sm501fb_driver);
1841}
1842
1843static void __exit sm501fb_cleanup(void)
1844{
1845 platform_driver_unregister(&sm501fb_driver);
1846}
1847
1848module_init(sm501fb_init);
1849module_exit(sm501fb_cleanup);
1850
1851MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
1852MODULE_DESCRIPTION("SM501 Framebuffer driver");
1853MODULE_LICENSE("GPL v2");
Empty description
This page took 0.475306 seconds and 4 git commands to generate.