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[linux.git] / drivers / ssb / main.c
CommitLineData
61e115a5
MB		 1/*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <[email protected]>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "ssb_private.h"
12
13#include <linux/delay.h>
6faf035c 14#include <linux/io.h>
61e115a5
MB		 15#include <linux/ssb/ssb.h>
16#include <linux/ssb/ssb_regs.h>
aab547ce 17#include <linux/ssb/ssb_driver_gige.h>
61e115a5
MB		 18#include <linux/dma-mapping.h>
19#include <linux/pci.h>
20
21#include <pcmcia/cs_types.h>
22#include <pcmcia/cs.h>
23#include <pcmcia/cistpl.h>
24#include <pcmcia/ds.h>
25
26
27MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
28MODULE_LICENSE("GPL");
29
30
31/* Temporary list of yet-to-be-attached buses */
32static LIST_HEAD(attach_queue);
33/* List if running buses */
34static LIST_HEAD(buses);
35/* Software ID counter */
36static unsigned int next_busnumber;
37/* buses_mutes locks the two buslists and the next_busnumber.
38 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
39static DEFINE_MUTEX(buses_mutex);
40
41/* There are differences in the codeflow, if the bus is
42 * initialized from early boot, as various needed services
43 * are not available early. This is a mechanism to delay
44 * these initializations to after early boot has finished.
45 * It's also used to avoid mutex locking, as that's not
46 * available and needed early. */
47static bool ssb_is_early_boot = 1;
48
49static void ssb_buses_lock(void);
50static void ssb_buses_unlock(void);
51
52
53#ifdef CONFIG_SSB_PCIHOST
54struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
55{
56 struct ssb_bus *bus;
57
58 ssb_buses_lock();
59 list_for_each_entry(bus, &buses, list) {
60 if (bus->bustype == SSB_BUSTYPE_PCI &&
61 bus->host_pci == pdev)
62 goto found;
63 }
64 bus = NULL;
65found:
66 ssb_buses_unlock();
67
68 return bus;
69}
70#endif /* CONFIG_SSB_PCIHOST */
71
e7ec2e32
MB		 72#ifdef CONFIG_SSB_PCMCIAHOST
73struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
74{
75 struct ssb_bus *bus;
76
77 ssb_buses_lock();
78 list_for_each_entry(bus, &buses, list) {
79 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
80 bus->host_pcmcia == pdev)
81 goto found;
82 }
83 bus = NULL;
84found:
85 ssb_buses_unlock();
86
87 return bus;
88}
89#endif /* CONFIG_SSB_PCMCIAHOST */
90
aab547ce
MB		 91int ssb_for_each_bus_call(unsigned long data,
92 int (*func)(struct ssb_bus *bus, unsigned long data))
93{
94 struct ssb_bus *bus;
95 int res;
96
97 ssb_buses_lock();
98 list_for_each_entry(bus, &buses, list) {
99 res = func(bus, data);
100 if (res >= 0) {
101 ssb_buses_unlock();
102 return res;
103 }
104 }
105 ssb_buses_unlock();
106
107 return -ENODEV;
108}
109
61e115a5
MB		 110static struct ssb_device *ssb_device_get(struct ssb_device *dev)
111{
112 if (dev)
113 get_device(dev->dev);
114 return dev;
115}
116
117static void ssb_device_put(struct ssb_device *dev)
118{
119 if (dev)
120 put_device(dev->dev);
121}
122
61e115a5
MB		 123static int ssb_device_resume(struct device *dev)
124{
125 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
126 struct ssb_driver *ssb_drv;
61e115a5
MB		 127 int err = 0;
128
61e115a5
MB		 129 if (dev->driver) {
130 ssb_drv = drv_to_ssb_drv(dev->driver);
131 if (ssb_drv && ssb_drv->resume)
132 err = ssb_drv->resume(ssb_dev);
133 if (err)
134 goto out;
135 }
136out:
137 return err;
138}
139
61e115a5
MB		 140static int ssb_device_suspend(struct device *dev, pm_message_t state)
141{
142 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
143 struct ssb_driver *ssb_drv;
61e115a5
MB		 144 int err = 0;
145
146 if (dev->driver) {
147 ssb_drv = drv_to_ssb_drv(dev->driver);
148 if (ssb_drv && ssb_drv->suspend)
149 err = ssb_drv->suspend(ssb_dev, state);
150 if (err)
151 goto out;
152 }
8fe2b65a
MB		 153out:
154 return err;
155}
61e115a5 156
8fe2b65a
MB		 157int ssb_bus_resume(struct ssb_bus *bus)
158{
159 int err;
160
161 /* Reset HW state information in memory, so that HW is
162 * completely reinitialized. */
163 bus->mapped_device = NULL;
164#ifdef CONFIG_SSB_DRIVER_PCICORE
165 bus->pcicore.setup_done = 0;
166#endif
167
168 err = ssb_bus_powerup(bus, 0);
169 if (err)
170 return err;
171 err = ssb_pcmcia_hardware_setup(bus);
172 if (err) {
173 ssb_bus_may_powerdown(bus);
174 return err;
61e115a5 175 }
8fe2b65a
MB		 176 ssb_chipco_resume(&bus->chipco);
177 ssb_bus_may_powerdown(bus);
61e115a5 178
8fe2b65a
MB		 179 return 0;
180}
181EXPORT_SYMBOL(ssb_bus_resume);
182
183int ssb_bus_suspend(struct ssb_bus *bus)
184{
185 ssb_chipco_suspend(&bus->chipco);
186 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
187
188 return 0;
61e115a5 189}
8fe2b65a 190EXPORT_SYMBOL(ssb_bus_suspend);
61e115a5 191
d72bb40f 192#ifdef CONFIG_SSB_SPROM
61e115a5
MB		 193int ssb_devices_freeze(struct ssb_bus *bus)
194{
195 struct ssb_device *dev;
196 struct ssb_driver *drv;
197 int err = 0;
198 int i;
199 pm_message_t state = PMSG_FREEZE;
200
201 /* First check that we are capable to freeze all devices. */
202 for (i = 0; i < bus->nr_devices; i++) {
203 dev = &(bus->devices[i]);
204 if (!dev->dev ||
205 !dev->dev->driver ||
206 !device_is_registered(dev->dev))
207 continue;
208 drv = drv_to_ssb_drv(dev->dev->driver);
209 if (!drv)
210 continue;
211 if (!drv->suspend) {
212 /* Nope, can't suspend this one. */
213 return -EOPNOTSUPP;
214 }
215 }
216 /* Now suspend all devices */
217 for (i = 0; i < bus->nr_devices; i++) {
218 dev = &(bus->devices[i]);
219 if (!dev->dev ||
220 !dev->dev->driver ||
221 !device_is_registered(dev->dev))
222 continue;
223 drv = drv_to_ssb_drv(dev->dev->driver);
224 if (!drv)
225 continue;
226 err = drv->suspend(dev, state);
227 if (err) {
228 ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
229 dev->dev->bus_id);
230 goto err_unwind;
231 }
232 }
233
234 return 0;
235err_unwind:
236 for (i--; i >= 0; i--) {
237 dev = &(bus->devices[i]);
238 if (!dev->dev ||
239 !dev->dev->driver ||
240 !device_is_registered(dev->dev))
241 continue;
242 drv = drv_to_ssb_drv(dev->dev->driver);
243 if (!drv)
244 continue;
245 if (drv->resume)
246 drv->resume(dev);
247 }
248 return err;
249}
250
251int ssb_devices_thaw(struct ssb_bus *bus)
252{
253 struct ssb_device *dev;
254 struct ssb_driver *drv;
255 int err;
256 int i;
257
258 for (i = 0; i < bus->nr_devices; i++) {
259 dev = &(bus->devices[i]);
260 if (!dev->dev ||
261 !dev->dev->driver ||
262 !device_is_registered(dev->dev))
263 continue;
264 drv = drv_to_ssb_drv(dev->dev->driver);
265 if (!drv)
266 continue;
267 if (SSB_WARN_ON(!drv->resume))
268 continue;
269 err = drv->resume(dev);
270 if (err) {
271 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
272 dev->dev->bus_id);
273 }
274 }
275
276 return 0;
277}
d72bb40f 278#endif /* CONFIG_SSB_SPROM */
61e115a5
MB		 279
280static void ssb_device_shutdown(struct device *dev)
281{
282 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
283 struct ssb_driver *ssb_drv;
284
285 if (!dev->driver)
286 return;
287 ssb_drv = drv_to_ssb_drv(dev->driver);
288 if (ssb_drv && ssb_drv->shutdown)
289 ssb_drv->shutdown(ssb_dev);
290}
291
292static int ssb_device_remove(struct device *dev)
293{
294 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
295 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
296
297 if (ssb_drv && ssb_drv->remove)
298 ssb_drv->remove(ssb_dev);
299 ssb_device_put(ssb_dev);
300
301 return 0;
302}
303
304static int ssb_device_probe(struct device *dev)
305{
306 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
307 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
308 int err = 0;
309
310 ssb_device_get(ssb_dev);
311 if (ssb_drv && ssb_drv->probe)
312 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
313 if (err)
314 ssb_device_put(ssb_dev);
315
316 return err;
317}
318
319static int ssb_match_devid(const struct ssb_device_id *tabid,
320 const struct ssb_device_id *devid)
321{
322 if ((tabid->vendor != devid->vendor) &&
323 tabid->vendor != SSB_ANY_VENDOR)
324 return 0;
325 if ((tabid->coreid != devid->coreid) &&
326 tabid->coreid != SSB_ANY_ID)
327 return 0;
328 if ((tabid->revision != devid->revision) &&
329 tabid->revision != SSB_ANY_REV)
330 return 0;
331 return 1;
332}
333
334static int ssb_bus_match(struct device *dev, struct device_driver *drv)
335{
336 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
337 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
338 const struct ssb_device_id *id;
339
340 for (id = ssb_drv->id_table;
341 id->vendor || id->coreid || id->revision;
342 id++) {
343 if (ssb_match_devid(id, &ssb_dev->id))
344 return 1; /* found */
345 }
346
347 return 0;
348}
349
7ac0326c 350static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
61e115a5
MB		 351{
352 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
61e115a5
MB		 353
354 if (!dev)
355 return -ENODEV;
356
7ac0326c 357 return add_uevent_var(env,
61e115a5
MB		 358 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
359 ssb_dev->id.vendor, ssb_dev->id.coreid,
360 ssb_dev->id.revision);
61e115a5
MB		 361}
362
363static struct bus_type ssb_bustype = {
364 .name = "ssb",
365 .match = ssb_bus_match,
366 .probe = ssb_device_probe,
367 .remove = ssb_device_remove,
368 .shutdown = ssb_device_shutdown,
369 .suspend = ssb_device_suspend,
370 .resume = ssb_device_resume,
371 .uevent = ssb_device_uevent,
372};
373
374static void ssb_buses_lock(void)
375{
376 /* See the comment at the ssb_is_early_boot definition */
377 if (!ssb_is_early_boot)
378 mutex_lock(&buses_mutex);
379}
380
381static void ssb_buses_unlock(void)
382{
383 /* See the comment at the ssb_is_early_boot definition */
384 if (!ssb_is_early_boot)
385 mutex_unlock(&buses_mutex);
386}
387
388static void ssb_devices_unregister(struct ssb_bus *bus)
389{
390 struct ssb_device *sdev;
391 int i;
392
393 for (i = bus->nr_devices - 1; i >= 0; i--) {
394 sdev = &(bus->devices[i]);
395 if (sdev->dev)
396 device_unregister(sdev->dev);
397 }
398}
399
400void ssb_bus_unregister(struct ssb_bus *bus)
401{
402 ssb_buses_lock();
403 ssb_devices_unregister(bus);
404 list_del(&bus->list);
405 ssb_buses_unlock();
406
e7ec2e32 407 ssb_pcmcia_exit(bus);
61e115a5
MB		 408 ssb_pci_exit(bus);
409 ssb_iounmap(bus);
410}
411EXPORT_SYMBOL(ssb_bus_unregister);
412
413static void ssb_release_dev(struct device *dev)
414{
415 struct __ssb_dev_wrapper *devwrap;
416
417 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
418 kfree(devwrap);
419}
420
421static int ssb_devices_register(struct ssb_bus *bus)
422{
423 struct ssb_device *sdev;
424 struct device *dev;
425 struct __ssb_dev_wrapper *devwrap;
426 int i, err = 0;
427 int dev_idx = 0;
428
429 for (i = 0; i < bus->nr_devices; i++) {
430 sdev = &(bus->devices[i]);
431
432 /* We don't register SSB-system devices to the kernel,
433 * as the drivers for them are built into SSB. */
434 switch (sdev->id.coreid) {
435 case SSB_DEV_CHIPCOMMON:
436 case SSB_DEV_PCI:
437 case SSB_DEV_PCIE:
438 case SSB_DEV_PCMCIA:
439 case SSB_DEV_MIPS:
440 case SSB_DEV_MIPS_3302:
441 case SSB_DEV_EXTIF:
442 continue;
443 }
444
445 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
446 if (!devwrap) {
447 ssb_printk(KERN_ERR PFX
448 "Could not allocate device\n");
449 err = -ENOMEM;
450 goto error;
451 }
452 dev = &devwrap->dev;
453 devwrap->sdev = sdev;
454
455 dev->release = ssb_release_dev;
456 dev->bus = &ssb_bustype;
457 snprintf(dev->bus_id, sizeof(dev->bus_id),
458 "ssb%u:%d", bus->busnumber, dev_idx);
459
460 switch (bus->bustype) {
461 case SSB_BUSTYPE_PCI:
462#ifdef CONFIG_SSB_PCIHOST
463 sdev->irq = bus->host_pci->irq;
464 dev->parent = &bus->host_pci->dev;
465#endif
466 break;
467 case SSB_BUSTYPE_PCMCIA:
468#ifdef CONFIG_SSB_PCMCIAHOST
60d78c44 469 sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
61e115a5
MB		 470 dev->parent = &bus->host_pcmcia->dev;
471#endif
472 break;
473 case SSB_BUSTYPE_SSB:
474 break;
475 }
476
477 sdev->dev = dev;
478 err = device_register(dev);
479 if (err) {
480 ssb_printk(KERN_ERR PFX
481 "Could not register %s\n",
482 dev->bus_id);
483 /* Set dev to NULL to not unregister
484 * dev on error unwinding. */
485 sdev->dev = NULL;
486 kfree(devwrap);
487 goto error;
488 }
489 dev_idx++;
490 }
491
492 return 0;
493error:
494 /* Unwind the already registered devices. */
495 ssb_devices_unregister(bus);
496 return err;
497}
498
499/* Needs ssb_buses_lock() */
500static int ssb_attach_queued_buses(void)
501{
502 struct ssb_bus *bus, *n;
503 int err = 0;
504 int drop_them_all = 0;
505
506 list_for_each_entry_safe(bus, n, &attach_queue, list) {
507 if (drop_them_all) {
508 list_del(&bus->list);
509 continue;
510 }
511 /* Can't init the PCIcore in ssb_bus_register(), as that
512 * is too early in boot for embedded systems
513 * (no udelay() available). So do it here in attach stage.
514 */
515 err = ssb_bus_powerup(bus, 0);
516 if (err)
517 goto error;
518 ssb_pcicore_init(&bus->pcicore);
519 ssb_bus_may_powerdown(bus);
520
521 err = ssb_devices_register(bus);
522error:
523 if (err) {
524 drop_them_all = 1;
525 list_del(&bus->list);
526 continue;
527 }
528 list_move_tail(&bus->list, &buses);
529 }
530
531 return err;
532}
533
ffc7689d
MB		 534static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
535{
536 struct ssb_bus *bus = dev->bus;
537
538 offset += dev->core_index * SSB_CORE_SIZE;
539 return readb(bus->mmio + offset);
540}
541
61e115a5
MB		 542static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
543{
544 struct ssb_bus *bus = dev->bus;
545
546 offset += dev->core_index * SSB_CORE_SIZE;
547 return readw(bus->mmio + offset);
548}
549
550static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
551{
552 struct ssb_bus *bus = dev->bus;
553
554 offset += dev->core_index * SSB_CORE_SIZE;
555 return readl(bus->mmio + offset);
556}
557
ffc7689d
MB		 558static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
559{
560 struct ssb_bus *bus = dev->bus;
561
562 offset += dev->core_index * SSB_CORE_SIZE;
563 writeb(value, bus->mmio + offset);
564}
565
61e115a5
MB		 566static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
567{
568 struct ssb_bus *bus = dev->bus;
569
570 offset += dev->core_index * SSB_CORE_SIZE;
571 writew(value, bus->mmio + offset);
572}
573
574static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
575{
576 struct ssb_bus *bus = dev->bus;
577
578 offset += dev->core_index * SSB_CORE_SIZE;
579 writel(value, bus->mmio + offset);
580}
581
582/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
583static const struct ssb_bus_ops ssb_ssb_ops = {
ffc7689d 584 .read8 = ssb_ssb_read8,
61e115a5
MB		 585 .read16 = ssb_ssb_read16,
586 .read32 = ssb_ssb_read32,
ffc7689d 587 .write8 = ssb_ssb_write8,
61e115a5
MB		 588 .write16 = ssb_ssb_write16,
589 .write32 = ssb_ssb_write32,
590};
591
592static int ssb_fetch_invariants(struct ssb_bus *bus,
593 ssb_invariants_func_t get_invariants)
594{
595 struct ssb_init_invariants iv;
596 int err;
597
598 memset(&iv, 0, sizeof(iv));
599 err = get_invariants(bus, &iv);
600 if (err)
601 goto out;
602 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
603 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
7cb44615 604 bus->has_cardbus_slot = iv.has_cardbus_slot;
61e115a5
MB		 605out:
606 return err;
607}
608
609static int ssb_bus_register(struct ssb_bus *bus,
610 ssb_invariants_func_t get_invariants,
611 unsigned long baseaddr)
612{
613 int err;
614
615 spin_lock_init(&bus->bar_lock);
616 INIT_LIST_HEAD(&bus->list);
53521d8c
MB		 617#ifdef CONFIG_SSB_EMBEDDED
618 spin_lock_init(&bus->gpio_lock);
619#endif
61e115a5
MB		 620
621 /* Powerup the bus */
622 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
623 if (err)
624 goto out;
625 ssb_buses_lock();
626 bus->busnumber = next_busnumber;
627 /* Scan for devices (cores) */
628 err = ssb_bus_scan(bus, baseaddr);
629 if (err)
630 goto err_disable_xtal;
631
632 /* Init PCI-host device (if any) */
633 err = ssb_pci_init(bus);
634 if (err)
635 goto err_unmap;
636 /* Init PCMCIA-host device (if any) */
637 err = ssb_pcmcia_init(bus);
638 if (err)
639 goto err_pci_exit;
640
641 /* Initialize basic system devices (if available) */
642 err = ssb_bus_powerup(bus, 0);
643 if (err)
644 goto err_pcmcia_exit;
645 ssb_chipcommon_init(&bus->chipco);
646 ssb_mipscore_init(&bus->mipscore);
647 err = ssb_fetch_invariants(bus, get_invariants);
648 if (err) {
649 ssb_bus_may_powerdown(bus);
650 goto err_pcmcia_exit;
651 }
652 ssb_bus_may_powerdown(bus);
653
654 /* Queue it for attach.
655 * See the comment at the ssb_is_early_boot definition. */
656 list_add_tail(&bus->list, &attach_queue);
657 if (!ssb_is_early_boot) {
658 /* This is not early boot, so we must attach the bus now */
659 err = ssb_attach_queued_buses();
660 if (err)
661 goto err_dequeue;
662 }
663 next_busnumber++;
664 ssb_buses_unlock();
665
666out:
667 return err;
668
669err_dequeue:
670 list_del(&bus->list);
671err_pcmcia_exit:
e7ec2e32 672 ssb_pcmcia_exit(bus);
61e115a5
MB		 673err_pci_exit:
674 ssb_pci_exit(bus);
675err_unmap:
676 ssb_iounmap(bus);
677err_disable_xtal:
678 ssb_buses_unlock();
679 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
680 return err;
681}
682
683#ifdef CONFIG_SSB_PCIHOST
684int ssb_bus_pcibus_register(struct ssb_bus *bus,
685 struct pci_dev *host_pci)
686{
687 int err;
688
689 bus->bustype = SSB_BUSTYPE_PCI;
690 bus->host_pci = host_pci;
691 bus->ops = &ssb_pci_ops;
692
693 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
694 if (!err) {
695 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
696 "PCI device %s\n", host_pci->dev.bus_id);
697 }
698
699 return err;
700}
701EXPORT_SYMBOL(ssb_bus_pcibus_register);
702#endif /* CONFIG_SSB_PCIHOST */
703
704#ifdef CONFIG_SSB_PCMCIAHOST
705int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
706 struct pcmcia_device *pcmcia_dev,
707 unsigned long baseaddr)
708{
709 int err;
710
711 bus->bustype = SSB_BUSTYPE_PCMCIA;
712 bus->host_pcmcia = pcmcia_dev;
713 bus->ops = &ssb_pcmcia_ops;
714
715 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
716 if (!err) {
717 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
718 "PCMCIA device %s\n", pcmcia_dev->devname);
719 }
720
721 return err;
722}
723EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
724#endif /* CONFIG_SSB_PCMCIAHOST */
725
726int ssb_bus_ssbbus_register(struct ssb_bus *bus,
727 unsigned long baseaddr,
728 ssb_invariants_func_t get_invariants)
729{
730 int err;
731
732 bus->bustype = SSB_BUSTYPE_SSB;
733 bus->ops = &ssb_ssb_ops;
734
735 err = ssb_bus_register(bus, get_invariants, baseaddr);
736 if (!err) {
737 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
738 "address 0x%08lX\n", baseaddr);
739 }
740
741 return err;
742}
743
744int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
745{
746 drv->drv.name = drv->name;
747 drv->drv.bus = &ssb_bustype;
748 drv->drv.owner = owner;
749
750 return driver_register(&drv->drv);
751}
752EXPORT_SYMBOL(__ssb_driver_register);
753
754void ssb_driver_unregister(struct ssb_driver *drv)
755{
756 driver_unregister(&drv->drv);
757}
758EXPORT_SYMBOL(ssb_driver_unregister);
759
760void ssb_set_devtypedata(struct ssb_device *dev, void *data)
761{
762 struct ssb_bus *bus = dev->bus;
763 struct ssb_device *ent;
764 int i;
765
766 for (i = 0; i < bus->nr_devices; i++) {
767 ent = &(bus->devices[i]);
768 if (ent->id.vendor != dev->id.vendor)
769 continue;
770 if (ent->id.coreid != dev->id.coreid)
771 continue;
772
773 ent->devtypedata = data;
774 }
775}
776EXPORT_SYMBOL(ssb_set_devtypedata);
777
778static u32 clkfactor_f6_resolve(u32 v)
779{
780 /* map the magic values */
781 switch (v) {
782 case SSB_CHIPCO_CLK_F6_2:
783 return 2;
784 case SSB_CHIPCO_CLK_F6_3:
785 return 3;
786 case SSB_CHIPCO_CLK_F6_4:
787 return 4;
788 case SSB_CHIPCO_CLK_F6_5:
789 return 5;
790 case SSB_CHIPCO_CLK_F6_6:
791 return 6;
792 case SSB_CHIPCO_CLK_F6_7:
793 return 7;
794 }
795 return 0;
796}
797
798/* Calculate the speed the backplane would run at a given set of clockcontrol values */
799u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
800{
801 u32 n1, n2, clock, m1, m2, m3, mc;
802
803 n1 = (n & SSB_CHIPCO_CLK_N1);
804 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
805
806 switch (plltype) {
807 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
808 if (m & SSB_CHIPCO_CLK_T6_MMASK)
809 return SSB_CHIPCO_CLK_T6_M0;
810 return SSB_CHIPCO_CLK_T6_M1;
811 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
812 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
813 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
814 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
815 n1 = clkfactor_f6_resolve(n1);
816 n2 += SSB_CHIPCO_CLK_F5_BIAS;
817 break;
818 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
819 n1 += SSB_CHIPCO_CLK_T2_BIAS;
820 n2 += SSB_CHIPCO_CLK_T2_BIAS;
821 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
822 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
823 break;
824 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
825 return 100000000;
826 default:
827 SSB_WARN_ON(1);
828 }
829
830 switch (plltype) {
831 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
832 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
833 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
834 break;
835 default:
836 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
837 }
838 if (!clock)
839 return 0;
840
841 m1 = (m & SSB_CHIPCO_CLK_M1);
842 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
843 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
844 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
845
846 switch (plltype) {
847 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
848 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
849 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
850 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
851 m1 = clkfactor_f6_resolve(m1);
852 if ((plltype == SSB_PLLTYPE_1) ||
853 (plltype == SSB_PLLTYPE_3))
854 m2 += SSB_CHIPCO_CLK_F5_BIAS;
855 else
856 m2 = clkfactor_f6_resolve(m2);
857 m3 = clkfactor_f6_resolve(m3);
858
859 switch (mc) {
860 case SSB_CHIPCO_CLK_MC_BYPASS:
861 return clock;
862 case SSB_CHIPCO_CLK_MC_M1:
863 return (clock / m1);
864 case SSB_CHIPCO_CLK_MC_M1M2:
865 return (clock / (m1 * m2));
866 case SSB_CHIPCO_CLK_MC_M1M2M3:
867 return (clock / (m1 * m2 * m3));
868 case SSB_CHIPCO_CLK_MC_M1M3:
869 return (clock / (m1 * m3));
870 }
871 return 0;
872 case SSB_PLLTYPE_2:
873 m1 += SSB_CHIPCO_CLK_T2_BIAS;
874 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
875 m3 += SSB_CHIPCO_CLK_T2_BIAS;
876 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
877 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
878 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
879
880 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
881 clock /= m1;
882 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
883 clock /= m2;
884 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
885 clock /= m3;
886 return clock;
887 default:
888 SSB_WARN_ON(1);
889 }
890 return 0;
891}
892
893/* Get the current speed the backplane is running at */
894u32 ssb_clockspeed(struct ssb_bus *bus)
895{
896 u32 rate;
897 u32 plltype;
898 u32 clkctl_n, clkctl_m;
899
900 if (ssb_extif_available(&bus->extif))
901 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
902 &clkctl_n, &clkctl_m);
903 else if (bus->chipco.dev)
904 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
905 &clkctl_n, &clkctl_m);
906 else
907 return 0;
908
909 if (bus->chip_id == 0x5365) {
910 rate = 100000000;
911 } else {
912 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
913 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
914 rate /= 2;
915 }
916
917 return rate;
918}
919EXPORT_SYMBOL(ssb_clockspeed);
920
921static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
922{
c272ef44
LF		 923 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
924
61e115a5
MB		 925 /* The REJECT bit changed position in TMSLOW between
926 * Backplane revisions. */
c272ef44 927 switch (rev) {
61e115a5
MB		 928 case SSB_IDLOW_SSBREV_22:
929 return SSB_TMSLOW_REJECT_22;
930 case SSB_IDLOW_SSBREV_23:
931 return SSB_TMSLOW_REJECT_23;
c272ef44
LF		 932 case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
933 case SSB_IDLOW_SSBREV_25: /* same here */
934 case SSB_IDLOW_SSBREV_26: /* same here */
935 case SSB_IDLOW_SSBREV_27: /* same here */
936 return SSB_TMSLOW_REJECT_23; /* this is a guess */
61e115a5 937 default:
c272ef44 938 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
61e115a5
MB		 939 WARN_ON(1);
940 }
941 return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
942}
943
944int ssb_device_is_enabled(struct ssb_device *dev)
945{
946 u32 val;
947 u32 reject;
948
949 reject = ssb_tmslow_reject_bitmask(dev);
950 val = ssb_read32(dev, SSB_TMSLOW);
951 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
952
953 return (val == SSB_TMSLOW_CLOCK);
954}
955EXPORT_SYMBOL(ssb_device_is_enabled);
956
957static void ssb_flush_tmslow(struct ssb_device *dev)
958{
959 /* Make _really_ sure the device has finished the TMSLOW
960 * register write transaction, as we risk running into
961 * a machine check exception otherwise.
962 * Do this by reading the register back to commit the
963 * PCI write and delay an additional usec for the device
964 * to react to the change. */
965 ssb_read32(dev, SSB_TMSLOW);
966 udelay(1);
967}
968
969void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
970{
971 u32 val;
972
973 ssb_device_disable(dev, core_specific_flags);
974 ssb_write32(dev, SSB_TMSLOW,
975 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
976 SSB_TMSLOW_FGC | core_specific_flags);
977 ssb_flush_tmslow(dev);
978
979 /* Clear SERR if set. This is a hw bug workaround. */
980 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
981 ssb_write32(dev, SSB_TMSHIGH, 0);
982
983 val = ssb_read32(dev, SSB_IMSTATE);
984 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
985 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
986 ssb_write32(dev, SSB_IMSTATE, val);
987 }
988
989 ssb_write32(dev, SSB_TMSLOW,
990 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
991 core_specific_flags);
992 ssb_flush_tmslow(dev);
993
994 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
995 core_specific_flags);
996 ssb_flush_tmslow(dev);
997}
998EXPORT_SYMBOL(ssb_device_enable);
999
1000/* Wait for a bit in a register to get set or unset.
1001 * timeout is in units of ten-microseconds */
1002static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1003 int timeout, int set)
1004{
1005 int i;
1006 u32 val;
1007
1008 for (i = 0; i < timeout; i++) {
1009 val = ssb_read32(dev, reg);
1010 if (set) {
1011 if (val & bitmask)
1012 return 0;
1013 } else {
1014 if (!(val & bitmask))
1015 return 0;
1016 }
1017 udelay(10);
1018 }
1019 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1020 "register %04X to %s.\n",
1021 bitmask, reg, (set ? "set" : "clear"));
1022
1023 return -ETIMEDOUT;
1024}
1025
1026void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1027{
1028 u32 reject;
1029
1030 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1031 return;
1032
1033 reject = ssb_tmslow_reject_bitmask(dev);
1034 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1035 ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1036 ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1037 ssb_write32(dev, SSB_TMSLOW,
1038 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1039 reject | SSB_TMSLOW_RESET |
1040 core_specific_flags);
1041 ssb_flush_tmslow(dev);
1042
1043 ssb_write32(dev, SSB_TMSLOW,
1044 reject | SSB_TMSLOW_RESET |
1045 core_specific_flags);
1046 ssb_flush_tmslow(dev);
1047}
1048EXPORT_SYMBOL(ssb_device_disable);
1049
1050u32 ssb_dma_translation(struct ssb_device *dev)
1051{
1052 switch (dev->bus->bustype) {
1053 case SSB_BUSTYPE_SSB:
9788ba75 1054 case SSB_BUSTYPE_PCMCIA:
61e115a5
MB		 1055 return 0;
1056 case SSB_BUSTYPE_PCI:
61e115a5
MB		 1057 return SSB_PCI_DMA;
1058 }
1059 return 0;
1060}
1061EXPORT_SYMBOL(ssb_dma_translation);
1062
1063int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
1064{
1065 struct device *dev = ssb_dev->dev;
1066
1067#ifdef CONFIG_SSB_PCIHOST
1068 if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
1069 !dma_supported(dev, mask))
1070 return -EIO;
1071#endif
1072 dev->coherent_dma_mask = mask;
1073 dev->dma_mask = &dev->coherent_dma_mask;
1074
1075 return 0;
1076}
1077EXPORT_SYMBOL(ssb_dma_set_mask);
1078
1079int ssb_bus_may_powerdown(struct ssb_bus *bus)
1080{
1081 struct ssb_chipcommon *cc;
1082 int err = 0;
1083
1084 /* On buses where more than one core may be working
1085 * at a time, we must not powerdown stuff if there are
1086 * still cores that may want to run. */
1087 if (bus->bustype == SSB_BUSTYPE_SSB)
1088 goto out;
1089
1090 cc = &bus->chipco;
1091 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1092 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1093 if (err)
1094 goto error;
1095out:
1096#ifdef CONFIG_SSB_DEBUG
1097 bus->powered_up = 0;
1098#endif
1099 return err;
1100error:
1101 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1102 goto out;
1103}
1104EXPORT_SYMBOL(ssb_bus_may_powerdown);
1105
1106int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1107{
1108 struct ssb_chipcommon *cc;
1109 int err;
1110 enum ssb_clkmode mode;
1111
1112 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1113 if (err)
1114 goto error;
1115 cc = &bus->chipco;
1116 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1117 ssb_chipco_set_clockmode(cc, mode);
1118
1119#ifdef CONFIG_SSB_DEBUG
1120 bus->powered_up = 1;
1121#endif
1122 return 0;
1123error:
1124 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1125 return err;
1126}
1127EXPORT_SYMBOL(ssb_bus_powerup);
1128
1129u32 ssb_admatch_base(u32 adm)
1130{
1131 u32 base = 0;
1132
1133 switch (adm & SSB_ADM_TYPE) {
1134 case SSB_ADM_TYPE0:
1135 base = (adm & SSB_ADM_BASE0);
1136 break;
1137 case SSB_ADM_TYPE1:
1138 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1139 base = (adm & SSB_ADM_BASE1);
1140 break;
1141 case SSB_ADM_TYPE2:
1142 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1143 base = (adm & SSB_ADM_BASE2);
1144 break;
1145 default:
1146 SSB_WARN_ON(1);
1147 }
1148
1149 return base;
1150}
1151EXPORT_SYMBOL(ssb_admatch_base);
1152
1153u32 ssb_admatch_size(u32 adm)
1154{
1155 u32 size = 0;
1156
1157 switch (adm & SSB_ADM_TYPE) {
1158 case SSB_ADM_TYPE0:
1159 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1160 break;
1161 case SSB_ADM_TYPE1:
1162 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1163 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1164 break;
1165 case SSB_ADM_TYPE2:
1166 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1167 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1168 break;
1169 default:
1170 SSB_WARN_ON(1);
1171 }
1172 size = (1 << (size + 1));
1173
1174 return size;
1175}
1176EXPORT_SYMBOL(ssb_admatch_size);
1177
1178static int __init ssb_modinit(void)
1179{
1180 int err;
1181
1182 /* See the comment at the ssb_is_early_boot definition */
1183 ssb_is_early_boot = 0;
1184 err = bus_register(&ssb_bustype);
1185 if (err)
1186 return err;
1187
1188 /* Maybe we already registered some buses at early boot.
1189 * Check for this and attach them
1190 */
1191 ssb_buses_lock();
1192 err = ssb_attach_queued_buses();
1193 ssb_buses_unlock();
1194 if (err)
1195 bus_unregister(&ssb_bustype);
1196
1197 err = b43_pci_ssb_bridge_init();
1198 if (err) {
1199 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
aab547ce
MB		 1200 "initialization failed\n");
1201 /* don't fail SSB init because of this */
1202 err = 0;
1203 }
1204 err = ssb_gige_init();
1205 if (err) {
1206 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1207 "driver initialization failed\n");
61e115a5
MB		 1208 /* don't fail SSB init because of this */
1209 err = 0;
1210 }
1211
1212 return err;
1213}
8d8c90e3
MB		 1214/* ssb must be initialized after PCI but before the ssb drivers.
1215 * That means we must use some initcall between subsys_initcall
1216 * and device_initcall. */
1217fs_initcall(ssb_modinit);
61e115a5
MB		 1218
1219static void __exit ssb_modexit(void)
1220{
aab547ce 1221 ssb_gige_exit();
61e115a5
MB		 1222 b43_pci_ssb_bridge_exit();
1223 bus_unregister(&ssb_bustype);
1224}
1225module_exit(ssb_modexit)
Empty description
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