[linux.git] / drivers / ata / pata_it8172.c

/*
 * pata_it8172.c 	- IT8172 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <[email protected]>
 *
 * Based heavily on
 *
 * BRIEF MODULE DESCRIPTION
 *      IT8172 IDE controller support
 *
 * Copyright 2000 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              [email protected] or [email protected]
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *	TODO
 *	Check for errata
 *	See if we really need to force native mode
 *	PIO timings (also lacking in original)
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_it8172"
#define DRV_VERSION "0.3.1"

static int it8172_pre_reset(struct ata_port *ap)
{
	static const struct pci_bits it8172_enable_bits[] = {
		{ 0x00, 0, 0x00, 0x00 },
		{ 0x40, 1, 0x00, 0x01 }
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (ap->port_no && !pci_test_config_bits(pdev, &it8172_enable_bits[ap->port_no])) {
		ata_port_disable(ap);
		printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
		return 0;
	}
	ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}

static void it8172_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, it8172_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	it8172_set_pio_timing	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called by both the pio and dma setup functions to set the controller
 *	timings for PIO transfers. We must load both the mode number and
 *	timing values into the controller.
 */

static void it8172_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 reg40;

	pci_read_config_word(pdev, 0x40, &reg40);

	/*
	 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
	 * are being left at the default values of 8 PCI clocks (242 nsec
	 * for a 33 MHz clock). These can be safely shortened at higher
	 * PIO modes. The DIOR/DIOW pulse width and recovery times only
	 * apply to PIO modes, not to the DMA modes.
	 */

	/*
	 * Enable port 0x44. The IT8172G spec is confused; it calls
	 * this register the "Slave IDE Timing Register", but in fact,
	 * it controls timing for both master and slave drives.
	 */

	reg40 |= 0x4000;
	if (adev->devno) {
		reg40 &= 0xC006;
		if (pio > 1)
			/* Enable prefetch and IORDY sample-point */
			reg40 |= 0x0060;
	} else {
		reg40 &= 0xC060;
		if (pio > 1)
			/* Enable prefetch and IORDY sample-point */
			reg40 |= 0x0006;
	}
	/* Write back the enables */
	pci_write_config_word(pdev, 0x40, reg40);
}

/**
 *	it8172_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. We use a shared helper for this
 *	as the DMA setup must also adjust the PIO timing information.
 */

static void it8172_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	it8172_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	it8172_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup. We must tune an appropriate PIO
 *	mode to match.
 */

static void it8172_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = (2 * ap->port_no) + adev->devno;
	u8 reg48, reg4a;
	int pio;

	static const int pio_map[] = { 1, 3, 4};
	/*
	 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
	 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
	 * transfers on some drives, even though both numbers meet the minimum
	 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
	 * So the faster times are just commented out here. The good news is
	 * that the slower cycle time has very little affect on transfer
	 * performance.
	 */

	pci_read_config_byte(pdev, 0x48, &reg48);
	pci_read_config_byte(pdev, 0x4A, &reg4a);

 	reg4a &= ~(3 << (4 * dn));

	if (adev->dma_mode >= XFER_UDMA_0) {
		reg48 |= 1 << dn;
#ifdef UDMA_TIMING_SET
		reg4a |= ((adev->dma_mode - XFER_UDMA_0) << (4 * dn));
#endif
	 	pio = 4;
	} else  {
		pio = pio_map[adev->dma_mode - XFER_MW_DMA_0];
		reg48 &= ~ (1 << dn);
	}
	pci_write_config_byte(pdev, 0x48, reg48);
	pci_write_config_byte(pdev, 0x4A, reg4a);
 	it8172_set_pio_timing(ap, adev, pio);

}

static struct scsi_host_template it8172_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations it8172_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= it8172_set_piomode,
	.set_dmamode	= it8172_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= it8172_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.eng_timeout	= ata_eng_timeout,
	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

static int it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info = {
		.sht = &it8172_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x06,	/* No MWDMA0 support */
		.udma_mask = 0x7,
		.port_ops = &it8172_port_ops
	};
	static struct ata_port_info *port_info[2] = { &info, &info };

        if ((!(PCI_FUNC(dev->devfn) & 1) ||
            (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
		return -ENODEV; /* IT8172 is more than an IDE controller */

	return ata_pci_init_one(dev, port_info, 2);
}

static struct pci_device_id it8172[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G), },
	{ 0, },
};

static struct pci_driver it8172_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= it8172,
	.probe 		= it8172_init_one,
	.remove		= ata_pci_remove_one
};

static int __init it8172_init(void)
{
	return pci_register_driver(&it8172_pci_driver);
}


static void __exit it8172_exit(void)
{
	pci_unregister_driver(&it8172_pci_driver);
}


MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for ITE IT8172");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, it8172);
MODULE_VERSION(DRV_VERSION);

module_init(it8172_init);
module_exit(it8172_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_it8172.c - IT8172 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <[email protected]>
	5	*
	6	* Based heavily on
	7	*
	8	* BRIEF MODULE DESCRIPTION
	9	* IT8172 IDE controller support
	10	*
	11	* Copyright 2000 MontaVista Software Inc.
	12	* Author: MontaVista Software, Inc.
	13	* [email protected] or [email protected]
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms of the GNU General Public License as published by the
	17	* Free Software Foundation; either version 2 of the License, or (at your
	18	* option) any later version.
	19	*
	20	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	21	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	22	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	23	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	24	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	25	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	26	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	29	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	30	*
	31	* You should have received a copy of the GNU General Public License along
	32	* with this program; if not, write to the Free Software Foundation, Inc.,
	33	* 675 Mass Ave, Cambridge, MA 02139, USA.
	34	*
	35	* TODO
	36	* Check for errata
	37	* See if we really need to force native mode
	38	* PIO timings (also lacking in original)
	39	*/
	40
	41	#include <linux/kernel.h>
	42	#include <linux/module.h>
	43	#include <linux/pci.h>
	44	#include <linux/init.h>
	45	#include <linux/blkdev.h>
	46	#include <linux/delay.h>
	47	#include <scsi/scsi_host.h>
	48	#include <linux/libata.h>
	49
	50	#define DRV_NAME "pata_it8172"
	51	#define DRV_VERSION "0.3.1"
	52
	53	static int it8172_pre_reset(struct ata_port *ap)
	54	{
	55	static const struct pci_bits it8172_enable_bits[] = {
	56	{ 0x00, 0, 0x00, 0x00 },
	57	{ 0x40, 1, 0x00, 0x01 }
	58	};
	59
	60	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	61
669a5db4 JG	62	if (ap->port_no && !pci_test_config_bits(pdev, &it8172_enable_bits[ap->port_no])) {
	63	ata_port_disable(ap);
	64	printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
	65	return 0;
	66	}
	67	ap->cbl = ATA_CBL_PATA40;
	68	return ata_std_prereset(ap);
	69	}
	70
	71	static void it8172_error_handler(struct ata_port *ap)
	72	{
	73	ata_bmdma_drive_eh(ap, it8172_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	74	}
	75
	76	/**
	77	* it8172_set_pio_timing - set initial PIO mode data
	78	* @ap: ATA interface
	79	* @adev: ATA device
	80	*
	81	* Called by both the pio and dma setup functions to set the controller
	82	* timings for PIO transfers. We must load both the mode number and
	83	* timing values into the controller.
	84	*/
	85
	86	static void it8172_set_pio_timing(struct ata_port ap, struct ata_device adev, int pio)
	87	{
	88	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	89	u16 reg40;
	90
	91	pci_read_config_word(pdev, 0x40, &reg40);
	92
	93	/*
	94	* FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
	95	* are being left at the default values of 8 PCI clocks (242 nsec
	96	* for a 33 MHz clock). These can be safely shortened at higher
	97	* PIO modes. The DIOR/DIOW pulse width and recovery times only
	98	* apply to PIO modes, not to the DMA modes.
	99	*/
	100
	101	/*
	102	* Enable port 0x44. The IT8172G spec is confused; it calls
	103	* this register the "Slave IDE Timing Register", but in fact,
	104	* it controls timing for both master and slave drives.
	105	*/
	106
	107	reg40 \|= 0x4000;
	108	if (adev->devno) {
	109	reg40 &= 0xC006;
	110	if (pio > 1)
	111	/* Enable prefetch and IORDY sample-point */
	112	reg40 \|= 0x0060;
	113	} else {
	114	reg40 &= 0xC060;
	115	if (pio > 1)
	116	/* Enable prefetch and IORDY sample-point */
	117	reg40 \|= 0x0006;
	118	}
	119	/* Write back the enables */
	120	pci_write_config_word(pdev, 0x40, reg40);
	121	}
	122
	123	/**
	124	* it8172_set_piomode - set initial PIO mode data
	125	* @ap: ATA interface
126	* @adev: ATA device
127	*
128	* Called to do the PIO mode setup. We use a shared helper for this
129	* as the DMA setup must also adjust the PIO timing information.
130	*/
131
132	static void it8172_set_piomode(struct ata_port ap, struct ata_device adev)
133	{
134	it8172_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
135	}
136
137	/**
138	* it8172_set_dmamode - set initial DMA mode data
139	* @ap: ATA interface
140	* @adev: ATA device
141	*
142	* Called to do the DMA mode setup. We must tune an appropriate PIO
143	* mode to match.
144	*/
145
146	static void it8172_set_dmamode(struct ata_port ap, struct ata_device adev)
147	{
148	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149	int dn = (2 * ap->port_no) + adev->devno;
150	u8 reg48, reg4a;
151	int pio;
152
153	static const int pio_map[] = { 1, 3, 4};
154	/*
155	* Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
156	* at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
157	* transfers on some drives, even though both numbers meet the minimum
158	* ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
159	* So the faster times are just commented out here. The good news is
160	* that the slower cycle time has very little affect on transfer
161	* performance.
162	*/
163
164	pci_read_config_byte(pdev, 0x48, &reg48);
165	pci_read_config_byte(pdev, 0x4A, &reg4a);
166
167	reg4a &= ~(3 << (4 * dn));
168
169	if (adev->dma_mode >= XFER_UDMA_0) {
170	reg48 \|= 1 << dn;
171	#ifdef UDMA_TIMING_SET
172	reg4a \|= ((adev->dma_mode - XFER_UDMA_0) << (4 * dn));
173	#endif
174	pio = 4;
175	} else {
176	pio = pio_map[adev->dma_mode - XFER_MW_DMA_0];
177	reg48 &= ~ (1 << dn);
178	}
179	pci_write_config_byte(pdev, 0x48, reg48);
180	pci_write_config_byte(pdev, 0x4A, reg4a);
181	it8172_set_pio_timing(ap, adev, pio);
182
183	}
184
185	static struct scsi_host_template it8172_sht = {
186	.module = THIS_MODULE,
187	.name = DRV_NAME,
188	.ioctl = ata_scsi_ioctl,
189	.queuecommand = ata_scsi_queuecmd,
190	.can_queue = ATA_DEF_QUEUE,
191	.this_id = ATA_SHT_THIS_ID,
192	.sg_tablesize = LIBATA_MAX_PRD,
193	.max_sectors = ATA_MAX_SECTORS,
194	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
195	.emulated = ATA_SHT_EMULATED,
196	.use_clustering = ATA_SHT_USE_CLUSTERING,
197	.proc_name = DRV_NAME,
198	.dma_boundary = ATA_DMA_BOUNDARY,
199	.slave_configure = ata_scsi_slave_config,
200	.bios_param = ata_std_bios_param,
201	};
202
203	static struct ata_port_operations it8172_port_ops = {
204	.port_disable = ata_port_disable,
205	.set_piomode = it8172_set_piomode,
206	.set_dmamode = it8172_set_dmamode,
207	.mode_filter = ata_pci_default_filter,
208
209	.tf_load = ata_tf_load,
210	.tf_read = ata_tf_read,
211	.check_status = ata_check_status,
212	.exec_command = ata_exec_command,
213	.dev_select = ata_std_dev_select,
214
215	.freeze = ata_bmdma_freeze,
216	.thaw = ata_bmdma_thaw,
217	.error_handler = it8172_error_handler,
218	.post_internal_cmd = ata_bmdma_post_internal_cmd,
219
220	.bmdma_setup = ata_bmdma_setup,
221	.bmdma_start = ata_bmdma_start,
222	.bmdma_stop = ata_bmdma_stop,
223	.bmdma_status = ata_bmdma_status,
224
225	.qc_prep = ata_qc_prep,
226	.qc_issue = ata_qc_issue_prot,
227	.eng_timeout = ata_eng_timeout,
228	.data_xfer = ata_pio_data_xfer,
229
230	.irq_handler = ata_interrupt,
231	.irq_clear = ata_bmdma_irq_clear,
232
233	.port_start = ata_port_start,
234	.port_stop = ata_port_stop,
235	.host_stop = ata_host_stop
236	};
237
238	static int it8172_init_one(struct pci_dev dev, const struct pci_device_id id)
239	{
240	static struct ata_port_info info = {
241	.sht = &it8172_sht,
242	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
243	.pio_mask = 0x1f,
244	.mwdma_mask = 0x06, /* No MWDMA0 support */
245	.udma_mask = 0x7,
246	.port_ops = &it8172_port_ops
247	};
248	static struct ata_port_info *port_info[2] = { &info, &info };
249
250	if ((!(PCI_FUNC(dev->devfn) & 1) \|\|
251	(!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
252	return -ENODEV; /* IT8172 is more than an IDE controller */
253
254	return ata_pci_init_one(dev, port_info, 2);
255	}
256
257	static struct pci_device_id it8172[] = {
258	{ PCI_DEVICE(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G), },
259	{ 0, },
260	};
261
262	static struct pci_driver it8172_pci_driver = {
263	.name = DRV_NAME,
264	.id_table = it8172,
265	.probe = it8172_init_one,
266	.remove = ata_pci_remove_one
267	};
268
269	static int __init it8172_init(void)
270	{
271	return pci_register_driver(&it8172_pci_driver);
272	}
273
274
275	static void __exit it8172_exit(void)
276	{
277	pci_unregister_driver(&it8172_pci_driver);
278	}
279
280
281	MODULE_AUTHOR("Alan Cox");
282	MODULE_DESCRIPTION("low-level driver for ITE IT8172");
283	MODULE_LICENSE("GPL");
284	MODULE_DEVICE_TABLE(pci, it8172);
285	MODULE_VERSION(DRV_VERSION);
286
287	module_init(it8172_init);
288	module_exit(it8172_exit);