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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs...
[linux.git] / sound / soc / codecs / wm8955.c
CommitLineData
b35a28af
MB		 1/*
2 * wm8955.c -- WM8955 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/consumer.h>
5a0e3ad6 21#include <linux/slab.h>
b35a28af
MB		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/wm8955.h>
30
31#include "wm8955.h"
32
b35a28af
MB		 33#define WM8955_NUM_SUPPLIES 4
34static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
35 "DCVDD",
36 "DBVDD",
37 "HPVDD",
38 "AVDD",
39};
40
41/* codec private data */
42struct wm8955_priv {
f0fba2ad 43 enum snd_soc_control_type control_type;
f0fba2ad 44
b35a28af
MB		 45 u16 reg_cache[WM8955_MAX_REGISTER + 1];
46
47 unsigned int mclk_rate;
48
49 int deemph;
50 int fs;
51
52 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
b35a28af
MB		 53};
54
55static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
56 0x0000, /* R0 */
57 0x0000, /* R1 */
58 0x0079, /* R2 - LOUT1 volume */
59 0x0079, /* R3 - ROUT1 volume */
60 0x0000, /* R4 */
61 0x0008, /* R5 - DAC Control */
62 0x0000, /* R6 */
63 0x000A, /* R7 - Audio Interface */
64 0x0000, /* R8 - Sample Rate */
65 0x0000, /* R9 */
66 0x00FF, /* R10 - Left DAC volume */
67 0x00FF, /* R11 - Right DAC volume */
68 0x000F, /* R12 - Bass control */
69 0x000F, /* R13 - Treble control */
70 0x0000, /* R14 */
71 0x0000, /* R15 - Reset */
72 0x0000, /* R16 */
73 0x0000, /* R17 */
74 0x0000, /* R18 */
75 0x0000, /* R19 */
76 0x0000, /* R20 */
77 0x0000, /* R21 */
78 0x0000, /* R22 */
79 0x00C1, /* R23 - Additional control (1) */
80 0x0000, /* R24 - Additional control (2) */
81 0x0000, /* R25 - Power Management (1) */
82 0x0000, /* R26 - Power Management (2) */
83 0x0000, /* R27 - Additional Control (3) */
84 0x0000, /* R28 */
85 0x0000, /* R29 */
86 0x0000, /* R30 */
87 0x0000, /* R31 */
88 0x0000, /* R32 */
89 0x0000, /* R33 */
90 0x0050, /* R34 - Left out Mix (1) */
91 0x0050, /* R35 - Left out Mix (2) */
92 0x0050, /* R36 - Right out Mix (1) */
93 0x0050, /* R37 - Right Out Mix (2) */
94 0x0050, /* R38 - Mono out Mix (1) */
95 0x0050, /* R39 - Mono out Mix (2) */
96 0x0079, /* R40 - LOUT2 volume */
97 0x0079, /* R41 - ROUT2 volume */
98 0x0079, /* R42 - MONOOUT volume */
99 0x0000, /* R43 - Clocking / PLL */
100 0x0103, /* R44 - PLL Control 1 */
101 0x0024, /* R45 - PLL Control 2 */
102 0x01BA, /* R46 - PLL Control 3 */
103 0x0000, /* R47 */
104 0x0000, /* R48 */
105 0x0000, /* R49 */
106 0x0000, /* R50 */
107 0x0000, /* R51 */
108 0x0000, /* R52 */
109 0x0000, /* R53 */
110 0x0000, /* R54 */
111 0x0000, /* R55 */
112 0x0000, /* R56 */
113 0x0000, /* R57 */
114 0x0000, /* R58 */
115 0x0000, /* R59 - PLL Control 4 */
116};
117
118static int wm8955_reset(struct snd_soc_codec *codec)
119{
120 return snd_soc_write(codec, WM8955_RESET, 0);
121}
122
123struct pll_factors {
124 int n;
125 int k;
126 int outdiv;
127};
128
129/* The size in bits of the FLL divide multiplied by 10
130 * to allow rounding later */
131#define FIXED_FLL_SIZE ((1 << 22) * 10)
132
133static int wm8995_pll_factors(struct device *dev,
134 int Fref, int Fout, struct pll_factors *pll)
135{
136 u64 Kpart;
137 unsigned int K, Ndiv, Nmod, target;
138
139 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
140
141 /* The oscilator should run at should be 90-100MHz, and
142 * there's a divide by 4 plus an optional divide by 2 in the
143 * output path to generate the system clock. The clock table
144 * is sortd so we should always generate a suitable target. */
145 target = Fout * 4;
146 if (target < 90000000) {
147 pll->outdiv = 1;
148 target *= 2;
149 } else {
150 pll->outdiv = 0;
151 }
152
153 WARN_ON(target < 90000000 || target > 100000000);
154
155 dev_dbg(dev, "Fvco=%dHz\n", target);
156
157 /* Now, calculate N.K */
158 Ndiv = target / Fref;
159
160 pll->n = Ndiv;
161 Nmod = target % Fref;
162 dev_dbg(dev, "Nmod=%d\n", Nmod);
163
164 /* Calculate fractional part - scale up so we can round. */
165 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
166
167 do_div(Kpart, Fref);
168
169 K = Kpart & 0xFFFFFFFF;
170
171 if ((K % 10) >= 5)
172 K += 5;
173
174 /* Move down to proper range now rounding is done */
175 pll->k = K / 10;
176
177 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
178
179 return 0;
180}
181
182/* Lookup table specifiying SRATE (table 25 in datasheet); some of the
183 * output frequencies have been rounded to the standard frequencies
184 * they are intended to match where the error is slight. */
185static struct {
186 int mclk;
187 int fs;
188 int usb;
189 int sr;
190} clock_cfgs[] = {
191 { 18432000, 8000, 0, 3, },
192 { 18432000, 12000, 0, 9, },
193 { 18432000, 16000, 0, 11, },
194 { 18432000, 24000, 0, 29, },
195 { 18432000, 32000, 0, 13, },
196 { 18432000, 48000, 0, 1, },
197 { 18432000, 96000, 0, 15, },
198
199 { 16934400, 8018, 0, 19, },
200 { 16934400, 11025, 0, 25, },
201 { 16934400, 22050, 0, 27, },
202 { 16934400, 44100, 0, 17, },
203 { 16934400, 88200, 0, 31, },
204
205 { 12000000, 8000, 1, 2, },
206 { 12000000, 11025, 1, 25, },
207 { 12000000, 12000, 1, 8, },
208 { 12000000, 16000, 1, 10, },
209 { 12000000, 22050, 1, 27, },
210 { 12000000, 24000, 1, 28, },
211 { 12000000, 32000, 1, 12, },
212 { 12000000, 44100, 1, 17, },
213 { 12000000, 48000, 1, 0, },
214 { 12000000, 88200, 1, 31, },
215 { 12000000, 96000, 1, 14, },
216
217 { 12288000, 8000, 0, 2, },
218 { 12288000, 12000, 0, 8, },
219 { 12288000, 16000, 0, 10, },
220 { 12288000, 24000, 0, 28, },
221 { 12288000, 32000, 0, 12, },
222 { 12288000, 48000, 0, 0, },
223 { 12288000, 96000, 0, 14, },
224
225 { 12289600, 8018, 0, 18, },
226 { 12289600, 11025, 0, 24, },
227 { 12289600, 22050, 0, 26, },
228 { 11289600, 44100, 0, 16, },
229 { 11289600, 88200, 0, 31, },
230};
231
232static int wm8955_configure_clocking(struct snd_soc_codec *codec)
233{
b2c812e2 234 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 235 int i, ret, val;
236 int clocking = 0;
237 int srate = 0;
238 int sr = -1;
239 struct pll_factors pll;
240
241 /* If we're not running a sample rate currently just pick one */
242 if (wm8955->fs == 0)
243 wm8955->fs = 8000;
244
245 /* Can we generate an exact output? */
246 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
247 if (wm8955->fs != clock_cfgs[i].fs)
248 continue;
249 sr = i;
250
251 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
252 break;
253 }
254
255 /* We should never get here with an unsupported sample rate */
256 if (sr == -1) {
257 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
258 wm8955->fs);
259 WARN_ON(sr == -1);
260 return -EINVAL;
261 }
262
263 if (i == ARRAY_SIZE(clock_cfgs)) {
264 /* If we can't generate the right clock from MCLK then
265 * we should configure the PLL to supply us with an
266 * appropriate clock.
267 */
268 clocking |= WM8955_MCLKSEL;
269
270 /* Use the last divider configuration we saw for the
271 * sample rate. */
272 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
273 clock_cfgs[sr].mclk, &pll);
274 if (ret != 0) {
275 dev_err(codec->dev,
276 "Unable to generate %dHz from %dHz MCLK\n",
277 wm8955->fs, wm8955->mclk_rate);
278 return -EINVAL;
279 }
280
281 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
282 WM8955_N_MASK | WM8955_K_21_18_MASK,
283 (pll.n << WM8955_N_SHIFT) |
284 pll.k >> 18);
285 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
286 WM8955_K_17_9_MASK,
287 (pll.k >> 9) & WM8955_K_17_9_MASK);
288 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
289 WM8955_K_8_0_MASK,
290 pll.k & WM8955_K_8_0_MASK);
291 if (pll.k)
292 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
293 WM8955_KEN, WM8955_KEN);
294 else
295 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
296 WM8955_KEN, 0);
297
298 if (pll.outdiv)
299 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
300 else
301 val = WM8955_PLL_RB;
302
303 /* Now start the PLL running */
304 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
305 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
306 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
307 WM8955_PLLEN, WM8955_PLLEN);
308 }
309
310 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
311
312 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
313 WM8955_USB | WM8955_SR_MASK, srate);
314 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
315 WM8955_MCLKSEL, clocking);
316
317 return 0;
318}
319
320static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
321 struct snd_kcontrol *kcontrol, int event)
322{
323 struct snd_soc_codec *codec = w->codec;
324 int ret = 0;
325
326 /* Always disable the clocks - if we're doing reconfiguration this
327 * avoids misclocking.
328 */
329 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
330 WM8955_DIGENB, 0);
331 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
332 WM8955_PLL_RB | WM8955_PLLEN, 0);
333
334 switch (event) {
335 case SND_SOC_DAPM_POST_PMD:
336 break;
337 case SND_SOC_DAPM_PRE_PMU:
338 ret = wm8955_configure_clocking(codec);
339 break;
340 default:
341 ret = -EINVAL;
342 break;
343 }
344
345 return ret;
346}
347
348static int deemph_settings[] = { 0, 32000, 44100, 48000 };
349
350static int wm8955_set_deemph(struct snd_soc_codec *codec)
351{
b2c812e2 352 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 353 int val, i, best;
354
355 /* If we're using deemphasis select the nearest available sample
356 * rate.
357 */
358 if (wm8955->deemph) {
359 best = 1;
360 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
361 if (abs(deemph_settings[i] - wm8955->fs) <
362 abs(deemph_settings[best] - wm8955->fs))
363 best = i;
364 }
365
366 val = best << WM8955_DEEMPH_SHIFT;
367 } else {
368 val = 0;
369 }
370
371 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
372
373 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
374 WM8955_DEEMPH_MASK, val);
375}
376
377static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
378 struct snd_ctl_elem_value *ucontrol)
379{
380 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 381 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 382
383 return wm8955->deemph;
384}
385
386static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_value *ucontrol)
388{
389 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 390 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 391 int deemph = ucontrol->value.enumerated.item[0];
392
393 if (deemph > 1)
394 return -EINVAL;
395
396 wm8955->deemph = deemph;
397
398 return wm8955_set_deemph(codec);
399}
400
401static const char *bass_mode_text[] = {
402 "Linear", "Adaptive",
403};
404
405static const struct soc_enum bass_mode =
406 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
407
408static const char *bass_cutoff_text[] = {
409 "Low", "High"
410};
411
412static const struct soc_enum bass_cutoff =
413 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
414
415static const char *treble_cutoff_text[] = {
416 "High", "Low"
417};
418
419static const struct soc_enum treble_cutoff =
420 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
421
422static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
423static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
424static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
425static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
426static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
427static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
428
429static const struct snd_kcontrol_new wm8955_snd_controls[] = {
430SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
431 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
432SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
433 atten_tlv),
434SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
435 wm8955_get_deemph, wm8955_put_deemph),
436
437SOC_ENUM("Bass Mode", bass_mode),
438SOC_ENUM("Bass Cutoff", bass_cutoff),
439SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
440
441SOC_ENUM("Treble Cutoff", treble_cutoff),
442SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
443
444SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
445 bypass_tlv),
446SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
447 bypass_tlv),
448
449SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
450 bypass_tlv),
451SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
452 bypass_tlv),
453
454/* Not a stereo pair so they line up with the DAPM switches */
455SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
456 mono_tlv),
457SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
458 mono_tlv),
459
460SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
461 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
462SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
463 WM8955_ROUT1_VOLUME, 7, 1, 0),
464
465SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
466 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
467SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
468 WM8955_ROUT2_VOLUME, 7, 1, 0),
469
470SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
471SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
472};
473
474static const struct snd_kcontrol_new lmixer[] = {
475SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
476SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
477SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
478SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
479};
480
481static const struct snd_kcontrol_new rmixer[] = {
482SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
483SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
484SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
485SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
486};
487
488static const struct snd_kcontrol_new mmixer[] = {
489SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
490SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
491SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
492SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
493};
494
495static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
496SND_SOC_DAPM_INPUT("MONOIN-"),
497SND_SOC_DAPM_INPUT("MONOIN+"),
498SND_SOC_DAPM_INPUT("LINEINR"),
499SND_SOC_DAPM_INPUT("LINEINL"),
500
501SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
502
503SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
505SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
506
507SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
508SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
509
510SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
511SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
512SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
513SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
514SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
515SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
516
517/* The names are chosen to make the control names nice */
518SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
519 lmixer, ARRAY_SIZE(lmixer)),
520SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
521 rmixer, ARRAY_SIZE(rmixer)),
522SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
523 mmixer, ARRAY_SIZE(mmixer)),
524
525SND_SOC_DAPM_OUTPUT("LOUT1"),
526SND_SOC_DAPM_OUTPUT("ROUT1"),
527SND_SOC_DAPM_OUTPUT("LOUT2"),
528SND_SOC_DAPM_OUTPUT("ROUT2"),
529SND_SOC_DAPM_OUTPUT("MONOOUT"),
530SND_SOC_DAPM_OUTPUT("OUT3"),
531};
532
533static const struct snd_soc_dapm_route wm8955_intercon[] = {
534 { "DACL", NULL, "SYSCLK" },
535 { "DACR", NULL, "SYSCLK" },
536
537 { "Mono Input", NULL, "MONOIN-" },
538 { "Mono Input", NULL, "MONOIN+" },
539
540 { "Left", "Playback Switch", "DACL" },
541 { "Left", "Right Playback Switch", "DACR" },
542 { "Left", "Bypass Switch", "LINEINL" },
543 { "Left", "Mono Switch", "Mono Input" },
544
545 { "Right", "Playback Switch", "DACR" },
546 { "Right", "Left Playback Switch", "DACL" },
547 { "Right", "Bypass Switch", "LINEINR" },
548 { "Right", "Mono Switch", "Mono Input" },
549
550 { "Mono", "Left Playback Switch", "DACL" },
551 { "Mono", "Right Playback Switch", "DACR" },
552 { "Mono", "Left Bypass Switch", "LINEINL" },
553 { "Mono", "Right Bypass Switch", "LINEINR" },
554
555 { "LOUT1 PGA", NULL, "Left" },
556 { "LOUT1", NULL, "TSDEN" },
557 { "LOUT1", NULL, "LOUT1 PGA" },
558
559 { "ROUT1 PGA", NULL, "Right" },
560 { "ROUT1", NULL, "TSDEN" },
561 { "ROUT1", NULL, "ROUT1 PGA" },
562
563 { "LOUT2 PGA", NULL, "Left" },
564 { "LOUT2", NULL, "TSDEN" },
565 { "LOUT2", NULL, "LOUT2 PGA" },
566
567 { "ROUT2 PGA", NULL, "Right" },
568 { "ROUT2", NULL, "TSDEN" },
569 { "ROUT2", NULL, "ROUT2 PGA" },
570
571 { "MOUT PGA", NULL, "Mono" },
572 { "MONOOUT", NULL, "MOUT PGA" },
573
574 /* OUT3 not currently implemented */
575 { "OUT3", NULL, "OUT3 PGA" },
576};
577
578static int wm8955_add_widgets(struct snd_soc_codec *codec)
579{
580 snd_soc_add_controls(codec, wm8955_snd_controls,
581 ARRAY_SIZE(wm8955_snd_controls));
582
583 snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets,
584 ARRAY_SIZE(wm8955_dapm_widgets));
585
586 snd_soc_dapm_add_routes(codec, wm8955_intercon,
587 ARRAY_SIZE(wm8955_intercon));
588
589 return 0;
590}
591
592static int wm8955_hw_params(struct snd_pcm_substream *substream,
593 struct snd_pcm_hw_params *params,
594 struct snd_soc_dai *dai)
595{
596 struct snd_soc_codec *codec = dai->codec;
b2c812e2 597 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 598 int ret;
599 int wl;
600
601 switch (params_format(params)) {
602 case SNDRV_PCM_FORMAT_S16_LE:
603 wl = 0;
604 break;
605 case SNDRV_PCM_FORMAT_S20_3LE:
606 wl = 0x4;
607 break;
608 case SNDRV_PCM_FORMAT_S24_LE:
609 wl = 0x8;
610 break;
611 case SNDRV_PCM_FORMAT_S32_LE:
612 wl = 0xc;
613 break;
614 default:
615 return -EINVAL;
616 }
617 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
618 WM8955_WL_MASK, wl);
619
620 wm8955->fs = params_rate(params);
621 wm8955_set_deemph(codec);
622
623 /* If the chip is clocked then disable the clocks and force a
624 * reconfiguration, otherwise DAPM will power up the
625 * clocks for us later. */
626 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
627 if (ret < 0)
628 return ret;
629 if (ret & WM8955_DIGENB) {
630 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
631 WM8955_DIGENB, 0);
632 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
633 WM8955_PLL_RB | WM8955_PLLEN, 0);
634
635 wm8955_configure_clocking(codec);
636 }
637
638 return 0;
639}
640
641
642static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
643 unsigned int freq, int dir)
644{
645 struct snd_soc_codec *codec = dai->codec;
b2c812e2 646 struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 647 int div;
648
649 switch (clk_id) {
650 case WM8955_CLK_MCLK:
651 if (freq > 15000000) {
652 priv->mclk_rate = freq /= 2;
653 div = WM8955_MCLKDIV2;
654 } else {
655 priv->mclk_rate = freq;
656 div = 0;
657 }
658
659 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
660 WM8955_MCLKDIV2, div);
661 break;
662
663 default:
664 return -EINVAL;
665 }
666
667 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
668
669 return 0;
670}
671
672static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
673{
674 struct snd_soc_codec *codec = dai->codec;
675 u16 aif = 0;
676
677 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
678 case SND_SOC_DAIFMT_CBS_CFS:
679 break;
680 case SND_SOC_DAIFMT_CBM_CFM:
681 aif |= WM8955_MS;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
688 case SND_SOC_DAIFMT_DSP_B:
689 aif |= WM8955_LRP;
690 case SND_SOC_DAIFMT_DSP_A:
691 aif |= 0x3;
692 break;
693 case SND_SOC_DAIFMT_I2S:
694 aif |= 0x2;
695 break;
696 case SND_SOC_DAIFMT_RIGHT_J:
697 break;
698 case SND_SOC_DAIFMT_LEFT_J:
699 aif |= 0x1;
700 break;
701 default:
702 return -EINVAL;
703 }
704
705 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
706 case SND_SOC_DAIFMT_DSP_A:
707 case SND_SOC_DAIFMT_DSP_B:
708 /* frame inversion not valid for DSP modes */
709 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
710 case SND_SOC_DAIFMT_NB_NF:
711 break;
712 case SND_SOC_DAIFMT_IB_NF:
713 aif |= WM8955_BCLKINV;
714 break;
715 default:
716 return -EINVAL;
717 }
718 break;
719
720 case SND_SOC_DAIFMT_I2S:
721 case SND_SOC_DAIFMT_RIGHT_J:
722 case SND_SOC_DAIFMT_LEFT_J:
723 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
724 case SND_SOC_DAIFMT_NB_NF:
725 break;
726 case SND_SOC_DAIFMT_IB_IF:
727 aif |= WM8955_BCLKINV | WM8955_LRP;
728 break;
729 case SND_SOC_DAIFMT_IB_NF:
730 aif |= WM8955_BCLKINV;
731 break;
732 case SND_SOC_DAIFMT_NB_IF:
733 aif |= WM8955_LRP;
734 break;
735 default:
736 return -EINVAL;
737 }
738 break;
739 default:
740 return -EINVAL;
741 }
742
743 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
744 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
745 WM8955_LRP, aif);
746
747 return 0;
748}
749
750
751static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
752{
753 struct snd_soc_codec *codec = codec_dai->codec;
754 int val;
755
756 if (mute)
757 val = WM8955_DACMU;
758 else
759 val = 0;
760
761 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
762
763 return 0;
764}
765
766static int wm8955_set_bias_level(struct snd_soc_codec *codec,
767 enum snd_soc_bias_level level)
768{
b2c812e2 769 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 770 int ret, i;
771
772 switch (level) {
773 case SND_SOC_BIAS_ON:
774 break;
775
776 case SND_SOC_BIAS_PREPARE:
777 /* VMID resistance 2*50k */
778 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
779 WM8955_VMIDSEL_MASK,
780 0x1 << WM8955_VMIDSEL_SHIFT);
781
782 /* Default bias current */
783 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
784 WM8955_VSEL_MASK,
785 0x2 << WM8955_VSEL_SHIFT);
786 break;
787
788 case SND_SOC_BIAS_STANDBY:
789 if (codec->bias_level == SND_SOC_BIAS_OFF) {
790 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
791 wm8955->supplies);
792 if (ret != 0) {
793 dev_err(codec->dev,
794 "Failed to enable supplies: %d\n",
795 ret);
796 return ret;
797 }
798
799 /* Sync back cached values if they're
800 * different from the hardware default.
801 */
802 for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) {
803 if (i == WM8955_RESET)
804 continue;
805
806 if (wm8955->reg_cache[i] == wm8955_reg[i])
807 continue;
808
809 snd_soc_write(codec, i, wm8955->reg_cache[i]);
810 }
811
812 /* Enable VREF and VMID */
813 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
814 WM8955_VREF |
815 WM8955_VMIDSEL_MASK,
816 WM8955_VREF |
817 0x3 << WM8955_VREF_SHIFT);
818
819 /* Let VMID ramp */
820 msleep(500);
821
822 /* High resistance VROI to maintain outputs */
823 snd_soc_update_bits(codec,
824 WM8955_ADDITIONAL_CONTROL_3,
825 WM8955_VROI, WM8955_VROI);
826 }
827
828 /* Maintain VMID with 2*250k */
829 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
830 WM8955_VMIDSEL_MASK,
831 0x2 << WM8955_VMIDSEL_SHIFT);
832
833 /* Minimum bias current */
834 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
835 WM8955_VSEL_MASK, 0);
836 break;
837
838 case SND_SOC_BIAS_OFF:
839 /* Low resistance VROI to help discharge */
840 snd_soc_update_bits(codec,
841 WM8955_ADDITIONAL_CONTROL_3,
842 WM8955_VROI, 0);
843
844 /* Turn off VMID and VREF */
845 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
846 WM8955_VREF |
847 WM8955_VMIDSEL_MASK, 0);
848
849 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
850 wm8955->supplies);
851 break;
852 }
853 codec->bias_level = level;
854 return 0;
855}
856
857#define WM8955_RATES SNDRV_PCM_RATE_8000_96000
858
859#define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
860 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
861
862static struct snd_soc_dai_ops wm8955_dai_ops = {
863 .set_sysclk = wm8955_set_sysclk,
864 .set_fmt = wm8955_set_fmt,
865 .hw_params = wm8955_hw_params,
866 .digital_mute = wm8955_digital_mute,
867};
868
f0fba2ad
LG		 869static struct snd_soc_dai_driver wm8955_dai = {
870 .name = "wm8955-hifi",
b35a28af
MB		 871 .playback = {
872 .stream_name = "Playback",
873 .channels_min = 2,
874 .channels_max = 2,
875 .rates = WM8955_RATES,
876 .formats = WM8955_FORMATS,
877 },
878 .ops = &wm8955_dai_ops,
879};
b35a28af
MB		 880
881#ifdef CONFIG_PM
f0fba2ad 882static int wm8955_suspend(struct snd_soc_codec *codec, pm_message_t state)
b35a28af 883{
b35a28af
MB		 884 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
885
886 return 0;
887}
888
f0fba2ad 889static int wm8955_resume(struct snd_soc_codec *codec)
b35a28af 890{
b35a28af
MB		 891 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
892
893 return 0;
894}
895#else
896#define wm8955_suspend NULL
897#define wm8955_resume NULL
898#endif
899
f0fba2ad 900static int wm8955_probe(struct snd_soc_codec *codec)
b35a28af 901{
f0fba2ad
LG		 902 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
903 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
904 int ret, i;
b35a28af 905
f0fba2ad 906 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
b35a28af
MB		 907 if (ret != 0) {
908 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 909 return ret;
b35a28af
MB		 910 }
911
912 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
913 wm8955->supplies[i].supply = wm8955_supply_names[i];
914
915 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
916 wm8955->supplies);
917 if (ret != 0) {
918 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 919 return ret;
b35a28af
MB		 920 }
921
922 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
923 wm8955->supplies);
924 if (ret != 0) {
925 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
926 goto err_get;
927 }
928
929 ret = wm8955_reset(codec);
930 if (ret < 0) {
931 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
932 goto err_enable;
933 }
934
b35a28af
MB		 935 /* Change some default settings - latch VU and enable ZC */
936 wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
937 wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
938 wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
939 wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
940 wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
941 wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
942 wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
943
944 /* Also enable adaptive bass boost by default */
945 wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
946
947 /* Set platform data values */
f0fba2ad
LG		 948 if (pdata) {
949 if (pdata->out2_speaker)
b35a28af
MB		 950 wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2]
951 |= WM8955_ROUT2INV;
952
f0fba2ad 953 if (pdata->monoin_diff)
b35a28af
MB		 954 wm8955->reg_cache[WM8955_MONO_OUT_MIX_1]
955 |= WM8955_DMEN;
956 }
957
958 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
959
960 /* Bias level configuration will have done an extra enable */
961 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
962
f0fba2ad 963 wm8955_add_widgets(codec);
b35a28af
MB		 964 return 0;
965
966err_enable:
967 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
968err_get:
969 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
b35a28af
MB		 970 return ret;
971}
972
f0fba2ad 973static int wm8955_remove(struct snd_soc_codec *codec)
b35a28af 974{
f0fba2ad
LG		 975 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
976
977 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
b35a28af 978 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
f0fba2ad 979 return 0;
b35a28af
MB		 980}
981
f0fba2ad
LG		 982static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
983 .probe = wm8955_probe,
984 .remove = wm8955_remove,
985 .suspend = wm8955_suspend,
986 .resume = wm8955_resume,
987 .set_bias_level = wm8955_set_bias_level,
988 .reg_cache_size = ARRAY_SIZE(wm8955_reg),
989 .reg_word_size = sizeof(u16),
990 .reg_cache_default = wm8955_reg,
991};
992
b35a28af
MB		 993#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
994static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
995 const struct i2c_device_id *id)
996{
997 struct wm8955_priv *wm8955;
f0fba2ad 998 int ret;
b35a28af
MB		 999
1000 wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1001 if (wm8955 == NULL)
1002 return -ENOMEM;
1003
b35a28af 1004 i2c_set_clientdata(i2c, wm8955);
b35a28af 1005
f0fba2ad
LG		 1006 ret = snd_soc_register_codec(&i2c->dev,
1007 &soc_codec_dev_wm8955, &wm8955_dai, 1);
1008 if (ret < 0)
1009 kfree(wm8955);
1010 return ret;
b35a28af
MB		 1011}
1012
1013static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1014{
f0fba2ad
LG		 1015 snd_soc_unregister_codec(&client->dev);
1016 kfree(i2c_get_clientdata(client));
b35a28af
MB		 1017 return 0;
1018}
1019
1020static const struct i2c_device_id wm8955_i2c_id[] = {
1021 { "wm8955", 0 },
1022 { }
1023};
1024MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1025
1026static struct i2c_driver wm8955_i2c_driver = {
1027 .driver = {
f0fba2ad 1028 .name = "wm8955-codec",
b35a28af
MB		 1029 .owner = THIS_MODULE,
1030 },
1031 .probe = wm8955_i2c_probe,
1032 .remove = __devexit_p(wm8955_i2c_remove),
1033 .id_table = wm8955_i2c_id,
1034};
1035#endif
1036
1037static int __init wm8955_modinit(void)
1038{
f0fba2ad 1039 int ret = 0;
b35a28af
MB		 1040#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1041 ret = i2c_add_driver(&wm8955_i2c_driver);
1042 if (ret != 0) {
1043 printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1044 ret);
1045 }
1046#endif
f0fba2ad 1047 return ret;
b35a28af
MB		 1048}
1049module_init(wm8955_modinit);
1050
1051static void __exit wm8955_exit(void)
1052{
1053#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1054 i2c_del_driver(&wm8955_i2c_driver);
1055#endif
1056}
1057module_exit(wm8955_exit);
1058
1059MODULE_DESCRIPTION("ASoC WM8955 driver");
1060MODULE_AUTHOR("Mark Brown <[email protected]>");
1061MODULE_LICENSE("GPL");
Empty description
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