[linux.git] / arch / mips / sgi-ip22 / ip22-eisa.c

/*
 * Basic EISA bus support for the SGI Indigo-2.
 *
 * (C) 2002 Pascal Dameme <[email protected]>
 *      and Marc Zyngier <[email protected]>
 *
 * This code is released under both the GPL version 2 and BSD
 * licenses.  Either license may be used.
 *
 * This code offers a very basic support for this EISA bus present in
 * the SGI Indigo-2. It currently only supports PIO (forget about DMA
 * for the time being). This is enough for a low-end ethernet card,
 * but forget about your favorite SCSI card...
 *
 * TODO :
 * - Fix bugs...
 * - Add ISA support
 * - Add DMA (yeah, right...).
 * - Fix more bugs.
 */

#include <linux/eisa.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/ip22.h>

/* I2 has four EISA slots. */
#define IP22_EISA_MAX_SLOTS	  4
#define EISA_MAX_IRQ             16

#define EIU_MODE_REG     0x0001ffc0
#define EIU_STAT_REG     0x0001ffc4
#define EIU_PREMPT_REG   0x0001ffc8
#define EIU_QUIET_REG    0x0001ffcc
#define EIU_INTRPT_ACK   0x00010004

static char __init *decode_eisa_sig(unsigned long addr)
{
        static char sig_str[EISA_SIG_LEN];
	u8 sig[4];
        u16 rev;
	int i;

	for (i = 0; i < 4; i++) {
		sig[i] = inb (addr + i);

		if (!i && (sig[0] & 0x80))
			return NULL;
	}

	sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
	sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
	sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
	rev = (sig[2] << 8) | sig[3];
	sprintf(sig_str + 3, "%04X", rev);

	return sig_str;
}

static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
{
	u8 eisa_irq;
	u8 dma1, dma2;

	eisa_irq = inb(EIU_INTRPT_ACK);
	dma1 = inb(EISA_DMA1_STATUS);
	dma2 = inb(EISA_DMA2_STATUS);

	if (eisa_irq < EISA_MAX_IRQ) {
		do_IRQ(eisa_irq);
		return IRQ_HANDLED;
	}

	/* Oops, Bad Stuff Happened... */
	printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);

	outb(0x20, EISA_INT2_CTRL);
	outb(0x20, EISA_INT1_CTRL);

	return IRQ_NONE;
}

static void enable_eisa1_irq(unsigned int irq)
{
	u8 mask;

	mask = inb(EISA_INT1_MASK);
	mask &= ~((u8) (1 << irq));
	outb(mask, EISA_INT1_MASK);
}

static unsigned int startup_eisa1_irq(unsigned int irq)
{
	u8 edge;

	/* Only use edge interrupts for EISA */

	edge = inb(EISA_INT1_EDGE_LEVEL);
	edge &= ~((u8) (1 << irq));
	outb(edge, EISA_INT1_EDGE_LEVEL);

	enable_eisa1_irq(irq);
	return 0;
}

static void disable_eisa1_irq(unsigned int irq)
{
	u8 mask;

	mask = inb(EISA_INT1_MASK);
	mask |= ((u8) (1 << irq));
	outb(mask, EISA_INT1_MASK);
}

static void mask_and_ack_eisa1_irq(unsigned int irq)
{
	disable_eisa1_irq(irq);

	outb(0x20, EISA_INT1_CTRL);
}

static void end_eisa1_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_eisa1_irq(irq);
}

static struct irq_chip ip22_eisa1_irq_type = {
	.typename	= "IP22 EISA",
	.startup	= startup_eisa1_irq,
	.ack		= mask_and_ack_eisa1_irq,
	.mask		= disable_eisa1_irq,
	.mask_ack	= mask_and_ack_eisa1_irq,
	.unmask		= enable_eisa1_irq,
	.end		= end_eisa1_irq,
};

static void enable_eisa2_irq(unsigned int irq)
{
	u8 mask;

	mask = inb(EISA_INT2_MASK);
	mask &= ~((u8) (1 << (irq - 8)));
	outb(mask, EISA_INT2_MASK);
}

static unsigned int startup_eisa2_irq(unsigned int irq)
{
	u8 edge;

	/* Only use edge interrupts for EISA */

	edge = inb(EISA_INT2_EDGE_LEVEL);
	edge &= ~((u8) (1 << (irq - 8)));
	outb(edge, EISA_INT2_EDGE_LEVEL);

	enable_eisa2_irq(irq);
	return 0;
}

static void disable_eisa2_irq(unsigned int irq)
{
	u8 mask;

	mask = inb(EISA_INT2_MASK);
	mask |= ((u8) (1 << (irq - 8)));
	outb(mask, EISA_INT2_MASK);
}

static void mask_and_ack_eisa2_irq(unsigned int irq)
{
	disable_eisa2_irq(irq);

	outb(0x20, EISA_INT2_CTRL);
}

static void end_eisa2_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_eisa2_irq(irq);
}

static struct irq_chip ip22_eisa2_irq_type = {
	.typename	= "IP22 EISA",
	.startup	= startup_eisa2_irq,
	.ack		= mask_and_ack_eisa2_irq,
	.mask		= disable_eisa2_irq,
	.mask_ack	= mask_and_ack_eisa2_irq,
	.unmask		= enable_eisa2_irq,
	.end		= end_eisa2_irq,
};

static struct irqaction eisa_action = {
	.handler	= ip22_eisa_intr,
	.name		= "EISA",
};

static struct irqaction cascade_action = {
	.handler	= no_action,
	.name		= "EISA cascade",
};

int __init ip22_eisa_init(void)
{
	int i, c;
	char *str;

	if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
		printk(KERN_INFO "EISA: bus not present.\n");
		return 1;
	}

	printk(KERN_INFO "EISA: Probing bus...\n");
	for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
		if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
			printk(KERN_INFO "EISA: slot %d : %s detected.\n",
			       i, str);
			c++;
		}
	}
	printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
#ifdef CONFIG_ISA
	printk(KERN_INFO "ISA support compiled in.\n");
#endif

	/* Warning : BlackMagicAhead(tm).
	   Please wave your favorite dead chicken over the busses */

	/* First say hello to the EIU */
	outl(0x0000FFFF, EIU_PREMPT_REG);
	outl(1, EIU_QUIET_REG);
	outl(0x40f3c07F, EIU_MODE_REG);

	/* Now be nice to the EISA chipset */
	outb(1, EISA_EXT_NMI_RESET_CTRL);
	udelay(50);	/* Wait long enough for the dust to settle */
	outb(0, EISA_EXT_NMI_RESET_CTRL);
	outb(0x11, EISA_INT1_CTRL);
	outb(0x11, EISA_INT2_CTRL);
	outb(0, EISA_INT1_MASK);
	outb(8, EISA_INT2_MASK);
	outb(4, EISA_INT1_MASK);
	outb(2, EISA_INT2_MASK);
	outb(1, EISA_INT1_MASK);
	outb(1, EISA_INT2_MASK);
	outb(0xfb, EISA_INT1_MASK);
	outb(0xff, EISA_INT2_MASK);
	outb(0, EISA_DMA2_WRITE_SINGLE);

	for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
		if (i < (SGINT_EISA + 8))
			set_irq_chip(i, &ip22_eisa1_irq_type);
		else
			set_irq_chip(i, &ip22_eisa2_irq_type);
	}

	/* Cannot use request_irq because of kmalloc not being ready at such
	 * an early stage. Yes, I've been bitten... */
	setup_irq(SGI_EISA_IRQ, &eisa_action);
	setup_irq(SGINT_EISA + 2, &cascade_action);

	EISA_bus = 1;
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Basic EISA bus support for the SGI Indigo-2.
	3	*
	4	* (C) 2002 Pascal Dameme <[email protected]>
	5	* and Marc Zyngier <[email protected]>
	6	*
	7	* This code is released under both the GPL version 2 and BSD
	8	* licenses. Either license may be used.
	9	*
	10	* This code offers a very basic support for this EISA bus present in
	11	* the SGI Indigo-2. It currently only supports PIO (forget about DMA
	12	* for the time being). This is enough for a low-end ethernet card,
	13	* but forget about your favorite SCSI card...
	14	*
	15	* TODO :
	16	* - Fix bugs...
	17	* - Add ISA support
	18	* - Add DMA (yeah, right...).
	19	* - Fix more bugs.
	20	*/
	21
1da177e4 LT	22	#include <linux/eisa.h>
	23	#include <linux/types.h>
	24	#include <linux/init.h>
	25	#include <linux/irq.h>
	26	#include <linux/kernel_stat.h>
	27	#include <linux/signal.h>
	28	#include <linux/sched.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/delay.h>
37c8c642	31	#include <asm/io.h>
1da177e4 LT	32	#include <asm/irq.h>
	33	#include <asm/mipsregs.h>
	34	#include <asm/addrspace.h>
	35	#include <asm/processor.h>
	36	#include <asm/sgi/ioc.h>
	37	#include <asm/sgi/mc.h>
	38	#include <asm/sgi/ip22.h>
	39
37c8c642 TS	40	/* I2 has four EISA slots. */
37c8c642 TS	41	#define IP22_EISA_MAX_SLOTS 4
1da177e4 LT	42	#define EISA_MAX_IRQ 16
1da177e4 LT	43
37c8c642 TS	44	#define EIU_MODE_REG 0x0001ffc0
	45	#define EIU_STAT_REG 0x0001ffc4
	46	#define EIU_PREMPT_REG 0x0001ffc8
	47	#define EIU_QUIET_REG 0x0001ffcc
	48	#define EIU_INTRPT_ACK 0x00010004
	49
	50	static char __init *decode_eisa_sig(unsigned long addr)
1da177e4	51	{
37c8c642 TS	52	static char sig_str[EISA_SIG_LEN];
	53	u8 sig[4];
	54	u16 rev;
	55	int i;
	56
	57	for (i = 0; i < 4; i++) {
	58	sig[i] = inb (addr + i);
1da177e4	59
37c8c642 TS	60	if (!i && (sig[0] & 0x80))
	61	return NULL;
	62	}
1da177e4 LT	63
	64	sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
	65	sig_str[1] = (((sig[0] & 3) << 3) \| (sig[1] >> 5)) + ('A' - 1);
	66	sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
	67	rev = (sig[2] << 8) \| sig[3];
	68	sprintf(sig_str + 3, "%04X", rev);
	69
	70	return sig_str;
	71	}
	72
937a8015	73	static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
1da177e4 LT	74	{
	75	u8 eisa_irq;
	76	u8 dma1, dma2;
	77
37c8c642 TS	78	eisa_irq = inb(EIU_INTRPT_ACK);
	79	dma1 = inb(EISA_DMA1_STATUS);
	80	dma2 = inb(EISA_DMA2_STATUS);
1da177e4	81
37c8c642	82	if (eisa_irq < EISA_MAX_IRQ) {
937a8015	83	do_IRQ(eisa_irq);
37c8c642 TS	84	return IRQ_HANDLED;
	85	}
	86
	87	/* Oops, Bad Stuff Happened... */
	88	printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
	89
	90	outb(0x20, EISA_INT2_CTRL);
	91	outb(0x20, EISA_INT1_CTRL);
937a8015	92
37c8c642	93	return IRQ_NONE;
1da177e4 LT	94	}
	95
	96	static void enable_eisa1_irq(unsigned int irq)
	97	{
1da177e4 LT	98	u8 mask;
1da177e4 LT	99
37c8c642	100	mask = inb(EISA_INT1_MASK);
1da177e4	101	mask &= ~((u8) (1 << irq));
37c8c642	102	outb(mask, EISA_INT1_MASK);
1da177e4 LT	103	}
	104
	105	static unsigned int startup_eisa1_irq(unsigned int irq)
	106	{
	107	u8 edge;
	108
	109	/* Only use edge interrupts for EISA */
	110
37c8c642	111	edge = inb(EISA_INT1_EDGE_LEVEL);
1da177e4	112	edge &= ~((u8) (1 << irq));
37c8c642	113	outb(edge, EISA_INT1_EDGE_LEVEL);
1da177e4 LT	114
	115	enable_eisa1_irq(irq);
	116	return 0;
	117	}
	118
	119	static void disable_eisa1_irq(unsigned int irq)
	120	{
	121	u8 mask;
	122
37c8c642	123	mask = inb(EISA_INT1_MASK);
1da177e4	124	mask \|= ((u8) (1 << irq));
37c8c642	125	outb(mask, EISA_INT1_MASK);
1da177e4 LT	126	}
1da177e4 LT	127
1da177e4 LT	128	static void mask_and_ack_eisa1_irq(unsigned int irq)
	129	{
	130	disable_eisa1_irq(irq);
	131
37c8c642	132	outb(0x20, EISA_INT1_CTRL);
1da177e4 LT	133	}
	134
	135	static void end_eisa1_irq(unsigned int irq)
	136	{
	137	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	138	enable_eisa1_irq(irq);
	139	}
	140
94dee171	141	static struct irq_chip ip22_eisa1_irq_type = {
1da177e4 LT	142	.typename = "IP22 EISA",
1da177e4 LT	143	.startup = startup_eisa1_irq,
1da177e4	144	.ack = mask_and_ack_eisa1_irq,
1603b5ac AN	145	.mask = disable_eisa1_irq,
	146	.mask_ack = mask_and_ack_eisa1_irq,
	147	.unmask = enable_eisa1_irq,
1da177e4 LT	148	.end = end_eisa1_irq,
	149	};
	150
	151	static void enable_eisa2_irq(unsigned int irq)
	152	{
1da177e4 LT	153	u8 mask;
1da177e4 LT	154
37c8c642	155	mask = inb(EISA_INT2_MASK);
1da177e4	156	mask &= ~((u8) (1 << (irq - 8)));
37c8c642	157	outb(mask, EISA_INT2_MASK);
1da177e4 LT	158	}
	159
	160	static unsigned int startup_eisa2_irq(unsigned int irq)
	161	{
	162	u8 edge;
	163
	164	/* Only use edge interrupts for EISA */
	165
37c8c642	166	edge = inb(EISA_INT2_EDGE_LEVEL);
1da177e4	167	edge &= ~((u8) (1 << (irq - 8)));
37c8c642	168	outb(edge, EISA_INT2_EDGE_LEVEL);
1da177e4 LT	169
	170	enable_eisa2_irq(irq);
	171	return 0;
	172	}
	173
	174	static void disable_eisa2_irq(unsigned int irq)
	175	{
	176	u8 mask;
	177
37c8c642	178	mask = inb(EISA_INT2_MASK);
1da177e4	179	mask \|= ((u8) (1 << (irq - 8)));
37c8c642	180	outb(mask, EISA_INT2_MASK);
1da177e4 LT	181	}
1da177e4 LT	182
1da177e4 LT	183	static void mask_and_ack_eisa2_irq(unsigned int irq)
	184	{
	185	disable_eisa2_irq(irq);
	186
37c8c642	187	outb(0x20, EISA_INT2_CTRL);
1da177e4 LT	188	}
	189
	190	static void end_eisa2_irq(unsigned int irq)
	191	{
	192	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	193	enable_eisa2_irq(irq);
	194	}
	195
94dee171	196	static struct irq_chip ip22_eisa2_irq_type = {
1da177e4 LT	197	.typename = "IP22 EISA",
1da177e4 LT	198	.startup = startup_eisa2_irq,
1da177e4	199	.ack = mask_and_ack_eisa2_irq,
1603b5ac AN	200	.mask = disable_eisa2_irq,
	201	.mask_ack = mask_and_ack_eisa2_irq,
	202	.unmask = enable_eisa2_irq,
1da177e4 LT	203	.end = end_eisa2_irq,
	204	};
	205
	206	static struct irqaction eisa_action = {
	207	.handler = ip22_eisa_intr,
	208	.name = "EISA",
	209	};
	210
	211	static struct irqaction cascade_action = {
	212	.handler = no_action,
	213	.name = "EISA cascade",
	214	};
	215
	216	int __init ip22_eisa_init(void)
	217	{
	218	int i, c;
	219	char *str;
42a3b4f2	220
1da177e4 LT	221	if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
	222	printk(KERN_INFO "EISA: bus not present.\n");
	223	return 1;
	224	}
	225
	226	printk(KERN_INFO "EISA: Probing bus...\n");
37c8c642 TS	227	for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
37c8c642 TS	228	if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
1da177e4 LT	229	printk(KERN_INFO "EISA: slot %d : %s detected.\n",
	230	i, str);
	231	c++;
	232	}
	233	}
	234	printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
	235	#ifdef CONFIG_ISA
	236	printk(KERN_INFO "ISA support compiled in.\n");
	237	#endif
	238
	239	/* Warning : BlackMagicAhead(tm).
	240	Please wave your favorite dead chicken over the busses */
	241
	242	/* First say hello to the EIU */
37c8c642 TS	243	outl(0x0000FFFF, EIU_PREMPT_REG);
	244	outl(1, EIU_QUIET_REG);
	245	outl(0x40f3c07F, EIU_MODE_REG);
1da177e4 LT	246
1da177e4 LT	247	/* Now be nice to the EISA chipset */
37c8c642 TS	248	outb(1, EISA_EXT_NMI_RESET_CTRL);
	249	udelay(50); /* Wait long enough for the dust to settle */
	250	outb(0, EISA_EXT_NMI_RESET_CTRL);
	251	outb(0x11, EISA_INT1_CTRL);
	252	outb(0x11, EISA_INT2_CTRL);
	253	outb(0, EISA_INT1_MASK);
	254	outb(8, EISA_INT2_MASK);
	255	outb(4, EISA_INT1_MASK);
	256	outb(2, EISA_INT2_MASK);
	257	outb(1, EISA_INT1_MASK);
	258	outb(1, EISA_INT2_MASK);
	259	outb(0xfb, EISA_INT1_MASK);
	260	outb(0xff, EISA_INT2_MASK);
	261	outb(0, EISA_DMA2_WRITE_SINGLE);
1da177e4 LT	262
1da177e4 LT	263	for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
1da177e4	264	if (i < (SGINT_EISA + 8))
1603b5ac	265	set_irq_chip(i, &ip22_eisa1_irq_type);
1da177e4	266	else
1603b5ac	267	set_irq_chip(i, &ip22_eisa2_irq_type);
1da177e4 LT	268	}
	269
	270	/* Cannot use request_irq because of kmalloc not being ready at such
	271	* an early stage. Yes, I've been bitten... */
	272	setup_irq(SGI_EISA_IRQ, &eisa_action);
	273	setup_irq(SGINT_EISA + 2, &cascade_action);
	274
	275	EISA_bus = 1;
	276	return 0;
	277	}