[linux.git] / arch / arm / mach-imx / clock-imx31.c

/*
 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2008 by Sascha Hauer <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clkdev.h>

#include <asm/div64.h>

#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/mx31.h>
#include <mach/common.h>

#include "crmregs-imx31.h"

#define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */

static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
{
	u32 min_pre, temp_pre, old_err, err;

	if (div >= 512) {
		*pre = 8;
		*post = 64;
	} else if (div >= 64) {
		min_pre = (div - 1) / 64 + 1;
		old_err = 8;
		for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
			err = div % temp_pre;
			if (err == 0) {
				*pre = temp_pre;
				break;
			}
			err = temp_pre - err;
			if (err < old_err) {
				old_err = err;
				*pre = temp_pre;
			}
		}
		*post = (div + *pre - 1) / *pre;
	} else if (div <= 8) {
		*pre = div;
		*post = 1;
	} else {
		*pre = 1;
		*post = div;
	}
}

static struct clk mcu_pll_clk;
static struct clk serial_pll_clk;
static struct clk ipg_clk;
static struct clk ckih_clk;

static int cgr_enable(struct clk *clk)
{
	u32 reg;

	if (!clk->enable_reg)
		return 0;

	reg = __raw_readl(clk->enable_reg);
	reg |= 3 << clk->enable_shift;
	__raw_writel(reg, clk->enable_reg);

	return 0;
}

static void cgr_disable(struct clk *clk)
{
	u32 reg;

	if (!clk->enable_reg)
		return;

	reg = __raw_readl(clk->enable_reg);
	reg &= ~(3 << clk->enable_shift);

	/* special case for EMI clock */
	if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
		reg |= (1 << clk->enable_shift);

	__raw_writel(reg, clk->enable_reg);
}

static unsigned long pll_ref_get_rate(void)
{
	unsigned long ccmr;
	unsigned int prcs;

	ccmr = __raw_readl(MXC_CCM_CCMR);
	prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
	if (prcs == 0x1)
		return CKIL_CLK_FREQ * 1024;
	else
		return clk_get_rate(&ckih_clk);
}

static unsigned long usb_pll_get_rate(struct clk *clk)
{
	unsigned long reg;

	reg = __raw_readl(MXC_CCM_UPCTL);

	return mxc_decode_pll(reg, pll_ref_get_rate());
}

static unsigned long serial_pll_get_rate(struct clk *clk)
{
	unsigned long reg;

	reg = __raw_readl(MXC_CCM_SRPCTL);

	return mxc_decode_pll(reg, pll_ref_get_rate());
}

static unsigned long mcu_pll_get_rate(struct clk *clk)
{
	unsigned long reg, ccmr;

	ccmr = __raw_readl(MXC_CCM_CCMR);

	if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
		return clk_get_rate(&ckih_clk);

	reg = __raw_readl(MXC_CCM_MPCTL);

	return mxc_decode_pll(reg, pll_ref_get_rate());
}

static int usb_pll_enable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(MXC_CCM_CCMR);
	reg |= MXC_CCM_CCMR_UPE;
	__raw_writel(reg, MXC_CCM_CCMR);

	/* No lock bit on MX31, so using max time from spec */
	udelay(80);

	return 0;
}

static void usb_pll_disable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(MXC_CCM_CCMR);
	reg &= ~MXC_CCM_CCMR_UPE;
	__raw_writel(reg, MXC_CCM_CCMR);
}

static int serial_pll_enable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(MXC_CCM_CCMR);
	reg |= MXC_CCM_CCMR_SPE;
	__raw_writel(reg, MXC_CCM_CCMR);

	/* No lock bit on MX31, so using max time from spec */
	udelay(80);

	return 0;
}

static void serial_pll_disable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(MXC_CCM_CCMR);
	reg &= ~MXC_CCM_CCMR_SPE;
	__raw_writel(reg, MXC_CCM_CCMR);
}

#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)

static unsigned long mcu_main_get_rate(struct clk *clk)
{
	u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);

	if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
		return clk_get_rate(&serial_pll_clk);
	else
		return clk_get_rate(&mcu_pll_clk);
}

static unsigned long ahb_get_rate(struct clk *clk)
{
	unsigned long max_pdf;

	max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
		       MXC_CCM_PDR0_MAX_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (max_pdf + 1);
}

static unsigned long ipg_get_rate(struct clk *clk)
{
	unsigned long ipg_pdf;

	ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
		       MXC_CCM_PDR0_IPG_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (ipg_pdf + 1);
}

static unsigned long nfc_get_rate(struct clk *clk)
{
	unsigned long nfc_pdf;

	nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
		       MXC_CCM_PDR0_NFC_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (nfc_pdf + 1);
}

static unsigned long hsp_get_rate(struct clk *clk)
{
	unsigned long hsp_pdf;

	hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
		       MXC_CCM_PDR0_HSP_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (hsp_pdf + 1);
}

static unsigned long usb_get_rate(struct clk *clk)
{
	unsigned long usb_pdf, usb_prepdf;

	usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
		       MXC_CCM_PDR1_USB_PODF_OFFSET);
	usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
			  MXC_CCM_PDR1_USB_PRDF_OFFSET);
	return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
}

static unsigned long csi_get_rate(struct clk *clk)
{
	u32 reg, pre, post;

	reg = __raw_readl(MXC_CCM_PDR0);
	pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
	    MXC_CCM_PDR0_CSI_PRDF_OFFSET;
	pre++;
	post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
	    MXC_CCM_PDR0_CSI_PODF_OFFSET;
	post++;
	return clk_get_rate(clk->parent) / (pre * post);
}

static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
{
	u32 pre, post, parent = clk_get_rate(clk->parent);
	u32 div = parent / rate;

	if (parent % rate)
		div++;

	__calc_pre_post_dividers(div, &pre, &post);

	return parent / (pre * post);
}

static int csi_set_rate(struct clk *clk, unsigned long rate)
{
	u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);

	div = parent / rate;

	if ((parent / div) != rate)
		return -EINVAL;

	__calc_pre_post_dividers(div, &pre, &post);

	/* Set CSI clock divider */
	reg = __raw_readl(MXC_CCM_PDR0) &
	    ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
	reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
	reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
	__raw_writel(reg, MXC_CCM_PDR0);

	return 0;
}

static unsigned long ssi1_get_rate(struct clk *clk)
{
	unsigned long ssi1_pdf, ssi1_prepdf;

	ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
			MXC_CCM_PDR1_SSI1_PODF_OFFSET);
	ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
			   MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
}

static unsigned long ssi2_get_rate(struct clk *clk)
{
	unsigned long ssi2_pdf, ssi2_prepdf;

	ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
			MXC_CCM_PDR1_SSI2_PODF_OFFSET);
	ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
			   MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
}

static unsigned long firi_get_rate(struct clk *clk)
{
	unsigned long firi_pdf, firi_prepdf;

	firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
			MXC_CCM_PDR1_FIRI_PODF_OFFSET);
	firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
			   MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
	return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
}

static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
{
	u32 pre, post;
	u32 parent = clk_get_rate(clk->parent);
	u32 div = parent / rate;

	if (parent % rate)
		div++;

	__calc_pre_post_dividers(div, &pre, &post);

	return parent / (pre * post);

}

static int firi_set_rate(struct clk *clk, unsigned long rate)
{
	u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);

	div = parent / rate;

	if ((parent / div) != rate)
		return -EINVAL;

	__calc_pre_post_dividers(div, &pre, &post);

	/* Set FIRI clock divider */
	reg = __raw_readl(MXC_CCM_PDR1) &
	    ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
	reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
	reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
	__raw_writel(reg, MXC_CCM_PDR1);

	return 0;
}

static unsigned long mbx_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / 2;
}

static unsigned long mstick1_get_rate(struct clk *clk)
{
	unsigned long msti_pdf;

	msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
			MXC_CCM_PDR2_MST1_PDF_OFFSET);
	return clk_get_rate(clk->parent) / (msti_pdf + 1);
}

static unsigned long mstick2_get_rate(struct clk *clk)
{
	unsigned long msti_pdf;

	msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
			MXC_CCM_PDR2_MST2_PDF_OFFSET);
	return clk_get_rate(clk->parent) / (msti_pdf + 1);
}

static unsigned long ckih_rate;

static unsigned long clk_ckih_get_rate(struct clk *clk)
{
	return ckih_rate;
}

static unsigned long clk_ckil_get_rate(struct clk *clk)
{
	return CKIL_CLK_FREQ;
}

static struct clk ckih_clk = {
	.get_rate = clk_ckih_get_rate,
};

static struct clk mcu_pll_clk = {
	.parent = &ckih_clk,
	.get_rate = mcu_pll_get_rate,
};

static struct clk mcu_main_clk = {
	.parent = &mcu_pll_clk,
	.get_rate = mcu_main_get_rate,
};

static struct clk serial_pll_clk = {
	.parent = &ckih_clk,
	.get_rate = serial_pll_get_rate,
	.enable = serial_pll_enable,
	.disable = serial_pll_disable,
};

static struct clk usb_pll_clk = {
	.parent = &ckih_clk,
	.get_rate = usb_pll_get_rate,
	.enable = usb_pll_enable,
	.disable = usb_pll_disable,
};

static struct clk ahb_clk = {
	.parent = &mcu_main_clk,
	.get_rate = ahb_get_rate,
};

#define DEFINE_CLOCK(name, i, er, es, gr, s, p)		\
	static struct clk name = {			\
		.id		= i,			\
		.enable_reg	= er,			\
		.enable_shift	= es,			\
		.get_rate	= gr,			\
		.enable		= cgr_enable,		\
		.disable	= cgr_disable,		\
		.secondary	= s,			\
		.parent		= p,			\
	}

#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)	\
	static struct clk name = {				\
		.id		= i,				\
		.enable_reg	= er,				\
		.enable_shift	= es,				\
		.get_rate	= getsetround##_get_rate,	\
		.set_rate	= getsetround##_set_rate,	\
		.round_rate	= getsetround##_round_rate,	\
		.enable		= cgr_enable,			\
		.disable	= cgr_disable,			\
		.secondary	= s,				\
		.parent		= p,				\
	}

DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);

DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(uart2_clk,   1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(ssi1_clk,    0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
DEFINE_CLOCK(i2c1_clk,    0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(i2c2_clk,    1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);

DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
DEFINE_CLOCK(kpp_clk,     0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(ipu_clk,     0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
DEFINE_CLOCK(uart3_clk,   2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(uart4_clk,   3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(uart5_clk,   4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
DEFINE_CLOCK(owire_clk,   0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);

DEFINE_CLOCK(ssi2_clk,    1, MXC_CCM_CGR2,  0, ssi2_get_rate, NULL, &serial_pll_clk);
DEFINE_CLOCK(cspi1_clk,   0, MXC_CCM_CGR2,  2, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(cspi2_clk,   1, MXC_CCM_CGR2,  4, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(mbx_clk,     0, MXC_CCM_CGR2,  6, mbx_get_rate, NULL, &ahb_clk);
DEFINE_CLOCK(emi_clk,     0, MXC_CCM_CGR2,  8, NULL, NULL, &ahb_clk);
DEFINE_CLOCK(rtic_clk,    0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
DEFINE_CLOCK1(firi_clk,   0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);

DEFINE_CLOCK(sdma_clk2,   0, NULL,          0, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk);
DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);

#define _REGISTER_CLOCK(d, n, c) \
	{ \
		.dev_id = d, \
		.con_id = n, \
		.clk = &c, \
	},

static struct clk_lookup lookups[] = {
	_REGISTER_CLOCK(NULL, "emi", emi_clk)
	_REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
	_REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
	_REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
	_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
	_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
	_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
	_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
	_REGISTER_CLOCK(NULL, "epit", epit1_clk)
	_REGISTER_CLOCK(NULL, "epit", epit2_clk)
	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
	_REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
	_REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)
	_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
	_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
	_REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
	_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
	_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
	_REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
	/* i.mx31 has the i.mx21 type uart */
	_REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
	_REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
	_REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
	_REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
	_REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
	_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
	_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
	_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
	_REGISTER_CLOCK(NULL, "firi", firi_clk)
	_REGISTER_CLOCK(NULL, "ata", ata_clk)
	_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
	_REGISTER_CLOCK(NULL, "rng", rng_clk)
	_REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
	_REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
	_REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
	_REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
	_REGISTER_CLOCK(NULL, "scc", scc_clk)
	_REGISTER_CLOCK(NULL, "iim", iim_clk)
	_REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
	_REGISTER_CLOCK(NULL, "mbx", mbx_clk)
};

int __init mx31_clocks_init(unsigned long fref)
{
	u32 reg;

	ckih_rate = fref;

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	/* change the csi_clk parent if necessary */
	reg = __raw_readl(MXC_CCM_CCMR);
	if (!(reg & MXC_CCM_CCMR_CSCS))
		if (clk_set_parent(&csi_clk, &usb_pll_clk))
			pr_err("%s: error changing csi_clk parent\n", __func__);


	/* Turn off all possible clocks */
	__raw_writel((3 << 4), MXC_CCM_CGR0);
	__raw_writel(0, MXC_CCM_CGR1);
	__raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
		     1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
					   MX32, but still required to be set */
		     MXC_CCM_CGR2);

	/*
	 * Before turning off usb_pll make sure ipg_per_clk is generated
	 * by ipg_clk and not usb_pll.
	 */
	__raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);

	usb_pll_disable(&usb_pll_clk);

	pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));

	clk_enable(&gpt_clk);
	clk_enable(&emi_clk);
	clk_enable(&iim_clk);

	clk_enable(&serial_pll_clk);

	mx31_read_cpu_rev();

	if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
		reg = __raw_readl(MXC_CCM_PMCR1);
		/* No PLL restart on DVFS switch; enable auto EMI handshake */
		reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
		__raw_writel(reg, MXC_CCM_PMCR1);
	}

	mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
			MX31_INT_GPT);

	return 0;
}
Commit	Line	Data
df1bf4bd SH	1	/*
	2	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright (C) 2008 by Sascha Hauer <[email protected]>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
	18	*/
	19
	20	#include <linux/module.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/delay.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
	25	#include <linux/io.h>
6d803ba7	26	#include <linux/clkdev.h>
9eb2eb8c	27
9eb2eb8c SH	28	#include <asm/div64.h>
9eb2eb8c SH	29
a09e64fb	30	#include <mach/clock.h>
a2449091	31	#include <mach/hardware.h>
8db5d1a6	32	#include <mach/mx31.h>
30c730f8	33	#include <mach/common.h>
df1bf4bd	34
27ad4bf7	35	#include "crmregs-imx31.h"
df1bf4bd SH	36
	37	#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
	38
	39	static void __calc_pre_post_dividers(u32 div, u32 pre, u32 post)
	40	{
	41	u32 min_pre, temp_pre, old_err, err;
	42
	43	if (div >= 512) {
	44	*pre = 8;
	45	*post = 64;
	46	} else if (div >= 64) {
	47	min_pre = (div - 1) / 64 + 1;
	48	old_err = 8;
	49	for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
	50	err = div % temp_pre;
	51	if (err == 0) {
	52	*pre = temp_pre;
	53	break;
	54	}
	55	err = temp_pre - err;
	56	if (err < old_err) {
	57	old_err = err;
	58	*pre = temp_pre;
	59	}
	60	}
	61	post = (div + pre - 1) / *pre;
	62	} else if (div <= 8) {
	63	*pre = div;
	64	*post = 1;
	65	} else {
	66	*pre = 1;
	67	*post = div;
	68	}
	69	}
	70
	71	static struct clk mcu_pll_clk;
df1bf4bd SH	72	static struct clk serial_pll_clk;
	73	static struct clk ipg_clk;
	74	static struct clk ckih_clk;
df1bf4bd	75
9eb2eb8c	76	static int cgr_enable(struct clk *clk)
df1bf4bd SH	77	{
	78	u32 reg;
	79
9eb2eb8c SH	80	if (!clk->enable_reg)
	81	return 0;
	82
df1bf4bd SH	83	reg = __raw_readl(clk->enable_reg);
	84	reg \|= 3 << clk->enable_shift;
	85	__raw_writel(reg, clk->enable_reg);
	86
	87	return 0;
	88	}
	89
9eb2eb8c	90	static void cgr_disable(struct clk *clk)
df1bf4bd SH	91	{
	92	u32 reg;
	93
9eb2eb8c SH	94	if (!clk->enable_reg)
	95	return;
	96
df1bf4bd SH	97	reg = __raw_readl(clk->enable_reg);
df1bf4bd SH	98	reg &= ~(3 << clk->enable_shift);
9eb2eb8c SH	99
	100	/* special case for EMI clock */
	101	if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
	102	reg \|= (1 << clk->enable_shift);
	103
df1bf4bd SH	104	__raw_writel(reg, clk->enable_reg);
	105	}
	106
9eb2eb8c	107	static unsigned long pll_ref_get_rate(void)
df1bf4bd	108	{
9eb2eb8c SH	109	unsigned long ccmr;
9eb2eb8c SH	110	unsigned int prcs;
df1bf4bd	111
9eb2eb8c SH	112	ccmr = __raw_readl(MXC_CCM_CCMR);
	113	prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
	114	if (prcs == 0x1)
	115	return CKIL_CLK_FREQ * 1024;
	116	else
	117	return clk_get_rate(&ckih_clk);
df1bf4bd SH	118	}
df1bf4bd SH	119
9eb2eb8c	120	static unsigned long usb_pll_get_rate(struct clk *clk)
df1bf4bd	121	{
9eb2eb8c	122	unsigned long reg;
df1bf4bd	123
9eb2eb8c	124	reg = __raw_readl(MXC_CCM_UPCTL);
df1bf4bd	125
9eb2eb8c SH	126	return mxc_decode_pll(reg, pll_ref_get_rate());
9eb2eb8c SH	127	}
df1bf4bd	128
9eb2eb8c SH	129	static unsigned long serial_pll_get_rate(struct clk *clk)
	130	{
	131	unsigned long reg;
df1bf4bd	132
9eb2eb8c	133	reg = __raw_readl(MXC_CCM_SRPCTL);
df1bf4bd	134
9eb2eb8c	135	return mxc_decode_pll(reg, pll_ref_get_rate());
df1bf4bd SH	136	}
df1bf4bd SH	137
9eb2eb8c	138	static unsigned long mcu_pll_get_rate(struct clk *clk)
df1bf4bd	139	{
df1bf4bd	140	unsigned long reg, ccmr;
df1bf4bd SH	141
df1bf4bd SH	142	ccmr = __raw_readl(MXC_CCM_CCMR);
df1bf4bd	143
9eb2eb8c SH	144	if (!(ccmr & MXC_CCM_CCMR_MPE) \|\| (ccmr & MXC_CCM_CCMR_MDS))
	145	return clk_get_rate(&ckih_clk);
	146
	147	reg = __raw_readl(MXC_CCM_MPCTL);
	148
	149	return mxc_decode_pll(reg, pll_ref_get_rate());
df1bf4bd SH	150	}
df1bf4bd SH	151
9eb2eb8c	152	static int usb_pll_enable(struct clk *clk)
df1bf4bd SH	153	{
	154	u32 reg;
	155
	156	reg = __raw_readl(MXC_CCM_CCMR);
	157	reg \|= MXC_CCM_CCMR_UPE;
	158	__raw_writel(reg, MXC_CCM_CCMR);
	159
	160	/* No lock bit on MX31, so using max time from spec */
	161	udelay(80);
	162
	163	return 0;
	164	}
	165
9eb2eb8c	166	static void usb_pll_disable(struct clk *clk)
df1bf4bd SH	167	{
	168	u32 reg;
	169
	170	reg = __raw_readl(MXC_CCM_CCMR);
	171	reg &= ~MXC_CCM_CCMR_UPE;
	172	__raw_writel(reg, MXC_CCM_CCMR);
	173	}
	174
9eb2eb8c	175	static int serial_pll_enable(struct clk *clk)
df1bf4bd SH	176	{
	177	u32 reg;
	178
	179	reg = __raw_readl(MXC_CCM_CCMR);
	180	reg \|= MXC_CCM_CCMR_SPE;
	181	__raw_writel(reg, MXC_CCM_CCMR);
	182
	183	/* No lock bit on MX31, so using max time from spec */
	184	udelay(80);
	185
	186	return 0;
	187	}
	188
9eb2eb8c	189	static void serial_pll_disable(struct clk *clk)
df1bf4bd SH	190	{
	191	u32 reg;
	192
	193	reg = __raw_readl(MXC_CCM_CCMR);
	194	reg &= ~MXC_CCM_CCMR_SPE;
	195	__raw_writel(reg, MXC_CCM_CCMR);
	196	}
	197
	198	#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
	199	#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
	200	#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
	201
9eb2eb8c	202	static unsigned long mcu_main_get_rate(struct clk *clk)
df1bf4bd SH	203	{
	204	u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
	205
	206	if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
	207	return clk_get_rate(&serial_pll_clk);
	208	else
	209	return clk_get_rate(&mcu_pll_clk);
	210	}
	211
9eb2eb8c	212	static unsigned long ahb_get_rate(struct clk *clk)
df1bf4bd SH	213	{
	214	unsigned long max_pdf;
	215
	216	max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
	217	MXC_CCM_PDR0_MAX_PODF_OFFSET);
	218	return clk_get_rate(clk->parent) / (max_pdf + 1);
	219	}
	220
9eb2eb8c	221	static unsigned long ipg_get_rate(struct clk *clk)
df1bf4bd SH	222	{
	223	unsigned long ipg_pdf;
	224
	225	ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
	226	MXC_CCM_PDR0_IPG_PODF_OFFSET);
	227	return clk_get_rate(clk->parent) / (ipg_pdf + 1);
	228	}
	229
9eb2eb8c	230	static unsigned long nfc_get_rate(struct clk *clk)
df1bf4bd SH	231	{
	232	unsigned long nfc_pdf;
	233
	234	nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
	235	MXC_CCM_PDR0_NFC_PODF_OFFSET);
	236	return clk_get_rate(clk->parent) / (nfc_pdf + 1);
	237	}
	238
9eb2eb8c	239	static unsigned long hsp_get_rate(struct clk *clk)
df1bf4bd SH	240	{
	241	unsigned long hsp_pdf;
	242
	243	hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
	244	MXC_CCM_PDR0_HSP_PODF_OFFSET);
	245	return clk_get_rate(clk->parent) / (hsp_pdf + 1);
	246	}
	247
9eb2eb8c	248	static unsigned long usb_get_rate(struct clk *clk)
df1bf4bd SH	249	{
	250	unsigned long usb_pdf, usb_prepdf;
	251
	252	usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
	253	MXC_CCM_PDR1_USB_PODF_OFFSET);
	254	usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
	255	MXC_CCM_PDR1_USB_PRDF_OFFSET);
	256	return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
	257	}
	258
9eb2eb8c	259	static unsigned long csi_get_rate(struct clk *clk)
df1bf4bd SH	260	{
	261	u32 reg, pre, post;
	262
	263	reg = __raw_readl(MXC_CCM_PDR0);
	264	pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
	265	MXC_CCM_PDR0_CSI_PRDF_OFFSET;
	266	pre++;
	267	post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
	268	MXC_CCM_PDR0_CSI_PODF_OFFSET;
	269	post++;
	270	return clk_get_rate(clk->parent) / (pre * post);
	271	}
	272
9eb2eb8c	273	static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
df1bf4bd SH	274	{
	275	u32 pre, post, parent = clk_get_rate(clk->parent);
	276	u32 div = parent / rate;
	277
	278	if (parent % rate)
	279	div++;
	280
	281	__calc_pre_post_dividers(div, &pre, &post);
	282
	283	return parent / (pre * post);
	284	}
	285
9eb2eb8c	286	static int csi_set_rate(struct clk *clk, unsigned long rate)
df1bf4bd SH	287	{
	288	u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
	289
	290	div = parent / rate;
	291
	292	if ((parent / div) != rate)
	293	return -EINVAL;
	294
	295	__calc_pre_post_dividers(div, &pre, &post);
	296
	297	/* Set CSI clock divider */
	298	reg = __raw_readl(MXC_CCM_PDR0) &
	299	~(MXC_CCM_PDR0_CSI_PODF_MASK \| MXC_CCM_PDR0_CSI_PRDF_MASK);
	300	reg \|= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
	301	reg \|= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
	302	__raw_writel(reg, MXC_CCM_PDR0);
	303
	304	return 0;
	305	}
	306
9eb2eb8c	307	static unsigned long ssi1_get_rate(struct clk *clk)
df1bf4bd SH	308	{
	309	unsigned long ssi1_pdf, ssi1_prepdf;
	310
	311	ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
	312	MXC_CCM_PDR1_SSI1_PODF_OFFSET);
	313	ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
	314	MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
	315	return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
	316	}
	317
9eb2eb8c	318	static unsigned long ssi2_get_rate(struct clk *clk)
df1bf4bd SH	319	{
	320	unsigned long ssi2_pdf, ssi2_prepdf;
	321
	322	ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
	323	MXC_CCM_PDR1_SSI2_PODF_OFFSET);
	324	ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
	325	MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
	326	return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
	327	}
	328
9eb2eb8c	329	static unsigned long firi_get_rate(struct clk *clk)
df1bf4bd SH	330	{
	331	unsigned long firi_pdf, firi_prepdf;
	332
	333	firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
	334	MXC_CCM_PDR1_FIRI_PODF_OFFSET);
	335	firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
	336	MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
	337	return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
	338	}
	339
9eb2eb8c	340	static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
df1bf4bd SH	341	{
	342	u32 pre, post;
	343	u32 parent = clk_get_rate(clk->parent);
	344	u32 div = parent / rate;
	345
	346	if (parent % rate)
	347	div++;
	348
	349	__calc_pre_post_dividers(div, &pre, &post);
	350
	351	return parent / (pre * post);
	352
	353	}
	354
9eb2eb8c	355	static int firi_set_rate(struct clk *clk, unsigned long rate)
df1bf4bd SH	356	{
	357	u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
	358
	359	div = parent / rate;
	360
	361	if ((parent / div) != rate)
	362	return -EINVAL;
	363
	364	__calc_pre_post_dividers(div, &pre, &post);
	365
	366	/* Set FIRI clock divider */
	367	reg = __raw_readl(MXC_CCM_PDR1) &
	368	~(MXC_CCM_PDR1_FIRI_PODF_MASK \| MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
	369	reg \|= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
	370	reg \|= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
	371	__raw_writel(reg, MXC_CCM_PDR1);
	372
	373	return 0;
	374	}
	375
9eb2eb8c	376	static unsigned long mbx_get_rate(struct clk *clk)
df1bf4bd SH	377	{
	378	return clk_get_rate(clk->parent) / 2;
	379	}
	380
9eb2eb8c	381	static unsigned long mstick1_get_rate(struct clk *clk)
df1bf4bd SH	382	{
	383	unsigned long msti_pdf;
	384
	385	msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
	386	MXC_CCM_PDR2_MST1_PDF_OFFSET);
	387	return clk_get_rate(clk->parent) / (msti_pdf + 1);
	388	}
	389
9eb2eb8c	390	static unsigned long mstick2_get_rate(struct clk *clk)
df1bf4bd SH	391	{
	392	unsigned long msti_pdf;
	393
	394	msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
	395	MXC_CCM_PDR2_MST2_PDF_OFFSET);
	396	return clk_get_rate(clk->parent) / (msti_pdf + 1);
	397	}
	398
	399	static unsigned long ckih_rate;
	400
	401	static unsigned long clk_ckih_get_rate(struct clk *clk)
	402	{
	403	return ckih_rate;
	404	}
	405
c372a5cf DM	406	static unsigned long clk_ckil_get_rate(struct clk *clk)
	407	{
	408	return CKIL_CLK_FREQ;
	409	}
	410
df1bf4bd	411	static struct clk ckih_clk = {
df1bf4bd SH	412	.get_rate = clk_ckih_get_rate,
	413	};
	414
df1bf4bd	415	static struct clk mcu_pll_clk = {
df1bf4bd	416	.parent = &ckih_clk,
9eb2eb8c	417	.get_rate = mcu_pll_get_rate,
df1bf4bd SH	418	};
	419
	420	static struct clk mcu_main_clk = {
df1bf4bd	421	.parent = &mcu_pll_clk,
9eb2eb8c	422	.get_rate = mcu_main_get_rate,
df1bf4bd SH	423	};
	424
	425	static struct clk serial_pll_clk = {
df1bf4bd	426	.parent = &ckih_clk,
9eb2eb8c SH	427	.get_rate = serial_pll_get_rate,
	428	.enable = serial_pll_enable,
	429	.disable = serial_pll_disable,
df1bf4bd SH	430	};
	431
	432	static struct clk usb_pll_clk = {
df1bf4bd	433	.parent = &ckih_clk,
9eb2eb8c SH	434	.get_rate = usb_pll_get_rate,
	435	.enable = usb_pll_enable,
	436	.disable = usb_pll_disable,
df1bf4bd SH	437	};
	438
	439	static struct clk ahb_clk = {
df1bf4bd	440	.parent = &mcu_main_clk,
9eb2eb8c SH	441	.get_rate = ahb_get_rate,
	442	};
	443
	444	#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
	445	static struct clk name = { \
	446	.id = i, \
	447	.enable_reg = er, \
	448	.enable_shift = es, \
	449	.get_rate = gr, \
	450	.enable = cgr_enable, \
	451	.disable = cgr_disable, \
	452	.secondary = s, \
	453	.parent = p, \
	454	}
df1bf4bd	455
9eb2eb8c SH	456	#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
	457	static struct clk name = { \
	458	.id = i, \
	459	.enable_reg = er, \
	460	.enable_shift = es, \
	461	.get_rate = getsetround##_get_rate, \
	462	.set_rate = getsetround##_set_rate, \
	463	.round_rate = getsetround##_round_rate, \
	464	.enable = cgr_enable, \
	465	.disable = cgr_disable, \
	466	.secondary = s, \
	467	.parent = p, \
	468	}
df1bf4bd	469
9eb2eb8c	470	DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
6dc2d6bf	471	DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
9eb2eb8c SH	472
	473	DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
	474	DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
	475	DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
	476	DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
	477	DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
	478	DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
	479	DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
8a8d2060	480	DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
9eb2eb8c SH	481	DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
	482	DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
	483	DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
	484	DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
	485	DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
	486	DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
	487	DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
	488	DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
	489
	490	DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
	491	DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
	492	DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
0573cb5f	493	DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
6dc2d6bf	494	DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
9eb2eb8c SH	495	DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
	496	DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
	497	DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
	498	DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
	499	DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
	500	DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
	501	DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
	502	DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
	503	DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
	504
	505	DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
	506	DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
	507	DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
	508	DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
	509	DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
	510	DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
	511	DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
	512
	513	DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
	514	DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
	515	DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
	516	DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
	517	DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
	518
	519	#define _REGISTER_CLOCK(d, n, c) \
	520	{ \
	521	.dev_id = d, \
	522	.con_id = n, \
	523	.clk = &c, \
	524	},
	525
6b4bfb87	526	static struct clk_lookup lookups[] = {
9eb2eb8c	527	_REGISTER_CLOCK(NULL, "emi", emi_clk)
ab560503 UKK	528	_REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
	529	_REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
	530	_REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
9eb2eb8c SH	531	_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
9eb2eb8c SH	532	_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
2c1f4672	533	_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
9eb2eb8c SH	534	_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
	535	_REGISTER_CLOCK(NULL, "epit", epit1_clk)
	536	_REGISTER_CLOCK(NULL, "epit", epit2_clk)
	537	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
	538	_REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
	539	_REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
	540	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)
6558f985 SH	541	_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
	542	_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
	543	_REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
	544	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
	545	_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
	546	_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
9eb2eb8c SH	547	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
9eb2eb8c SH	548	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
b71df97a	549	_REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
fe6b540a SG	550	/* i.mx31 has the i.mx21 type uart */
	551	_REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
	552	_REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
	553	_REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
	554	_REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
	555	_REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
9eb2eb8c SH	556	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
	557	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
	558	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
	559	_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
	560	_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
	561	_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
74b2a70e SH	562	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
74b2a70e SH	563	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
9eb2eb8c SH	564	_REGISTER_CLOCK(NULL, "firi", firi_clk)
	565	_REGISTER_CLOCK(NULL, "ata", ata_clk)
	566	_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
	567	_REGISTER_CLOCK(NULL, "rng", rng_clk)
62550cd7	568	_REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
9eb2eb8c SH	569	_REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
	570	_REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
	571	_REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
	572	_REGISTER_CLOCK(NULL, "scc", scc_clk)
	573	_REGISTER_CLOCK(NULL, "iim", iim_clk)
	574	_REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
	575	_REGISTER_CLOCK(NULL, "mbx", mbx_clk)
df1bf4bd SH	576	};
df1bf4bd SH	577
30c730f8	578	int __init mx31_clocks_init(unsigned long fref)
df1bf4bd SH	579	{
df1bf4bd SH	580	u32 reg;
df1bf4bd SH	581
	582	ckih_rate = fref;
	583
0a0300dc	584	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
df1bf4bd	585
0573cb5f VL	586	/* change the csi_clk parent if necessary */
	587	reg = __raw_readl(MXC_CCM_CCMR);
	588	if (!(reg & MXC_CCM_CCMR_CSCS))
	589	if (clk_set_parent(&csi_clk, &usb_pll_clk))
	590	pr_err("%s: error changing csi_clk parent\n", __func__);
	591
	592
df1bf4bd	593	/* Turn off all possible clocks */
9eb2eb8c	594	__raw_writel((3 << 4), MXC_CCM_CGR0);
df1bf4bd	595	__raw_writel(0, MXC_CCM_CGR1);
9eb2eb8c	596	__raw_writel((3 << 8) \| (3 << 14) \| (3 << 16)\|
df1bf4bd SH	597	1 << 27 \| 1 << 28, /* Bit 27 and 28 are not defined for
	598	MX32, but still required to be set */
	599	MXC_CCM_CGR2);
	600
92ab0a50 AP	601	/*
	602	* Before turning off usb_pll make sure ipg_per_clk is generated
	603	* by ipg_clk and not usb_pll.
	604	*/
	605	__raw_writel(__raw_readl(MXC_CCM_CCMR) \| (1 << 24), MXC_CCM_CCMR);
	606
9eb2eb8c	607	usb_pll_disable(&usb_pll_clk);
df1bf4bd SH	608
	609	pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
	610
	611	clk_enable(&gpt_clk);
	612	clk_enable(&emi_clk);
	613	clk_enable(&iim_clk);
	614
	615	clk_enable(&serial_pll_clk);
	616
52939c03 DM	617	mx31_read_cpu_rev();
52939c03 DM	618
9ab4650f	619	if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
df1bf4bd SH	620	reg = __raw_readl(MXC_CCM_PMCR1);
	621	/* No PLL restart on DVFS switch; enable auto EMI handshake */
	622	reg \|= MXC_CCM_PMCR1_PLLRDIS \| MXC_CCM_PMCR1_EMIRQ_EN;
	623	__raw_writel(reg, MXC_CCM_PMCR1);
	624	}
	625
1273e768 UKK	626	mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
1273e768 UKK	627	MX31_INT_GPT);
30c730f8	628
df1bf4bd SH	629	return 0;
df1bf4bd SH	630	}