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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <[email protected]> | |
7 | * Copyright (C) 2000 Goutham Rao <[email protected]> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <[email protected]> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
17e5ad6c | 21 | #include <linux/dma-mapping.h> |
1da177e4 LT |
22 | #include <linux/mm.h> |
23 | #include <linux/module.h> | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
1da177e4 LT |
31 | |
32 | #include <asm/io.h> | |
1da177e4 | 33 | #include <asm/dma.h> |
17e5ad6c | 34 | #include <asm/scatterlist.h> |
1da177e4 LT |
35 | |
36 | #include <linux/init.h> | |
37 | #include <linux/bootmem.h> | |
a8522509 | 38 | #include <linux/iommu-helper.h> |
1da177e4 LT |
39 | |
40 | #define OFFSET(val,align) ((unsigned long) \ | |
41 | ( (val) & ( (align) - 1))) | |
42 | ||
0b9afede AW |
43 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
44 | ||
45 | /* | |
46 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
47 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
48 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
49 | */ | |
50 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
51 | ||
de69e0f0 JL |
52 | /* |
53 | * Enumeration for sync targets | |
54 | */ | |
55 | enum dma_sync_target { | |
56 | SYNC_FOR_CPU = 0, | |
57 | SYNC_FOR_DEVICE = 1, | |
58 | }; | |
59 | ||
1da177e4 LT |
60 | int swiotlb_force; |
61 | ||
62 | /* | |
ceb5ac32 BB |
63 | * Used to do a quick range check in unmap_single and |
64 | * sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
65 | * API. |
66 | */ | |
67 | static char *io_tlb_start, *io_tlb_end; | |
68 | ||
69 | /* | |
70 | * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and | |
71 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. | |
72 | */ | |
73 | static unsigned long io_tlb_nslabs; | |
74 | ||
75 | /* | |
76 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
77 | */ | |
78 | static unsigned long io_tlb_overflow = 32*1024; | |
79 | ||
80 | void *io_tlb_overflow_buffer; | |
81 | ||
82 | /* | |
83 | * This is a free list describing the number of free entries available from | |
84 | * each index | |
85 | */ | |
86 | static unsigned int *io_tlb_list; | |
87 | static unsigned int io_tlb_index; | |
88 | ||
89 | /* | |
90 | * We need to save away the original address corresponding to a mapped entry | |
91 | * for the sync operations. | |
92 | */ | |
bc40ac66 | 93 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
94 | |
95 | /* | |
96 | * Protect the above data structures in the map and unmap calls | |
97 | */ | |
98 | static DEFINE_SPINLOCK(io_tlb_lock); | |
99 | ||
5740afdb FT |
100 | static int late_alloc; |
101 | ||
1da177e4 LT |
102 | static int __init |
103 | setup_io_tlb_npages(char *str) | |
104 | { | |
105 | if (isdigit(*str)) { | |
e8579e72 | 106 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
107 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
108 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
109 | } | |
110 | if (*str == ',') | |
111 | ++str; | |
b18485e7 | 112 | if (!strcmp(str, "force")) |
1da177e4 | 113 | swiotlb_force = 1; |
b18485e7 | 114 | |
1da177e4 LT |
115 | return 1; |
116 | } | |
117 | __setup("swiotlb=", setup_io_tlb_npages); | |
118 | /* make io_tlb_overflow tunable too? */ | |
119 | ||
02ca646e | 120 | /* Note that this doesn't work with highmem page */ |
70a7d3cc JF |
121 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
122 | volatile void *address) | |
e08e1f7a | 123 | { |
862d196b | 124 | return phys_to_dma(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
125 | } |
126 | ||
ad32e8cb | 127 | void swiotlb_print_info(void) |
2e5b2b86 | 128 | { |
ad32e8cb | 129 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
2e5b2b86 | 130 | phys_addr_t pstart, pend; |
2e5b2b86 IC |
131 | |
132 | pstart = virt_to_phys(io_tlb_start); | |
133 | pend = virt_to_phys(io_tlb_end); | |
134 | ||
2e5b2b86 IC |
135 | printk(KERN_INFO "Placing %luMB software IO TLB between %p - %p\n", |
136 | bytes >> 20, io_tlb_start, io_tlb_end); | |
70a7d3cc JF |
137 | printk(KERN_INFO "software IO TLB at phys %#llx - %#llx\n", |
138 | (unsigned long long)pstart, | |
139 | (unsigned long long)pend); | |
2e5b2b86 IC |
140 | } |
141 | ||
1da177e4 LT |
142 | /* |
143 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
17e5ad6c | 144 | * structures for the software IO TLB used to implement the DMA API. |
1da177e4 | 145 | */ |
563aaf06 | 146 | void __init |
ad32e8cb | 147 | swiotlb_init_with_default_size(size_t default_size, int verbose) |
1da177e4 | 148 | { |
563aaf06 | 149 | unsigned long i, bytes; |
1da177e4 LT |
150 | |
151 | if (!io_tlb_nslabs) { | |
e8579e72 | 152 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); |
1da177e4 LT |
153 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); |
154 | } | |
155 | ||
563aaf06 JB |
156 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
157 | ||
1da177e4 LT |
158 | /* |
159 | * Get IO TLB memory from the low pages | |
160 | */ | |
3885123d | 161 | io_tlb_start = alloc_bootmem_low_pages(bytes); |
1da177e4 LT |
162 | if (!io_tlb_start) |
163 | panic("Cannot allocate SWIOTLB buffer"); | |
563aaf06 | 164 | io_tlb_end = io_tlb_start + bytes; |
1da177e4 LT |
165 | |
166 | /* | |
167 | * Allocate and initialize the free list array. This array is used | |
168 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
169 | * between io_tlb_start and io_tlb_end. | |
170 | */ | |
171 | io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int)); | |
25667d67 | 172 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
173 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
174 | io_tlb_index = 0; | |
bc40ac66 | 175 | io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(phys_addr_t)); |
1da177e4 LT |
176 | |
177 | /* | |
178 | * Get the overflow emergency buffer | |
179 | */ | |
180 | io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow); | |
563aaf06 JB |
181 | if (!io_tlb_overflow_buffer) |
182 | panic("Cannot allocate SWIOTLB overflow buffer!\n"); | |
ad32e8cb FT |
183 | if (verbose) |
184 | swiotlb_print_info(); | |
1da177e4 LT |
185 | } |
186 | ||
563aaf06 | 187 | void __init |
ad32e8cb | 188 | swiotlb_init(int verbose) |
1da177e4 | 189 | { |
ad32e8cb | 190 | swiotlb_init_with_default_size(64 * (1<<20), verbose); /* default to 64MB */ |
1da177e4 LT |
191 | } |
192 | ||
0b9afede AW |
193 | /* |
194 | * Systems with larger DMA zones (those that don't support ISA) can | |
195 | * initialize the swiotlb later using the slab allocator if needed. | |
196 | * This should be just like above, but with some error catching. | |
197 | */ | |
198 | int | |
563aaf06 | 199 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 200 | { |
563aaf06 | 201 | unsigned long i, bytes, req_nslabs = io_tlb_nslabs; |
0b9afede AW |
202 | unsigned int order; |
203 | ||
204 | if (!io_tlb_nslabs) { | |
205 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
206 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
207 | } | |
208 | ||
209 | /* | |
210 | * Get IO TLB memory from the low pages | |
211 | */ | |
563aaf06 | 212 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 213 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 214 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
215 | |
216 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
bb52196b FT |
217 | io_tlb_start = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
218 | order); | |
0b9afede AW |
219 | if (io_tlb_start) |
220 | break; | |
221 | order--; | |
222 | } | |
223 | ||
224 | if (!io_tlb_start) | |
225 | goto cleanup1; | |
226 | ||
563aaf06 | 227 | if (order != get_order(bytes)) { |
0b9afede AW |
228 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
229 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
230 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
563aaf06 | 231 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede | 232 | } |
563aaf06 JB |
233 | io_tlb_end = io_tlb_start + bytes; |
234 | memset(io_tlb_start, 0, bytes); | |
0b9afede AW |
235 | |
236 | /* | |
237 | * Allocate and initialize the free list array. This array is used | |
238 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
239 | * between io_tlb_start and io_tlb_end. | |
240 | */ | |
241 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
242 | get_order(io_tlb_nslabs * sizeof(int))); | |
243 | if (!io_tlb_list) | |
244 | goto cleanup2; | |
245 | ||
246 | for (i = 0; i < io_tlb_nslabs; i++) | |
247 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
248 | io_tlb_index = 0; | |
249 | ||
bc40ac66 BB |
250 | io_tlb_orig_addr = (phys_addr_t *) |
251 | __get_free_pages(GFP_KERNEL, | |
252 | get_order(io_tlb_nslabs * | |
253 | sizeof(phys_addr_t))); | |
0b9afede AW |
254 | if (!io_tlb_orig_addr) |
255 | goto cleanup3; | |
256 | ||
bc40ac66 | 257 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(phys_addr_t)); |
0b9afede AW |
258 | |
259 | /* | |
260 | * Get the overflow emergency buffer | |
261 | */ | |
262 | io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
263 | get_order(io_tlb_overflow)); | |
264 | if (!io_tlb_overflow_buffer) | |
265 | goto cleanup4; | |
266 | ||
ad32e8cb | 267 | swiotlb_print_info(); |
0b9afede | 268 | |
5740afdb FT |
269 | late_alloc = 1; |
270 | ||
0b9afede AW |
271 | return 0; |
272 | ||
273 | cleanup4: | |
bc40ac66 BB |
274 | free_pages((unsigned long)io_tlb_orig_addr, |
275 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
0b9afede AW |
276 | io_tlb_orig_addr = NULL; |
277 | cleanup3: | |
25667d67 TL |
278 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
279 | sizeof(int))); | |
0b9afede | 280 | io_tlb_list = NULL; |
0b9afede | 281 | cleanup2: |
563aaf06 | 282 | io_tlb_end = NULL; |
0b9afede AW |
283 | free_pages((unsigned long)io_tlb_start, order); |
284 | io_tlb_start = NULL; | |
285 | cleanup1: | |
286 | io_tlb_nslabs = req_nslabs; | |
287 | return -ENOMEM; | |
288 | } | |
289 | ||
5740afdb FT |
290 | void __init swiotlb_free(void) |
291 | { | |
292 | if (!io_tlb_overflow_buffer) | |
293 | return; | |
294 | ||
295 | if (late_alloc) { | |
296 | free_pages((unsigned long)io_tlb_overflow_buffer, | |
297 | get_order(io_tlb_overflow)); | |
298 | free_pages((unsigned long)io_tlb_orig_addr, | |
299 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
300 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
301 | sizeof(int))); | |
302 | free_pages((unsigned long)io_tlb_start, | |
303 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); | |
304 | } else { | |
305 | free_bootmem_late(__pa(io_tlb_overflow_buffer), | |
306 | io_tlb_overflow); | |
307 | free_bootmem_late(__pa(io_tlb_orig_addr), | |
308 | io_tlb_nslabs * sizeof(phys_addr_t)); | |
309 | free_bootmem_late(__pa(io_tlb_list), | |
310 | io_tlb_nslabs * sizeof(int)); | |
311 | free_bootmem_late(__pa(io_tlb_start), | |
312 | io_tlb_nslabs << IO_TLB_SHIFT); | |
313 | } | |
314 | } | |
315 | ||
02ca646e | 316 | static int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 317 | { |
02ca646e FT |
318 | return paddr >= virt_to_phys(io_tlb_start) && |
319 | paddr < virt_to_phys(io_tlb_end); | |
640aebfe FT |
320 | } |
321 | ||
fb05a379 BB |
322 | /* |
323 | * Bounce: copy the swiotlb buffer back to the original dma location | |
324 | */ | |
325 | static void swiotlb_bounce(phys_addr_t phys, char *dma_addr, size_t size, | |
326 | enum dma_data_direction dir) | |
327 | { | |
328 | unsigned long pfn = PFN_DOWN(phys); | |
329 | ||
330 | if (PageHighMem(pfn_to_page(pfn))) { | |
331 | /* The buffer does not have a mapping. Map it in and copy */ | |
332 | unsigned int offset = phys & ~PAGE_MASK; | |
333 | char *buffer; | |
334 | unsigned int sz = 0; | |
335 | unsigned long flags; | |
336 | ||
337 | while (size) { | |
67131ad0 | 338 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
339 | |
340 | local_irq_save(flags); | |
341 | buffer = kmap_atomic(pfn_to_page(pfn), | |
342 | KM_BOUNCE_READ); | |
343 | if (dir == DMA_TO_DEVICE) | |
344 | memcpy(dma_addr, buffer + offset, sz); | |
ef9b1893 | 345 | else |
fb05a379 BB |
346 | memcpy(buffer + offset, dma_addr, sz); |
347 | kunmap_atomic(buffer, KM_BOUNCE_READ); | |
ef9b1893 | 348 | local_irq_restore(flags); |
fb05a379 BB |
349 | |
350 | size -= sz; | |
351 | pfn++; | |
352 | dma_addr += sz; | |
353 | offset = 0; | |
ef9b1893 JF |
354 | } |
355 | } else { | |
ef9b1893 | 356 | if (dir == DMA_TO_DEVICE) |
fb05a379 | 357 | memcpy(dma_addr, phys_to_virt(phys), size); |
ef9b1893 | 358 | else |
fb05a379 | 359 | memcpy(phys_to_virt(phys), dma_addr, size); |
ef9b1893 | 360 | } |
1b548f66 JF |
361 | } |
362 | ||
1da177e4 LT |
363 | /* |
364 | * Allocates bounce buffer and returns its kernel virtual address. | |
365 | */ | |
366 | static void * | |
bc40ac66 | 367 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, int dir) |
1da177e4 LT |
368 | { |
369 | unsigned long flags; | |
370 | char *dma_addr; | |
371 | unsigned int nslots, stride, index, wrap; | |
372 | int i; | |
681cc5cd FT |
373 | unsigned long start_dma_addr; |
374 | unsigned long mask; | |
375 | unsigned long offset_slots; | |
376 | unsigned long max_slots; | |
377 | ||
378 | mask = dma_get_seg_boundary(hwdev); | |
70a7d3cc | 379 | start_dma_addr = swiotlb_virt_to_bus(hwdev, io_tlb_start) & mask; |
681cc5cd FT |
380 | |
381 | offset_slots = ALIGN(start_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
382 | |
383 | /* | |
384 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
385 | */ | |
b15a3891 JB |
386 | max_slots = mask + 1 |
387 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
388 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
389 | |
390 | /* | |
391 | * For mappings greater than a page, we limit the stride (and | |
392 | * hence alignment) to a page size. | |
393 | */ | |
394 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
395 | if (size > PAGE_SIZE) | |
396 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
397 | else | |
398 | stride = 1; | |
399 | ||
34814545 | 400 | BUG_ON(!nslots); |
1da177e4 LT |
401 | |
402 | /* | |
403 | * Find suitable number of IO TLB entries size that will fit this | |
404 | * request and allocate a buffer from that IO TLB pool. | |
405 | */ | |
406 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
407 | index = ALIGN(io_tlb_index, stride); |
408 | if (index >= io_tlb_nslabs) | |
409 | index = 0; | |
410 | wrap = index; | |
411 | ||
412 | do { | |
a8522509 FT |
413 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
414 | max_slots)) { | |
b15a3891 JB |
415 | index += stride; |
416 | if (index >= io_tlb_nslabs) | |
417 | index = 0; | |
a7133a15 AM |
418 | if (index == wrap) |
419 | goto not_found; | |
420 | } | |
421 | ||
422 | /* | |
423 | * If we find a slot that indicates we have 'nslots' number of | |
424 | * contiguous buffers, we allocate the buffers from that slot | |
425 | * and mark the entries as '0' indicating unavailable. | |
426 | */ | |
427 | if (io_tlb_list[index] >= nslots) { | |
428 | int count = 0; | |
429 | ||
430 | for (i = index; i < (int) (index + nslots); i++) | |
431 | io_tlb_list[i] = 0; | |
432 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
433 | io_tlb_list[i] = ++count; | |
434 | dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); | |
1da177e4 | 435 | |
a7133a15 AM |
436 | /* |
437 | * Update the indices to avoid searching in the next | |
438 | * round. | |
439 | */ | |
440 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
441 | ? (index + nslots) : 0); | |
442 | ||
443 | goto found; | |
444 | } | |
445 | index += stride; | |
446 | if (index >= io_tlb_nslabs) | |
447 | index = 0; | |
448 | } while (index != wrap); | |
449 | ||
450 | not_found: | |
451 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
452 | return NULL; | |
453 | found: | |
1da177e4 LT |
454 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
455 | ||
456 | /* | |
457 | * Save away the mapping from the original address to the DMA address. | |
458 | * This is needed when we sync the memory. Then we sync the buffer if | |
459 | * needed. | |
460 | */ | |
bc40ac66 BB |
461 | for (i = 0; i < nslots; i++) |
462 | io_tlb_orig_addr[index+i] = phys + (i << IO_TLB_SHIFT); | |
1da177e4 | 463 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
fb05a379 | 464 | swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE); |
1da177e4 LT |
465 | |
466 | return dma_addr; | |
467 | } | |
468 | ||
469 | /* | |
470 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
471 | */ | |
472 | static void | |
7fcebbd2 | 473 | do_unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir) |
1da177e4 LT |
474 | { |
475 | unsigned long flags; | |
476 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
477 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
bc40ac66 | 478 | phys_addr_t phys = io_tlb_orig_addr[index]; |
1da177e4 LT |
479 | |
480 | /* | |
481 | * First, sync the memory before unmapping the entry | |
482 | */ | |
bc40ac66 | 483 | if (phys && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
fb05a379 | 484 | swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
485 | |
486 | /* | |
487 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 488 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
489 | * While returning the entries to the free list, we merge the entries |
490 | * with slots below and above the pool being returned. | |
491 | */ | |
492 | spin_lock_irqsave(&io_tlb_lock, flags); | |
493 | { | |
494 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
495 | io_tlb_list[index + nslots] : 0); | |
496 | /* | |
497 | * Step 1: return the slots to the free list, merging the | |
498 | * slots with superceeding slots | |
499 | */ | |
500 | for (i = index + nslots - 1; i >= index; i--) | |
501 | io_tlb_list[i] = ++count; | |
502 | /* | |
503 | * Step 2: merge the returned slots with the preceding slots, | |
504 | * if available (non zero) | |
505 | */ | |
506 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
507 | io_tlb_list[i] = ++count; | |
508 | } | |
509 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
510 | } | |
511 | ||
512 | static void | |
de69e0f0 JL |
513 | sync_single(struct device *hwdev, char *dma_addr, size_t size, |
514 | int dir, int target) | |
1da177e4 | 515 | { |
bc40ac66 BB |
516 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; |
517 | phys_addr_t phys = io_tlb_orig_addr[index]; | |
518 | ||
519 | phys += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); | |
df336d1c | 520 | |
de69e0f0 JL |
521 | switch (target) { |
522 | case SYNC_FOR_CPU: | |
523 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
fb05a379 | 524 | swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE); |
34814545 ES |
525 | else |
526 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
527 | break; |
528 | case SYNC_FOR_DEVICE: | |
529 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
fb05a379 | 530 | swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE); |
34814545 ES |
531 | else |
532 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
533 | break; |
534 | default: | |
1da177e4 | 535 | BUG(); |
de69e0f0 | 536 | } |
1da177e4 LT |
537 | } |
538 | ||
539 | void * | |
540 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 541 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 542 | { |
563aaf06 | 543 | dma_addr_t dev_addr; |
1da177e4 LT |
544 | void *ret; |
545 | int order = get_order(size); | |
284901a9 | 546 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
547 | |
548 | if (hwdev && hwdev->coherent_dma_mask) | |
549 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 550 | |
25667d67 | 551 | ret = (void *)__get_free_pages(flags, order); |
ac2b3e67 | 552 | if (ret && swiotlb_virt_to_bus(hwdev, ret) + size - 1 > dma_mask) { |
1da177e4 LT |
553 | /* |
554 | * The allocated memory isn't reachable by the device. | |
1da177e4 LT |
555 | */ |
556 | free_pages((unsigned long) ret, order); | |
557 | ret = NULL; | |
558 | } | |
559 | if (!ret) { | |
560 | /* | |
561 | * We are either out of memory or the device can't DMA | |
ceb5ac32 BB |
562 | * to GFP_DMA memory; fall back on map_single(), which |
563 | * will grab memory from the lowest available address range. | |
1da177e4 | 564 | */ |
bc40ac66 | 565 | ret = map_single(hwdev, 0, size, DMA_FROM_DEVICE); |
9dfda12b | 566 | if (!ret) |
1da177e4 | 567 | return NULL; |
1da177e4 LT |
568 | } |
569 | ||
570 | memset(ret, 0, size); | |
70a7d3cc | 571 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); |
1da177e4 LT |
572 | |
573 | /* Confirm address can be DMA'd by device */ | |
ac2b3e67 | 574 | if (dev_addr + size - 1 > dma_mask) { |
563aaf06 | 575 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", |
1e74f300 | 576 | (unsigned long long)dma_mask, |
563aaf06 | 577 | (unsigned long long)dev_addr); |
a2b89b59 FT |
578 | |
579 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
7fcebbd2 | 580 | do_unmap_single(hwdev, ret, size, DMA_TO_DEVICE); |
a2b89b59 | 581 | return NULL; |
1da177e4 LT |
582 | } |
583 | *dma_handle = dev_addr; | |
584 | return ret; | |
585 | } | |
874d6a95 | 586 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
587 | |
588 | void | |
589 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
02ca646e | 590 | dma_addr_t dev_addr) |
1da177e4 | 591 | { |
862d196b | 592 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
02ca646e | 593 | |
aa24886e | 594 | WARN_ON(irqs_disabled()); |
02ca646e FT |
595 | if (!is_swiotlb_buffer(paddr)) |
596 | free_pages((unsigned long)vaddr, get_order(size)); | |
1da177e4 LT |
597 | else |
598 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
7fcebbd2 | 599 | do_unmap_single(hwdev, vaddr, size, DMA_TO_DEVICE); |
1da177e4 | 600 | } |
874d6a95 | 601 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
602 | |
603 | static void | |
604 | swiotlb_full(struct device *dev, size_t size, int dir, int do_panic) | |
605 | { | |
606 | /* | |
607 | * Ran out of IOMMU space for this operation. This is very bad. | |
608 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 609 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
610 | * When the mapping is small enough return a static buffer to limit |
611 | * the damage, or panic when the transfer is too big. | |
612 | */ | |
563aaf06 | 613 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
94b32486 | 614 | "device %s\n", size, dev ? dev_name(dev) : "?"); |
1da177e4 | 615 | |
c7084b35 CD |
616 | if (size <= io_tlb_overflow || !do_panic) |
617 | return; | |
618 | ||
619 | if (dir == DMA_BIDIRECTIONAL) | |
620 | panic("DMA: Random memory could be DMA accessed\n"); | |
621 | if (dir == DMA_FROM_DEVICE) | |
622 | panic("DMA: Random memory could be DMA written\n"); | |
623 | if (dir == DMA_TO_DEVICE) | |
624 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
625 | } |
626 | ||
627 | /* | |
628 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 629 | * physical address to use is returned. |
1da177e4 LT |
630 | * |
631 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 632 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 633 | */ |
f98eee8e FT |
634 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
635 | unsigned long offset, size_t size, | |
636 | enum dma_data_direction dir, | |
637 | struct dma_attrs *attrs) | |
1da177e4 | 638 | { |
f98eee8e | 639 | phys_addr_t phys = page_to_phys(page) + offset; |
862d196b | 640 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 LT |
641 | void *map; |
642 | ||
34814545 | 643 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 644 | /* |
ceb5ac32 | 645 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
646 | * we can safely return the device addr and not worry about bounce |
647 | * buffering it. | |
648 | */ | |
b9394647 | 649 | if (dma_capable(dev, dev_addr, size) && !swiotlb_force) |
1da177e4 LT |
650 | return dev_addr; |
651 | ||
652 | /* | |
653 | * Oh well, have to allocate and map a bounce buffer. | |
654 | */ | |
f98eee8e | 655 | map = map_single(dev, phys, size, dir); |
1da177e4 | 656 | if (!map) { |
f98eee8e | 657 | swiotlb_full(dev, size, dir, 1); |
1da177e4 LT |
658 | map = io_tlb_overflow_buffer; |
659 | } | |
660 | ||
f98eee8e | 661 | dev_addr = swiotlb_virt_to_bus(dev, map); |
1da177e4 LT |
662 | |
663 | /* | |
664 | * Ensure that the address returned is DMA'ble | |
665 | */ | |
b9394647 | 666 | if (!dma_capable(dev, dev_addr, size)) |
1da177e4 LT |
667 | panic("map_single: bounce buffer is not DMA'ble"); |
668 | ||
669 | return dev_addr; | |
670 | } | |
f98eee8e | 671 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 672 | |
1da177e4 LT |
673 | /* |
674 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 675 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
676 | * other usages are undefined. |
677 | * | |
678 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
679 | * whatever the device wrote there. | |
680 | */ | |
7fcebbd2 BB |
681 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
682 | size_t size, int dir) | |
1da177e4 | 683 | { |
862d196b | 684 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 685 | |
34814545 | 686 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 687 | |
02ca646e FT |
688 | if (is_swiotlb_buffer(paddr)) { |
689 | do_unmap_single(hwdev, phys_to_virt(paddr), size, dir); | |
7fcebbd2 BB |
690 | return; |
691 | } | |
692 | ||
693 | if (dir != DMA_FROM_DEVICE) | |
694 | return; | |
695 | ||
02ca646e FT |
696 | /* |
697 | * phys_to_virt doesn't work with hihgmem page but we could | |
698 | * call dma_mark_clean() with hihgmem page here. However, we | |
699 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
700 | * make dma_mark_clean() take a physical address if necessary. | |
701 | */ | |
702 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
703 | } |
704 | ||
705 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
706 | size_t size, enum dma_data_direction dir, | |
707 | struct dma_attrs *attrs) | |
708 | { | |
709 | unmap_single(hwdev, dev_addr, size, dir); | |
1da177e4 | 710 | } |
f98eee8e | 711 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 712 | |
1da177e4 LT |
713 | /* |
714 | * Make physical memory consistent for a single streaming mode DMA translation | |
715 | * after a transfer. | |
716 | * | |
ceb5ac32 | 717 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
718 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
719 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
720 | * address back to the card, you must first perform a |
721 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
722 | */ | |
be6b0267 | 723 | static void |
8270f3f1 | 724 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 | 725 | size_t size, int dir, int target) |
1da177e4 | 726 | { |
862d196b | 727 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 728 | |
34814545 | 729 | BUG_ON(dir == DMA_NONE); |
380d6878 | 730 | |
02ca646e FT |
731 | if (is_swiotlb_buffer(paddr)) { |
732 | sync_single(hwdev, phys_to_virt(paddr), size, dir, target); | |
380d6878 BB |
733 | return; |
734 | } | |
735 | ||
736 | if (dir != DMA_FROM_DEVICE) | |
737 | return; | |
738 | ||
02ca646e | 739 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
740 | } |
741 | ||
8270f3f1 JL |
742 | void |
743 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 744 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 745 | { |
de69e0f0 | 746 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 747 | } |
874d6a95 | 748 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 749 | |
1da177e4 LT |
750 | void |
751 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 752 | size_t size, enum dma_data_direction dir) |
1da177e4 | 753 | { |
de69e0f0 | 754 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 755 | } |
874d6a95 | 756 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 | 757 | |
878a97cf JL |
758 | /* |
759 | * Same as above, but for a sub-range of the mapping. | |
760 | */ | |
be6b0267 | 761 | static void |
878a97cf | 762 | swiotlb_sync_single_range(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 JL |
763 | unsigned long offset, size_t size, |
764 | int dir, int target) | |
878a97cf | 765 | { |
380d6878 | 766 | swiotlb_sync_single(hwdev, dev_addr + offset, size, dir, target); |
878a97cf JL |
767 | } |
768 | ||
769 | void | |
770 | swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e FT |
771 | unsigned long offset, size_t size, |
772 | enum dma_data_direction dir) | |
878a97cf | 773 | { |
de69e0f0 JL |
774 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
775 | SYNC_FOR_CPU); | |
878a97cf | 776 | } |
874d6a95 | 777 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_cpu); |
878a97cf JL |
778 | |
779 | void | |
780 | swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e FT |
781 | unsigned long offset, size_t size, |
782 | enum dma_data_direction dir) | |
878a97cf | 783 | { |
de69e0f0 JL |
784 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
785 | SYNC_FOR_DEVICE); | |
878a97cf | 786 | } |
874d6a95 | 787 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_device); |
878a97cf | 788 | |
1da177e4 LT |
789 | /* |
790 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 791 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
792 | * interface. Here the scatter gather list elements are each tagged with the |
793 | * appropriate dma address and length. They are obtained via | |
794 | * sg_dma_{address,length}(SG). | |
795 | * | |
796 | * NOTE: An implementation may be able to use a smaller number of | |
797 | * DMA address/length pairs than there are SG table elements. | |
798 | * (for example via virtual mapping capabilities) | |
799 | * The routine returns the number of addr/length pairs actually | |
800 | * used, at most nents. | |
801 | * | |
ceb5ac32 | 802 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
803 | * same here. |
804 | */ | |
805 | int | |
309df0c5 | 806 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
160c1d8e | 807 | enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 808 | { |
dbfd49fe | 809 | struct scatterlist *sg; |
1da177e4 LT |
810 | int i; |
811 | ||
34814545 | 812 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 813 | |
dbfd49fe | 814 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 815 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 816 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 817 | |
cf56e3f2 | 818 | if (swiotlb_force || |
b9394647 | 819 | !dma_capable(hwdev, dev_addr, sg->length)) { |
bc40ac66 BB |
820 | void *map = map_single(hwdev, sg_phys(sg), |
821 | sg->length, dir); | |
7e870233 | 822 | if (!map) { |
1da177e4 LT |
823 | /* Don't panic here, we expect map_sg users |
824 | to do proper error handling. */ | |
825 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
826 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
827 | attrs); | |
dbfd49fe | 828 | sgl[0].dma_length = 0; |
1da177e4 LT |
829 | return 0; |
830 | } | |
70a7d3cc | 831 | sg->dma_address = swiotlb_virt_to_bus(hwdev, map); |
1da177e4 LT |
832 | } else |
833 | sg->dma_address = dev_addr; | |
834 | sg->dma_length = sg->length; | |
835 | } | |
836 | return nelems; | |
837 | } | |
309df0c5 AK |
838 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
839 | ||
840 | int | |
841 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
842 | int dir) | |
843 | { | |
844 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
845 | } | |
874d6a95 | 846 | EXPORT_SYMBOL(swiotlb_map_sg); |
1da177e4 LT |
847 | |
848 | /* | |
849 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 850 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
851 | */ |
852 | void | |
309df0c5 | 853 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
160c1d8e | 854 | int nelems, enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 855 | { |
dbfd49fe | 856 | struct scatterlist *sg; |
1da177e4 LT |
857 | int i; |
858 | ||
34814545 | 859 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 860 | |
7fcebbd2 BB |
861 | for_each_sg(sgl, sg, nelems, i) |
862 | unmap_single(hwdev, sg->dma_address, sg->dma_length, dir); | |
863 | ||
1da177e4 | 864 | } |
309df0c5 AK |
865 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
866 | ||
867 | void | |
868 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
869 | int dir) | |
870 | { | |
871 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
872 | } | |
874d6a95 | 873 | EXPORT_SYMBOL(swiotlb_unmap_sg); |
1da177e4 LT |
874 | |
875 | /* | |
876 | * Make physical memory consistent for a set of streaming mode DMA translations | |
877 | * after a transfer. | |
878 | * | |
879 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
880 | * and usage. | |
881 | */ | |
be6b0267 | 882 | static void |
dbfd49fe | 883 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
de69e0f0 | 884 | int nelems, int dir, int target) |
1da177e4 | 885 | { |
dbfd49fe | 886 | struct scatterlist *sg; |
1da177e4 LT |
887 | int i; |
888 | ||
380d6878 BB |
889 | for_each_sg(sgl, sg, nelems, i) |
890 | swiotlb_sync_single(hwdev, sg->dma_address, | |
de69e0f0 | 891 | sg->dma_length, dir, target); |
1da177e4 LT |
892 | } |
893 | ||
8270f3f1 JL |
894 | void |
895 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 896 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 897 | { |
de69e0f0 | 898 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 899 | } |
874d6a95 | 900 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 901 | |
1da177e4 LT |
902 | void |
903 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 904 | int nelems, enum dma_data_direction dir) |
1da177e4 | 905 | { |
de69e0f0 | 906 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 907 | } |
874d6a95 | 908 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
909 | |
910 | int | |
8d8bb39b | 911 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 912 | { |
70a7d3cc | 913 | return (dma_addr == swiotlb_virt_to_bus(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 914 | } |
874d6a95 | 915 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
916 | |
917 | /* | |
17e5ad6c | 918 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 919 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 920 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
921 | * this function. |
922 | */ | |
923 | int | |
563aaf06 | 924 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 925 | { |
70a7d3cc | 926 | return swiotlb_virt_to_bus(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 927 | } |
1da177e4 | 928 | EXPORT_SYMBOL(swiotlb_dma_supported); |