[linux.git] / drivers / ssb / driver_mipscore.c

/*
 * Sonics Silicon Backplane
 * Broadcom MIPS core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <[email protected]>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/ssb/ssb.h>

#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/time.h>

#include "ssb_private.h"


static inline u32 mips_read32(struct ssb_mipscore *mcore,
			      u16 offset)
{
	return ssb_read32(mcore->dev, offset);
}

static inline void mips_write32(struct ssb_mipscore *mcore,
				u16 offset,
				u32 value)
{
	ssb_write32(mcore->dev, offset, value);
}

static const u32 ipsflag_irq_mask[] = {
	0,
	SSB_IPSFLAG_IRQ1,
	SSB_IPSFLAG_IRQ2,
	SSB_IPSFLAG_IRQ3,
	SSB_IPSFLAG_IRQ4,
};

static const u32 ipsflag_irq_shift[] = {
	0,
	SSB_IPSFLAG_IRQ1_SHIFT,
	SSB_IPSFLAG_IRQ2_SHIFT,
	SSB_IPSFLAG_IRQ3_SHIFT,
	SSB_IPSFLAG_IRQ4_SHIFT,
};

static inline u32 ssb_irqflag(struct ssb_device *dev)
{
	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
	if (tpsflag)
		return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	else
		/* not irq supported */
		return 0x3f;
}

static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
{
	struct ssb_bus *bus = rdev->bus;
	int i;
	for (i = 0; i < bus->nr_devices; i++) {
		struct ssb_device *dev;
		dev = &(bus->devices[i]);
		if (ssb_irqflag(dev) == irqflag)
			return dev;
	}
	return NULL;
}

/* Get the MIPS IRQ assignment for a specified device.
 * If unassigned, 0 is returned.
 * If disabled, 5 is returned.
 * If not supported, 6 is returned.
 */
unsigned int ssb_mips_irq(struct ssb_device *dev)
{
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag;
	u32 ipsflag;
	u32 tmp;
	unsigned int irq;

	irqflag = ssb_irqflag(dev);
	if (irqflag == 0x3f)
		return 6;
	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	for (irq = 1; irq <= 4; irq++) {
		tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
		if (tmp == irqflag)
			break;
	}
	if (irq	== 5) {
		if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
			irq = 0;
	}

	return irq;
}

static void clear_irq(struct ssb_bus *bus, unsigned int irq)
{
	struct ssb_device *dev = bus->mipscore.dev;

	/* Clear the IRQ in the MIPScore backplane registers */
	if (irq == 0) {
		ssb_write32(dev, SSB_INTVEC, 0);
	} else {
		ssb_write32(dev, SSB_IPSFLAG,
			    ssb_read32(dev, SSB_IPSFLAG) |
			    ipsflag_irq_mask[irq]);
	}
}

static void set_irq(struct ssb_device *dev, unsigned int irq)
{
	unsigned int oldirq = ssb_mips_irq(dev);
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag = ssb_irqflag(dev);

	BUG_ON(oldirq == 6);

	dev->irq = irq + 2;

	/* clear the old irq */
	if (oldirq == 0)
		ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
	else if (oldirq != 5)
		clear_irq(bus, oldirq);

	/* assign the new one */
	if (irq == 0) {
		ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
	} else {
		u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
		if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
			u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
			struct ssb_device *olddev = find_device(dev, oldipsflag);
			if (olddev)
				set_irq(olddev, 0);
		}
		irqflag <<= ipsflag_irq_shift[irq];
		irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
		ssb_write32(mdev, SSB_IPSFLAG, irqflag);
	}
	ssb_dprintk(KERN_INFO PFX
		    "set_irq: core 0x%04x, irq %d => %d\n",
		    dev->id.coreid, oldirq+2, irq+2);
}

static void print_irq(struct ssb_device *dev, unsigned int irq)
{
	int i;
	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
	ssb_dprintk(KERN_INFO PFX
		"core 0x%04x, irq :", dev->id.coreid);
	for (i = 0; i <= 6; i++) {
		ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
	}
	ssb_dprintk("\n");
}

static void dump_irq(struct ssb_bus *bus)
{
	int i;
	for (i = 0; i < bus->nr_devices; i++) {
		struct ssb_device *dev;
		dev = &(bus->devices[i]);
		print_irq(dev, ssb_mips_irq(dev));
	}
}

static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;

	if (bus->extif.dev)
		mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
	else if (bus->chipco.dev)
		mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	else
		mcore->nr_serial_ports = 0;
}

static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;

	/* When there is no chipcommon on the bus there is 4MB flash */
	if (!bus->chipco.dev) {
		mcore->flash_buswidth = 2;
		mcore->flash_window = SSB_FLASH1;
		mcore->flash_window_size = SSB_FLASH1_SZ;
		return;
	}

	/* There is ChipCommon, so use it to read info about flash */
	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
	case SSB_CHIPCO_FLASHT_STSER:
	case SSB_CHIPCO_FLASHT_ATSER:
		pr_err("Serial flash not supported\n");
		break;
	case SSB_CHIPCO_FLASHT_PARA:
		pr_debug("Found parallel flash\n");
		mcore->flash_window = SSB_FLASH2;
		mcore->flash_window_size = SSB_FLASH2_SZ;
		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
		               & SSB_CHIPCO_CFG_DS16) == 0)
			mcore->flash_buswidth = 1;
		else
			mcore->flash_buswidth = 2;
		break;
	}
}

u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;
	u32 pll_type, n, m, rate = 0;

	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
		return ssb_pmu_get_cpu_clock(&bus->chipco);

	if (bus->extif.dev) {
		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
	} else if (bus->chipco.dev) {
		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	} else
		return 0;

	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
		rate = 200000000;
	} else {
		rate = ssb_calc_clock_rate(pll_type, n, m);
	}

	if (pll_type == SSB_PLLTYPE_6) {
		rate *= 2;
	}

	return rate;
}

void ssb_mipscore_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus;
	struct ssb_device *dev;
	unsigned long hz, ns;
	unsigned int irq, i;

	if (!mcore->dev)
		return; /* We don't have a MIPS core */

	ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");

	bus = mcore->dev->bus;
	hz = ssb_clockspeed(bus);
	if (!hz)
		hz = 100000000;
	ns = 1000000000 / hz;

	if (bus->extif.dev)
		ssb_extif_timing_init(&bus->extif, ns);
	else if (bus->chipco.dev)
		ssb_chipco_timing_init(&bus->chipco, ns);

	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
		int mips_irq;
		dev = &(bus->devices[i]);
		mips_irq = ssb_mips_irq(dev);
		if (mips_irq > 4)
			dev->irq = 0;
		else
			dev->irq = mips_irq + 2;
		if (dev->irq > 5)
			continue;
		switch (dev->id.coreid) {
		case SSB_DEV_USB11_HOST:
			/* shouldn't need a separate irq line for non-4710, most of them have a proper
			 * external usb controller on the pci */
			if ((bus->chip_id == 0x4710) && (irq <= 4)) {
				set_irq(dev, irq++);
			}
			break;
		case SSB_DEV_PCI:
		case SSB_DEV_ETHERNET:
		case SSB_DEV_ETHERNET_GBIT:
		case SSB_DEV_80211:
		case SSB_DEV_USB20_HOST:
			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
			if (irq <= 4) {
				set_irq(dev, irq++);
				break;
			}
			/* fallthrough */
		case SSB_DEV_EXTIF:
			set_irq(dev, 0);
			break;
		}
	}
	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
	dump_irq(bus);

	ssb_mips_serial_init(mcore);
	ssb_mips_flash_detect(mcore);
}
Commit	Line	Data
61e115a5 MB	1	/*
	2	* Sonics Silicon Backplane
	3	* Broadcom MIPS core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <[email protected]>
61e115a5 MB	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
	11	#include <linux/ssb/ssb.h>
	12
	13	#include <linux/serial.h>
	14	#include <linux/serial_core.h>
	15	#include <linux/serial_reg.h>
	16	#include <linux/time.h>
	17
	18	#include "ssb_private.h"
	19
	20
	21	static inline u32 mips_read32(struct ssb_mipscore *mcore,
	22	u16 offset)
	23	{
	24	return ssb_read32(mcore->dev, offset);
	25	}
	26
	27	static inline void mips_write32(struct ssb_mipscore *mcore,
	28	u16 offset,
	29	u32 value)
	30	{
	31	ssb_write32(mcore->dev, offset, value);
	32	}
	33
	34	static const u32 ipsflag_irq_mask[] = {
	35	0,
	36	SSB_IPSFLAG_IRQ1,
	37	SSB_IPSFLAG_IRQ2,
	38	SSB_IPSFLAG_IRQ3,
	39	SSB_IPSFLAG_IRQ4,
	40	};
	41
	42	static const u32 ipsflag_irq_shift[] = {
	43	0,
	44	SSB_IPSFLAG_IRQ1_SHIFT,
	45	SSB_IPSFLAG_IRQ2_SHIFT,
	46	SSB_IPSFLAG_IRQ3_SHIFT,
	47	SSB_IPSFLAG_IRQ4_SHIFT,
	48	};
	49
	50	static inline u32 ssb_irqflag(struct ssb_device *dev)
	51	{
ea4bbfd0 MC	52	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
	53	if (tpsflag)
	54	return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	55	else
	56	/* not irq supported */
	57	return 0x3f;
	58	}
	59
	60	static struct ssb_device find_device(struct ssb_device rdev, int irqflag)
	61	{
	62	struct ssb_bus *bus = rdev->bus;
	63	int i;
	64	for (i = 0; i < bus->nr_devices; i++) {
	65	struct ssb_device *dev;
	66	dev = &(bus->devices[i]);
	67	if (ssb_irqflag(dev) == irqflag)
	68	return dev;
	69	}
	70	return NULL;
61e115a5 MB	71	}
	72
	73	/* Get the MIPS IRQ assignment for a specified device.
	74	* If unassigned, 0 is returned.
ea4bbfd0 MC	75	* If disabled, 5 is returned.
ea4bbfd0 MC	76	* If not supported, 6 is returned.
61e115a5 MB	77	*/
	78	unsigned int ssb_mips_irq(struct ssb_device *dev)
	79	{
	80	struct ssb_bus *bus = dev->bus;
ea4bbfd0	81	struct ssb_device *mdev = bus->mipscore.dev;
61e115a5 MB	82	u32 irqflag;
	83	u32 ipsflag;
	84	u32 tmp;
	85	unsigned int irq;
	86
	87	irqflag = ssb_irqflag(dev);
ea4bbfd0 MC	88	if (irqflag == 0x3f)
ea4bbfd0 MC	89	return 6;
61e115a5 MB	90	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	91	for (irq = 1; irq <= 4; irq++) {
	92	tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
	93	if (tmp == irqflag)
	94	break;
	95	}
ea4bbfd0 MC	96	if (irq == 5) {
	97	if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
	98	irq = 0;
	99	}
61e115a5 MB	100
	101	return irq;
	102	}
	103
	104	static void clear_irq(struct ssb_bus *bus, unsigned int irq)
	105	{
	106	struct ssb_device *dev = bus->mipscore.dev;
	107
	108	/* Clear the IRQ in the MIPScore backplane registers */
	109	if (irq == 0) {
	110	ssb_write32(dev, SSB_INTVEC, 0);
	111	} else {
	112	ssb_write32(dev, SSB_IPSFLAG,
	113	ssb_read32(dev, SSB_IPSFLAG) \|
	114	ipsflag_irq_mask[irq]);
	115	}
	116	}
	117
	118	static void set_irq(struct ssb_device *dev, unsigned int irq)
	119	{
	120	unsigned int oldirq = ssb_mips_irq(dev);
	121	struct ssb_bus *bus = dev->bus;
	122	struct ssb_device *mdev = bus->mipscore.dev;
	123	u32 irqflag = ssb_irqflag(dev);
	124
ea4bbfd0 MC	125	BUG_ON(oldirq == 6);
ea4bbfd0 MC	126
61e115a5 MB	127	dev->irq = irq + 2;
61e115a5 MB	128
61e115a5 MB	129	/* clear the old irq */
	130	if (oldirq == 0)
	131	ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
ea4bbfd0	132	else if (oldirq != 5)
61e115a5 MB	133	clear_irq(bus, oldirq);
	134
	135	/* assign the new one */
2633da23 MB	136	if (irq == 0) {
	137	ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) \| ssb_read32(mdev, SSB_INTVEC)));
	138	} else {
ea4bbfd0 MC	139	u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
	140	if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
	141	u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
	142	struct ssb_device *olddev = find_device(dev, oldipsflag);
	143	if (olddev)
	144	set_irq(olddev, 0);
	145	}
2633da23	146	irqflag <<= ipsflag_irq_shift[irq];
ea4bbfd0	147	irqflag \|= (ipsflag & ~ipsflag_irq_mask[irq]);
2633da23 MB	148	ssb_write32(mdev, SSB_IPSFLAG, irqflag);
2633da23 MB	149	}
ea4bbfd0 MC	150	ssb_dprintk(KERN_INFO PFX
	151	"set_irq: core 0x%04x, irq %d => %d\n",
	152	dev->id.coreid, oldirq+2, irq+2);
	153	}
	154
	155	static void print_irq(struct ssb_device *dev, unsigned int irq)
	156	{
	157	int i;
	158	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
	159	ssb_dprintk(KERN_INFO PFX
	160	"core 0x%04x, irq :", dev->id.coreid);
	161	for (i = 0; i <= 6; i++) {
	162	ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
	163	}
	164	ssb_dprintk("\n");
	165	}
	166
	167	static void dump_irq(struct ssb_bus *bus)
	168	{
	169	int i;
	170	for (i = 0; i < bus->nr_devices; i++) {
	171	struct ssb_device *dev;
	172	dev = &(bus->devices[i]);
	173	print_irq(dev, ssb_mips_irq(dev));
	174	}
61e115a5 MB	175	}
	176
	177	static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
	178	{
	179	struct ssb_bus *bus = mcore->dev->bus;
	180
	181	if (bus->extif.dev)
	182	mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
	183	else if (bus->chipco.dev)
	184	mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	185	else
	186	mcore->nr_serial_ports = 0;
	187	}
	188
	189	static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
	190	{
	191	struct ssb_bus *bus = mcore->dev->bus;
	192
902d9e0f RM	193	/* When there is no chipcommon on the bus there is 4MB flash */
	194	if (!bus->chipco.dev) {
	195	mcore->flash_buswidth = 2;
	196	mcore->flash_window = SSB_FLASH1;
	197	mcore->flash_window_size = SSB_FLASH1_SZ;
	198	return;
	199	}
	200
	201	/* There is ChipCommon, so use it to read info about flash */
	202	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
	203	case SSB_CHIPCO_FLASHT_STSER:
	204	case SSB_CHIPCO_FLASHT_ATSER:
	205	pr_err("Serial flash not supported\n");
	206	break;
	207	case SSB_CHIPCO_FLASHT_PARA:
	208	pr_debug("Found parallel flash\n");
	209	mcore->flash_window = SSB_FLASH2;
	210	mcore->flash_window_size = SSB_FLASH2_SZ;
61e115a5 MB	211	if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
	212	& SSB_CHIPCO_CFG_DS16) == 0)
	213	mcore->flash_buswidth = 1;
902d9e0f RM	214	else
	215	mcore->flash_buswidth = 2;
	216	break;
61e115a5 MB	217	}
	218	}
	219
	220	u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
	221	{
	222	struct ssb_bus *bus = mcore->dev->bus;
	223	u32 pll_type, n, m, rate = 0;
	224
d486a5b4 HM	225	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
	226	return ssb_pmu_get_cpu_clock(&bus->chipco);
	227
61e115a5 MB	228	if (bus->extif.dev) {
	229	ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
	230	} else if (bus->chipco.dev) {
	231	ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	232	} else
	233	return 0;
	234
	235	if ((pll_type == SSB_PLLTYPE_5) \|\| (bus->chip_id == 0x5365)) {
	236	rate = 200000000;
	237	} else {
	238	rate = ssb_calc_clock_rate(pll_type, n, m);
	239	}
	240
	241	if (pll_type == SSB_PLLTYPE_6) {
	242	rate *= 2;
	243	}
	244
	245	return rate;
	246	}
	247
	248	void ssb_mipscore_init(struct ssb_mipscore *mcore)
	249	{
7007d00c	250	struct ssb_bus *bus;
61e115a5 MB	251	struct ssb_device *dev;
	252	unsigned long hz, ns;
	253	unsigned int irq, i;
	254
	255	if (!mcore->dev)
	256	return; /* We don't have a MIPS core */
	257
	258	ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
	259
7007d00c	260	bus = mcore->dev->bus;
61e115a5 MB	261	hz = ssb_clockspeed(bus);
	262	if (!hz)
	263	hz = 100000000;
	264	ns = 1000000000 / hz;
	265
	266	if (bus->extif.dev)
	267	ssb_extif_timing_init(&bus->extif, ns);
	268	else if (bus->chipco.dev)
	269	ssb_chipco_timing_init(&bus->chipco, ns);
	270
	271	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	272	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
ea4bbfd0	273	int mips_irq;
61e115a5	274	dev = &(bus->devices[i]);
ea4bbfd0 MC	275	mips_irq = ssb_mips_irq(dev);
	276	if (mips_irq > 4)
	277	dev->irq = 0;
	278	else
	279	dev->irq = mips_irq + 2;
	280	if (dev->irq > 5)
	281	continue;
61e115a5 MB	282	switch (dev->id.coreid) {
	283	case SSB_DEV_USB11_HOST:
	284	/* shouldn't need a separate irq line for non-4710, most of them have a proper
	285	* external usb controller on the pci */
	286	if ((bus->chip_id == 0x4710) && (irq <= 4)) {
	287	set_irq(dev, irq++);
61e115a5	288	}
ea4bbfd0	289	break;
61e115a5 MB	290	case SSB_DEV_PCI:
61e115a5 MB	291	case SSB_DEV_ETHERNET:
aab547ce	292	case SSB_DEV_ETHERNET_GBIT:
61e115a5 MB	293	case SSB_DEV_80211:
	294	case SSB_DEV_USB20_HOST:
	295	/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
	296	if (irq <= 4) {
	297	set_irq(dev, irq++);
	298	break;
	299	}
83e34f03 JF	300	/* fallthrough */
	301	case SSB_DEV_EXTIF:
	302	set_irq(dev, 0);
	303	break;
61e115a5 MB	304	}
61e115a5 MB	305	}
ea4bbfd0 MC	306	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
ea4bbfd0 MC	307	dump_irq(bus);
61e115a5 MB	308
	309	ssb_mips_serial_init(mcore);
	310	ssb_mips_flash_detect(mcore);
	311	}