[linux.git] / drivers / clk / clk-tango4.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/init.h>
#include <linux/io.h>

#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
static struct clk *clks[CLK_COUNT];
static struct clk_onecell_data clk_data = { clks, CLK_COUNT };

#define SYSCLK_DIV	0x20
#define CPUCLK_DIV	0x24
#define DIV_BYPASS	BIT(23)

/*** CLKGEN_PLL ***/
#define extract_pll_n(val)	((val >>  0) & ((1u << 7) - 1))
#define extract_pll_k(val)	((val >> 13) & ((1u << 3) - 1))
#define extract_pll_m(val)	((val >> 16) & ((1u << 3) - 1))
#define extract_pll_isel(val)	((val >> 24) & ((1u << 3) - 1))

static void __init make_pll(int idx, const char *parent, void __iomem *base)
{
	char name[8];
	u32 val, mul, div;

	sprintf(name, "pll%d", idx);
	val = readl(base + idx * 8);
	mul =  extract_pll_n(val) + 1;
	div = (extract_pll_m(val) + 1) << extract_pll_k(val);
	clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
	if (extract_pll_isel(val) != 1)
		panic("%s: input not set to XTAL_IN\n", name);
}

static void __init make_cd(int idx, void __iomem *base)
{
	char name[8];
	u32 val, mul, div;

	sprintf(name, "cd%d", idx);
	val = readl(base + idx * 8);
	mul =  1 << 27;
	div = (2 << 27) + val;
	clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
	if (val > 0xf0000000)
		panic("%s: unsupported divider %x\n", name, val);
}

static void __init tango4_clkgen_setup(struct device_node *np)
{
	struct clk **pp = clk_data.clks;
	void __iomem *base = of_iomap(np, 0);
	const char *parent = of_clk_get_parent_name(np, 0);

	if (!base)
		panic("%s: invalid address\n", np->name);

	if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
		panic("%s: unsupported cpuclk setup\n", np->name);

	if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
		panic("%s: unsupported sysclk setup\n", np->name);

	writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */

	make_pll(0, parent, base);
	make_pll(1, parent, base);
	make_pll(2, parent, base);
	make_cd(2, base + 0x80);
	make_cd(6, base + 0x80);

	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
			base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
	pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
	pp[2] = clk_register_fixed_factor(NULL,  "usb_clk", "cd2", 0, 1, 2);
	pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);

	if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
		panic("%s: clk registration failed\n", np->name);

	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
		panic("%s: clk provider registration failed\n", np->name);
}
CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
ed12dfc9 MG	2	#include <linux/kernel.h>
	3	#include <linux/clk-provider.h>
	4	#include <linux/of_address.h>
	5	#include <linux/init.h>
	6	#include <linux/io.h>
	7
fefe0535 MG	8	#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
	9	static struct clk *clks[CLK_COUNT];
	10	static struct clk_onecell_data clk_data = { clks, CLK_COUNT };
ed12dfc9	11
fefe0535 MG	12	#define SYSCLK_DIV 0x20
	13	#define CPUCLK_DIV 0x24
	14	#define DIV_BYPASS BIT(23)
ed12dfc9	15
fefe0535 MG	16	/* CLKGEN_PLL */
	17	#define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1))
	18	#define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1))
	19	#define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1))
	20	#define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1))
ed12dfc9 MG	21
	22	static void __init make_pll(int idx, const char parent, void __iomem base)
	23	{
	24	char name[8];
	25	u32 val, mul, div;
	26
	27	sprintf(name, "pll%d", idx);
fefe0535 MG	28	val = readl(base + idx * 8);
	29	mul = extract_pll_n(val) + 1;
	30	div = (extract_pll_m(val) + 1) << extract_pll_k(val);
ed12dfc9	31	clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
fefe0535 MG	32	if (extract_pll_isel(val) != 1)
fefe0535 MG	33	panic("%s: input not set to XTAL_IN\n", name);
ed12dfc9 MG	34	}
ed12dfc9 MG	35
fefe0535	36	static void __init make_cd(int idx, void __iomem *base)
ed12dfc9	37	{
fefe0535 MG	38	char name[8];
fefe0535 MG	39	u32 val, mul, div;
ed12dfc9	40
fefe0535 MG	41	sprintf(name, "cd%d", idx);
	42	val = readl(base + idx * 8);
	43	mul = 1 << 27;
	44	div = (2 << 27) + val;
	45	clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
	46	if (val > 0xf0000000)
	47	panic("%s: unsupported divider %x\n", name, val);
ed12dfc9 MG	48	}
	49
	50	static void __init tango4_clkgen_setup(struct device_node *np)
	51	{
fefe0535	52	struct clk **pp = clk_data.clks;
ed12dfc9 MG	53	void __iomem *base = of_iomap(np, 0);
	54	const char *parent = of_clk_get_parent_name(np, 0);
	55
	56	if (!base)
fefe0535 MG	57	panic("%s: invalid address\n", np->name);
	58
	59	if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
	60	panic("%s: unsupported cpuclk setup\n", np->name);
	61
	62	if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
	63	panic("%s: unsupported sysclk setup\n", np->name);
	64
	65	writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
ed12dfc9 MG	66
	67	make_pll(0, parent, base);
	68	make_pll(1, parent, base);
fefe0535 MG	69	make_pll(2, parent, base);
	70	make_cd(2, base + 0x80);
	71	make_cd(6, base + 0x80);
ed12dfc9	72
fefe0535 MG	73	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
	74	base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
	75	pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
	76	pp[2] = clk_register_fixed_factor(NULL, "usb_clk", "cd2", 0, 1, 2);
	77	pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
ed12dfc9	78
fefe0535 MG	79	if (IS_ERR(pp[0]) \|\| IS_ERR(pp[1]) \|\| IS_ERR(pp[2]) \|\| IS_ERR(pp[3]))
fefe0535 MG	80	panic("%s: clk registration failed\n", np->name);
ed12dfc9	81
fefe0535 MG	82	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
fefe0535 MG	83	panic("%s: clk provider registration failed\n", np->name);
ed12dfc9 MG	84	}
ed12dfc9 MG	85	CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);