[linux.git] / drivers / iio / dac / stm32-dac.c

// SPDX-License-Identifier: GPL-2.0
/*
 * This file is part of STM32 DAC driver
 *
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Authors: Amelie Delaunay <[email protected]>
 *	    Fabrice Gasnier <[email protected]>
 */

#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#include "stm32-dac-core.h"

#define STM32_DAC_CHANNEL_1		1
#define STM32_DAC_CHANNEL_2		2
#define STM32_DAC_IS_CHAN_1(ch)		((ch) & STM32_DAC_CHANNEL_1)

/**
 * struct stm32_dac - private data of DAC driver
 * @common:		reference to DAC common data
 */
struct stm32_dac {
	struct stm32_dac_common *common;
};

static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
{
	struct stm32_dac *dac = iio_priv(indio_dev);
	u32 en, val;
	int ret;

	ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
	if (ret < 0)
		return ret;
	if (STM32_DAC_IS_CHAN_1(channel))
		en = FIELD_GET(STM32_DAC_CR_EN1, val);
	else
		en = FIELD_GET(STM32_DAC_CR_EN2, val);

	return !!en;
}

static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
				      bool enable)
{
	struct stm32_dac *dac = iio_priv(indio_dev);
	u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
	u32 en = enable ? msk : 0;
	int ret;

	ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
	if (ret < 0) {
		dev_err(&indio_dev->dev, "%s failed\n", en ?
			"Enable" : "Disable");
		return ret;
	}

	/*
	 * When HFSEL is set, it is not allowed to write the DHRx register
	 * during 8 clock cycles after the ENx bit is set. It is not allowed
	 * to make software/hardware trigger during this period either.
	 */
	if (en && dac->common->hfsel)
		udelay(1);

	return 0;
}

static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
{
	int ret;

	if (STM32_DAC_IS_CHAN_1(channel))
		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
	else
		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);

	return ret ? ret : IIO_VAL_INT;
}

static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
{
	int ret;

	if (STM32_DAC_IS_CHAN_1(channel))
		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
	else
		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);

	return ret;
}

static int stm32_dac_read_raw(struct iio_dev *indio_dev,
			      struct iio_chan_spec const *chan,
			      int *val, int *val2, long mask)
{
	struct stm32_dac *dac = iio_priv(indio_dev);

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		return stm32_dac_get_value(dac, chan->channel, val);
	case IIO_CHAN_INFO_SCALE:
		*val = dac->common->vref_mv;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;
	default:
		return -EINVAL;
	}
}

static int stm32_dac_write_raw(struct iio_dev *indio_dev,
			       struct iio_chan_spec const *chan,
			       int val, int val2, long mask)
{
	struct stm32_dac *dac = iio_priv(indio_dev);

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		return stm32_dac_set_value(dac, chan->channel, val);
	default:
		return -EINVAL;
	}
}

static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
					unsigned reg, unsigned writeval,
					unsigned *readval)
{
	struct stm32_dac *dac = iio_priv(indio_dev);

	if (!readval)
		return regmap_write(dac->common->regmap, reg, writeval);
	else
		return regmap_read(dac->common->regmap, reg, readval);
}

static const struct iio_info stm32_dac_iio_info = {
	.read_raw = stm32_dac_read_raw,
	.write_raw = stm32_dac_write_raw,
	.debugfs_reg_access = stm32_dac_debugfs_reg_access,
};

static const char * const stm32_dac_powerdown_modes[] = {
	"three_state",
};

static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
					const struct iio_chan_spec *chan)
{
	return 0;
}

static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
					const struct iio_chan_spec *chan,
					unsigned int type)
{
	return 0;
}

static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
					uintptr_t private,
					const struct iio_chan_spec *chan,
					char *buf)
{
	int ret = stm32_dac_is_enabled(indio_dev, chan->channel);

	if (ret < 0)
		return ret;

	return sprintf(buf, "%d\n", ret ? 0 : 1);
}

static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
					 uintptr_t private,
					 const struct iio_chan_spec *chan,
					 const char *buf, size_t len)
{
	bool powerdown;
	int ret;

	ret = strtobool(buf, &powerdown);
	if (ret)
		return ret;

	ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
	if (ret)
		return ret;

	return len;
}

static const struct iio_enum stm32_dac_powerdown_mode_en = {
	.items = stm32_dac_powerdown_modes,
	.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
	.get = stm32_dac_get_powerdown_mode,
	.set = stm32_dac_set_powerdown_mode,
};

static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
	{
		.name = "powerdown",
		.read = stm32_dac_read_powerdown,
		.write = stm32_dac_write_powerdown,
		.shared = IIO_SEPARATE,
	},
	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
	IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
	{},
};

#define STM32_DAC_CHANNEL(chan, name) {			\
	.type = IIO_VOLTAGE,				\
	.indexed = 1,					\
	.output = 1,					\
	.channel = chan,				\
	.info_mask_separate =				\
		BIT(IIO_CHAN_INFO_RAW) |		\
		BIT(IIO_CHAN_INFO_SCALE),		\
	/* scan_index is always 0 as num_channels is 1 */ \
	.scan_type = {					\
		.sign = 'u',				\
		.realbits = 12,				\
		.storagebits = 16,			\
	},						\
	.datasheet_name = name,				\
	.ext_info = stm32_dac_ext_info			\
}

static const struct iio_chan_spec stm32_dac_channels[] = {
	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
};

static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
{
	struct device_node *np = indio_dev->dev.of_node;
	unsigned int i;
	u32 channel;
	int ret;

	ret = of_property_read_u32(np, "reg", &channel);
	if (ret) {
		dev_err(&indio_dev->dev, "Failed to read reg property\n");
		return ret;
	}

	for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
		if (stm32_dac_channels[i].channel == channel)
			break;
	}
	if (i >= ARRAY_SIZE(stm32_dac_channels)) {
		dev_err(&indio_dev->dev, "Invalid reg property\n");
		return -EINVAL;
	}

	indio_dev->channels = &stm32_dac_channels[i];
	/*
	 * Expose only one channel here, as they can be used independently,
	 * with separate trigger. Then separate IIO devices are instantiated
	 * to manage this.
	 */
	indio_dev->num_channels = 1;

	return 0;
};

static int stm32_dac_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct iio_dev *indio_dev;
	struct stm32_dac *dac;
	int ret;

	if (!np)
		return -ENODEV;

	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
	if (!indio_dev)
		return -ENOMEM;
	platform_set_drvdata(pdev, indio_dev);

	dac = iio_priv(indio_dev);
	dac->common = dev_get_drvdata(pdev->dev.parent);
	indio_dev->name = dev_name(&pdev->dev);
	indio_dev->dev.parent = &pdev->dev;
	indio_dev->dev.of_node = pdev->dev.of_node;
	indio_dev->info = &stm32_dac_iio_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	ret = stm32_dac_chan_of_init(indio_dev);
	if (ret < 0)
		return ret;

	return devm_iio_device_register(&pdev->dev, indio_dev);
}

static const struct of_device_id stm32_dac_of_match[] = {
	{ .compatible = "st,stm32-dac", },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_dac_of_match);

static struct platform_driver stm32_dac_driver = {
	.probe = stm32_dac_probe,
	.driver = {
		.name = "stm32-dac",
		.of_match_table = stm32_dac_of_match,
	},
};
module_platform_driver(stm32_dac_driver);

MODULE_ALIAS("platform:stm32-dac");
MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
6e93e261	1	// SPDX-License-Identifier: GPL-2.0
4d4b3052 FG	2	/*
	3	* This file is part of STM32 DAC driver
	4	*
	5	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
	6	* Authors: Amelie Delaunay <[email protected]>
	7	* Fabrice Gasnier <[email protected]>
4d4b3052 FG	8	*/
	9
	10	#include <linux/bitfield.h>
	11	#include <linux/delay.h>
	12	#include <linux/iio/iio.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16
	17	#include "stm32-dac-core.h"
	18
	19	#define STM32_DAC_CHANNEL_1 1
	20	#define STM32_DAC_CHANNEL_2 2
	21	#define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1)
	22
	23	/**
	24	* struct stm32_dac - private data of DAC driver
	25	* @common: reference to DAC common data
	26	*/
	27	struct stm32_dac {
	28	struct stm32_dac_common *common;
	29	};
	30
	31	static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
	32	{
	33	struct stm32_dac *dac = iio_priv(indio_dev);
	34	u32 en, val;
	35	int ret;
	36
	37	ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
	38	if (ret < 0)
	39	return ret;
	40	if (STM32_DAC_IS_CHAN_1(channel))
	41	en = FIELD_GET(STM32_DAC_CR_EN1, val);
	42	else
	43	en = FIELD_GET(STM32_DAC_CR_EN2, val);
	44
	45	return !!en;
	46	}
	47
	48	static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
	49	bool enable)
	50	{
	51	struct stm32_dac *dac = iio_priv(indio_dev);
	52	u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
	53	u32 en = enable ? msk : 0;
	54	int ret;
	55
	56	ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
	57	if (ret < 0) {
	58	dev_err(&indio_dev->dev, "%s failed\n", en ?
	59	"Enable" : "Disable");
	60	return ret;
	61	}
	62
	63	/*
	64	* When HFSEL is set, it is not allowed to write the DHRx register
	65	* during 8 clock cycles after the ENx bit is set. It is not allowed
	66	* to make software/hardware trigger during this period either.
	67	*/
	68	if (en && dac->common->hfsel)
	69	udelay(1);
	70
	71	return 0;
72	}
73
74	static int stm32_dac_get_value(struct stm32_dac dac, int channel, int val)
75	{
76	int ret;
77
78	if (STM32_DAC_IS_CHAN_1(channel))
79	ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
80	else
81	ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
82
83	return ret ? ret : IIO_VAL_INT;
84	}
85
86	static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
87	{
88	int ret;
89
90	if (STM32_DAC_IS_CHAN_1(channel))
91	ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
92	else
93	ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
94
95	return ret;
96	}
97
98	static int stm32_dac_read_raw(struct iio_dev *indio_dev,
99	struct iio_chan_spec const *chan,
100	int val, int val2, long mask)
101	{
102	struct stm32_dac *dac = iio_priv(indio_dev);
103
104	switch (mask) {
105	case IIO_CHAN_INFO_RAW:
106	return stm32_dac_get_value(dac, chan->channel, val);
107	case IIO_CHAN_INFO_SCALE:
108	*val = dac->common->vref_mv;
109	*val2 = chan->scan_type.realbits;
110	return IIO_VAL_FRACTIONAL_LOG2;
111	default:
112	return -EINVAL;
113	}
114	}
115
116	static int stm32_dac_write_raw(struct iio_dev *indio_dev,
117	struct iio_chan_spec const *chan,
118	int val, int val2, long mask)
119	{
120	struct stm32_dac *dac = iio_priv(indio_dev);
121
122	switch (mask) {
123	case IIO_CHAN_INFO_RAW:
124	return stm32_dac_set_value(dac, chan->channel, val);
125	default:
126	return -EINVAL;
127	}
128	}
129
130	static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
131	unsigned reg, unsigned writeval,
132	unsigned *readval)
133	{
134	struct stm32_dac *dac = iio_priv(indio_dev);
135
136	if (!readval)
137	return regmap_write(dac->common->regmap, reg, writeval);
138	else
139	return regmap_read(dac->common->regmap, reg, readval);
140	}
141
142	static const struct iio_info stm32_dac_iio_info = {
143	.read_raw = stm32_dac_read_raw,
144	.write_raw = stm32_dac_write_raw,
145	.debugfs_reg_access = stm32_dac_debugfs_reg_access,
4d4b3052 FG	146	};
	147
	148	static const char * const stm32_dac_powerdown_modes[] = {
	149	"three_state",
	150	};
	151
	152	static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
	153	const struct iio_chan_spec *chan)
	154	{
	155	return 0;
	156	}
	157
	158	static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
	159	const struct iio_chan_spec *chan,
	160	unsigned int type)
	161	{
	162	return 0;
	163	}
	164
	165	static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
	166	uintptr_t private,
	167	const struct iio_chan_spec *chan,
	168	char *buf)
	169	{
	170	int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
	171
	172	if (ret < 0)
	173	return ret;
	174
	175	return sprintf(buf, "%d\n", ret ? 0 : 1);
	176	}
	177
	178	static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
	179	uintptr_t private,
	180	const struct iio_chan_spec *chan,
	181	const char *buf, size_t len)
	182	{
	183	bool powerdown;
	184	int ret;
	185
	186	ret = strtobool(buf, &powerdown);
	187	if (ret)
	188	return ret;
	189
	190	ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
	191	if (ret)
	192	return ret;
	193
	194	return len;
	195	}
	196
	197	static const struct iio_enum stm32_dac_powerdown_mode_en = {
	198	.items = stm32_dac_powerdown_modes,
	199	.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
	200	.get = stm32_dac_get_powerdown_mode,
	201	.set = stm32_dac_set_powerdown_mode,
	202	};
	203
	204	static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
	205	{
	206	.name = "powerdown",
	207	.read = stm32_dac_read_powerdown,
	208	.write = stm32_dac_write_powerdown,
	209	.shared = IIO_SEPARATE,
210	},
211	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
212	IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
213	{},
214	};
215
216	#define STM32_DAC_CHANNEL(chan, name) { \
217	.type = IIO_VOLTAGE, \
218	.indexed = 1, \
219	.output = 1, \
220	.channel = chan, \
221	.info_mask_separate = \
222	BIT(IIO_CHAN_INFO_RAW) \| \
223	BIT(IIO_CHAN_INFO_SCALE), \
224	/* scan_index is always 0 as num_channels is 1 */ \
225	.scan_type = { \
226	.sign = 'u', \
227	.realbits = 12, \
228	.storagebits = 16, \
229	}, \
230	.datasheet_name = name, \
231	.ext_info = stm32_dac_ext_info \
232	}
233
234	static const struct iio_chan_spec stm32_dac_channels[] = {
235	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
236	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
237	};
238
239	static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
240	{
241	struct device_node *np = indio_dev->dev.of_node;
242	unsigned int i;
243	u32 channel;
244	int ret;
245
246	ret = of_property_read_u32(np, "reg", &channel);
247	if (ret) {
248	dev_err(&indio_dev->dev, "Failed to read reg property\n");
249	return ret;
250	}
251
252	for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
253	if (stm32_dac_channels[i].channel == channel)
254	break;
255	}
256	if (i >= ARRAY_SIZE(stm32_dac_channels)) {
0c1a1b6c	257	dev_err(&indio_dev->dev, "Invalid reg property\n");
4d4b3052 FG	258	return -EINVAL;
	259	}
	260
	261	indio_dev->channels = &stm32_dac_channels[i];
	262	/*
	263	* Expose only one channel here, as they can be used independently,
	264	* with separate trigger. Then separate IIO devices are instantiated
	265	* to manage this.
	266	*/
	267	indio_dev->num_channels = 1;
	268
	269	return 0;
	270	};
	271
	272	static int stm32_dac_probe(struct platform_device *pdev)
	273	{
	274	struct device_node *np = pdev->dev.of_node;
	275	struct iio_dev *indio_dev;
	276	struct stm32_dac *dac;
	277	int ret;
	278
	279	if (!np)
	280	return -ENODEV;
	281
	282	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
	283	if (!indio_dev)
	284	return -ENOMEM;
	285	platform_set_drvdata(pdev, indio_dev);
	286
	287	dac = iio_priv(indio_dev);
	288	dac->common = dev_get_drvdata(pdev->dev.parent);
	289	indio_dev->name = dev_name(&pdev->dev);
	290	indio_dev->dev.parent = &pdev->dev;
	291	indio_dev->dev.of_node = pdev->dev.of_node;
	292	indio_dev->info = &stm32_dac_iio_info;
	293	indio_dev->modes = INDIO_DIRECT_MODE;
	294
	295	ret = stm32_dac_chan_of_init(indio_dev);
	296	if (ret < 0)
	297	return ret;
	298
	299	return devm_iio_device_register(&pdev->dev, indio_dev);
	300	}
	301
	302	static const struct of_device_id stm32_dac_of_match[] = {
	303	{ .compatible = "st,stm32-dac", },
	304	{},
	305	};
	306	MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
	307
	308	static struct platform_driver stm32_dac_driver = {
	309	.probe = stm32_dac_probe,
	310	.driver = {
	311	.name = "stm32-dac",
	312	.of_match_table = stm32_dac_of_match,
	313	},
	314	};
	315	module_platform_driver(stm32_dac_driver);
	316
	317	MODULE_ALIAS("platform:stm32-dac");
	318	MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
	319	MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
	320	MODULE_LICENSE("GPL v2");