[linux.git] / drivers / iio / dac / ad5764.c

/*
 * Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
 * Digital to Analog Converters driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#define AD5764_REG_SF_NOP			0x0
#define AD5764_REG_SF_CONFIG			0x1
#define AD5764_REG_SF_CLEAR			0x4
#define AD5764_REG_SF_LOAD			0x5
#define AD5764_REG_DATA(x)			((2 << 3) | (x))
#define AD5764_REG_COARSE_GAIN(x)		((3 << 3) | (x))
#define AD5764_REG_FINE_GAIN(x)			((4 << 3) | (x))
#define AD5764_REG_OFFSET(x)			((5 << 3) | (x))

#define AD5764_NUM_CHANNELS 4

/**
 * struct ad5764_chip_info - chip specific information
 * @int_vref:	Value of the internal reference voltage in uV - 0 if external
 *		reference voltage is used
 * @channel	channel specification
*/

struct ad5764_chip_info {
	unsigned long int_vref;
	const struct iio_chan_spec *channels;
};

/**
 * struct ad5764_state - driver instance specific data
 * @spi:		spi_device
 * @chip_info:		chip info
 * @vref_reg:		vref supply regulators
 * @data:		spi transfer buffers
 */

struct ad5764_state {
	struct spi_device		*spi;
	const struct ad5764_chip_info	*chip_info;
	struct regulator_bulk_data	vref_reg[2];

	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */
	union {
		__be32 d32;
		u8 d8[4];
	} data[2] ____cacheline_aligned;
};

enum ad5764_type {
	ID_AD5744,
	ID_AD5744R,
	ID_AD5764,
	ID_AD5764R,
};

#define AD5764_CHANNEL(_chan, _bits) {				\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.output = 1,						\
	.channel = (_chan),					\
	.address = (_chan),					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
		BIT(IIO_CHAN_INFO_SCALE) |			\
		BIT(IIO_CHAN_INFO_CALIBSCALE) |			\
		BIT(IIO_CHAN_INFO_CALIBBIAS),			\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET),	\
	.scan_type = {						\
		.sign = 'u',					\
		.realbits = (_bits),				\
		.storagebits = 16,				\
		.shift = 16 - (_bits),				\
	},							\
}

#define DECLARE_AD5764_CHANNELS(_name, _bits) \
const struct iio_chan_spec _name##_channels[] = { \
	AD5764_CHANNEL(0, (_bits)), \
	AD5764_CHANNEL(1, (_bits)), \
	AD5764_CHANNEL(2, (_bits)), \
	AD5764_CHANNEL(3, (_bits)), \
};

static DECLARE_AD5764_CHANNELS(ad5764, 16);
static DECLARE_AD5764_CHANNELS(ad5744, 14);

static const struct ad5764_chip_info ad5764_chip_infos[] = {
	[ID_AD5744] = {
		.int_vref = 0,
		.channels = ad5744_channels,
	},
	[ID_AD5744R] = {
		.int_vref = 5000000,
		.channels = ad5744_channels,
	},
	[ID_AD5764] = {
		.int_vref = 0,
		.channels = ad5764_channels,
	},
	[ID_AD5764R] = {
		.int_vref = 5000000,
		.channels = ad5764_channels,
	},
};

static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
	unsigned int val)
{
	struct ad5764_state *st = iio_priv(indio_dev);
	int ret;

	mutex_lock(&indio_dev->mlock);
	st->data[0].d32 = cpu_to_be32((reg << 16) | val);

	ret = spi_write(st->spi, &st->data[0].d8[1], 3);
	mutex_unlock(&indio_dev->mlock);

	return ret;
}

static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
	unsigned int *val)
{
	struct ad5764_state *st = iio_priv(indio_dev);
	int ret;
	struct spi_transfer t[] = {
		{
			.tx_buf = &st->data[0].d8[1],
			.len = 3,
			.cs_change = 1,
		}, {
			.rx_buf = &st->data[1].d8[1],
			.len = 3,
		},
	};

	mutex_lock(&indio_dev->mlock);

	st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));

	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
	if (ret >= 0)
		*val = be32_to_cpu(st->data[1].d32) & 0xffff;

	mutex_unlock(&indio_dev->mlock);

	return ret;
}

static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
{
	switch (info) {
	case IIO_CHAN_INFO_RAW:
		return AD5764_REG_DATA(chan->address);
	case IIO_CHAN_INFO_CALIBBIAS:
		return AD5764_REG_OFFSET(chan->address);
	case IIO_CHAN_INFO_CALIBSCALE:
		return AD5764_REG_FINE_GAIN(chan->address);
	default:
		break;
	}

	return 0;
}

static int ad5764_write_raw(struct iio_dev *indio_dev,
	struct iio_chan_spec const *chan, int val, int val2, long info)
{
	const int max_val = (1 << chan->scan_type.realbits);
	unsigned int reg;

	switch (info) {
	case IIO_CHAN_INFO_RAW:
		if (val >= max_val || val < 0)
			return -EINVAL;
		val <<= chan->scan_type.shift;
		break;
	case IIO_CHAN_INFO_CALIBBIAS:
		if (val >= 128 || val < -128)
			return -EINVAL;
		break;
	case IIO_CHAN_INFO_CALIBSCALE:
		if (val >= 32 || val < -32)
			return -EINVAL;
		break;
	default:
		return -EINVAL;
	}

	reg = ad5764_chan_info_to_reg(chan, info);
	return ad5764_write(indio_dev, reg, (u16)val);
}

static int ad5764_get_channel_vref(struct ad5764_state *st,
	unsigned int channel)
{
	if (st->chip_info->int_vref)
		return st->chip_info->int_vref;
	else
		return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
}

static int ad5764_read_raw(struct iio_dev *indio_dev,
	struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
	struct ad5764_state *st = iio_priv(indio_dev);
	unsigned int reg;
	int vref;
	int ret;

	switch (info) {
	case IIO_CHAN_INFO_RAW:
		reg = AD5764_REG_DATA(chan->address);
		ret = ad5764_read(indio_dev, reg, val);
		if (ret < 0)
			return ret;
		*val >>= chan->scan_type.shift;
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_CALIBBIAS:
		reg = AD5764_REG_OFFSET(chan->address);
		ret = ad5764_read(indio_dev, reg, val);
		if (ret < 0)
			return ret;
		*val = sign_extend32(*val, 7);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_CALIBSCALE:
		reg = AD5764_REG_FINE_GAIN(chan->address);
		ret = ad5764_read(indio_dev, reg, val);
		if (ret < 0)
			return ret;
		*val = sign_extend32(*val, 5);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		/* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
		vref = ad5764_get_channel_vref(st, chan->channel);
		if (vref < 0)
			return vref;

		*val = vref * 4 / 1000;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;
	case IIO_CHAN_INFO_OFFSET:
		*val = -(1 << chan->scan_type.realbits) / 2;
		return IIO_VAL_INT;
	}

	return -EINVAL;
}

static const struct iio_info ad5764_info = {
	.read_raw = ad5764_read_raw,
	.write_raw = ad5764_write_raw,
};

static int ad5764_probe(struct spi_device *spi)
{
	enum ad5764_type type = spi_get_device_id(spi)->driver_data;
	struct iio_dev *indio_dev;
	struct ad5764_state *st;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL) {
		dev_err(&spi->dev, "Failed to allocate iio device\n");
		return -ENOMEM;
	}

	st = iio_priv(indio_dev);
	spi_set_drvdata(spi, indio_dev);

	st->spi = spi;
	st->chip_info = &ad5764_chip_infos[type];

	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad5764_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->num_channels = AD5764_NUM_CHANNELS;
	indio_dev->channels = st->chip_info->channels;

	if (st->chip_info->int_vref == 0) {
		st->vref_reg[0].supply = "vrefAB";
		st->vref_reg[1].supply = "vrefCD";

		ret = devm_regulator_bulk_get(&st->spi->dev,
			ARRAY_SIZE(st->vref_reg), st->vref_reg);
		if (ret) {
			dev_err(&spi->dev, "Failed to request vref regulators: %d\n",
				ret);
			return ret;
		}

		ret = regulator_bulk_enable(ARRAY_SIZE(st->vref_reg),
			st->vref_reg);
		if (ret) {
			dev_err(&spi->dev, "Failed to enable vref regulators: %d\n",
				ret);
			return ret;
		}
	}

	ret = iio_device_register(indio_dev);
	if (ret) {
		dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
		goto error_disable_reg;
	}

	return 0;

error_disable_reg:
	if (st->chip_info->int_vref == 0)
		regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
	return ret;
}

static int ad5764_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad5764_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);

	if (st->chip_info->int_vref == 0)
		regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);

	return 0;
}

static const struct spi_device_id ad5764_ids[] = {
	{ "ad5744", ID_AD5744 },
	{ "ad5744r", ID_AD5744R },
	{ "ad5764", ID_AD5764 },
	{ "ad5764r", ID_AD5764R },
	{ }
};
MODULE_DEVICE_TABLE(spi, ad5764_ids);

static struct spi_driver ad5764_driver = {
	.driver = {
		.name = "ad5764",
	},
	.probe = ad5764_probe,
	.remove = ad5764_remove,
	.id_table = ad5764_ids,
};
module_spi_driver(ad5764_driver);

MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5744/AD5744R/AD5764/AD5764R DAC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
68b14d7e LPC	1	/*
	2	* Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
	3	* Digital to Analog Converters driver
	4	*
	5	* Copyright 2011 Analog Devices Inc.
	6	*
	7	* Licensed under the GPL-2.
	8	*/
	9
	10	#include <linux/device.h>
	11	#include <linux/err.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/spi/spi.h>
	15	#include <linux/slab.h>
	16	#include <linux/sysfs.h>
	17	#include <linux/regulator/consumer.h>
	18
06458e27 JC	19	#include <linux/iio/iio.h>
06458e27 JC	20	#include <linux/iio/sysfs.h>
68b14d7e LPC	21
	22	#define AD5764_REG_SF_NOP 0x0
	23	#define AD5764_REG_SF_CONFIG 0x1
	24	#define AD5764_REG_SF_CLEAR 0x4
	25	#define AD5764_REG_SF_LOAD 0x5
	26	#define AD5764_REG_DATA(x) ((2 << 3) \| (x))
	27	#define AD5764_REG_COARSE_GAIN(x) ((3 << 3) \| (x))
	28	#define AD5764_REG_FINE_GAIN(x) ((4 << 3) \| (x))
	29	#define AD5764_REG_OFFSET(x) ((5 << 3) \| (x))
	30
	31	#define AD5764_NUM_CHANNELS 4
	32
	33	/**
	34	* struct ad5764_chip_info - chip specific information
	35	* @int_vref: Value of the internal reference voltage in uV - 0 if external
	36	* reference voltage is used
	37	* @channel channel specification
	38	*/
	39
	40	struct ad5764_chip_info {
	41	unsigned long int_vref;
	42	const struct iio_chan_spec *channels;
	43	};
	44
	45	/**
	46	* struct ad5764_state - driver instance specific data
	47	* @spi: spi_device
	48	* @chip_info: chip info
	49	* @vref_reg: vref supply regulators
	50	* @data: spi transfer buffers
	51	*/
	52
	53	struct ad5764_state {
	54	struct spi_device *spi;
	55	const struct ad5764_chip_info *chip_info;
	56	struct regulator_bulk_data vref_reg[2];
	57
	58	/*
	59	* DMA (thus cache coherency maintenance) requires the
	60	* transfer buffers to live in their own cache lines.
	61	*/
	62	union {
	63	__be32 d32;
	64	u8 d8[4];
	65	} data[2] ____cacheline_aligned;
	66	};
	67
	68	enum ad5764_type {
	69	ID_AD5744,
	70	ID_AD5744R,
	71	ID_AD5764,
	72	ID_AD5764R,
	73	};
	74
	75	#define AD5764_CHANNEL(_chan, _bits) { \
	76	.type = IIO_VOLTAGE, \
	77	.indexed = 1, \
	78	.output = 1, \
	79	.channel = (_chan), \
	80	.address = (_chan), \
f4d9df19 JC	81	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	82	BIT(IIO_CHAN_INFO_SCALE) \| \
	83	BIT(IIO_CHAN_INFO_CALIBSCALE) \| \
	84	BIT(IIO_CHAN_INFO_CALIBBIAS), \
	85	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET), \
560101de JC	86	.scan_type = { \
	87	.sign = 'u', \
	88	.realbits = (_bits), \
	89	.storagebits = 16, \
	90	.shift = 16 - (_bits), \
	91	}, \
68b14d7e LPC	92	}
	93
	94	#define DECLARE_AD5764_CHANNELS(_name, _bits) \
	95	const struct iio_chan_spec _name##_channels[] = { \
	96	AD5764_CHANNEL(0, (_bits)), \
	97	AD5764_CHANNEL(1, (_bits)), \
	98	AD5764_CHANNEL(2, (_bits)), \
	99	AD5764_CHANNEL(3, (_bits)), \
	100	};
	101
	102	static DECLARE_AD5764_CHANNELS(ad5764, 16);
	103	static DECLARE_AD5764_CHANNELS(ad5744, 14);
	104
	105	static const struct ad5764_chip_info ad5764_chip_infos[] = {
	106	[ID_AD5744] = {
	107	.int_vref = 0,
	108	.channels = ad5744_channels,
	109	},
	110	[ID_AD5744R] = {
	111	.int_vref = 5000000,
	112	.channels = ad5744_channels,
	113	},
	114	[ID_AD5764] = {
	115	.int_vref = 0,
	116	.channels = ad5764_channels,
	117	},
	118	[ID_AD5764R] = {
	119	.int_vref = 5000000,
	120	.channels = ad5764_channels,
	121	},
	122	};
	123
	124	static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
	125	unsigned int val)
	126	{
	127	struct ad5764_state *st = iio_priv(indio_dev);
	128	int ret;
	129
	130	mutex_lock(&indio_dev->mlock);
	131	st->data[0].d32 = cpu_to_be32((reg << 16) \| val);
	132
	133	ret = spi_write(st->spi, &st->data[0].d8[1], 3);
	134	mutex_unlock(&indio_dev->mlock);
	135
	136	return ret;
	137	}
	138
	139	static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
	140	unsigned int *val)
	141	{
	142	struct ad5764_state *st = iio_priv(indio_dev);
68b14d7e LPC	143	int ret;
	144	struct spi_transfer t[] = {
	145	{
	146	.tx_buf = &st->data[0].d8[1],
	147	.len = 3,
	148	.cs_change = 1,
	149	}, {
	150	.rx_buf = &st->data[1].d8[1],
	151	.len = 3,
	152	},
	153	};
	154
68b14d7e LPC	155	mutex_lock(&indio_dev->mlock);
	156
	157	st->data[0].d32 = cpu_to_be32((1 << 23) \| (reg << 16));
	158
14543a00	159	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
68b14d7e LPC	160	if (ret >= 0)
	161	*val = be32_to_cpu(st->data[1].d32) & 0xffff;
	162
	163	mutex_unlock(&indio_dev->mlock);
	164
	165	return ret;
	166	}
	167
	168	static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
	169	{
	170	switch (info) {
67464a54	171	case IIO_CHAN_INFO_RAW:
68b14d7e LPC	172	return AD5764_REG_DATA(chan->address);
	173	case IIO_CHAN_INFO_CALIBBIAS:
	174	return AD5764_REG_OFFSET(chan->address);
	175	case IIO_CHAN_INFO_CALIBSCALE:
	176	return AD5764_REG_FINE_GAIN(chan->address);
	177	default:
	178	break;
	179	}
	180
	181	return 0;
	182	}
	183
	184	static int ad5764_write_raw(struct iio_dev *indio_dev,
	185	struct iio_chan_spec const *chan, int val, int val2, long info)
	186	{
	187	const int max_val = (1 << chan->scan_type.realbits);
	188	unsigned int reg;
	189
	190	switch (info) {
09f4eb40	191	case IIO_CHAN_INFO_RAW:
68b14d7e LPC	192	if (val >= max_val \|\| val < 0)
	193	return -EINVAL;
	194	val <<= chan->scan_type.shift;
	195	break;
	196	case IIO_CHAN_INFO_CALIBBIAS:
	197	if (val >= 128 \|\| val < -128)
	198	return -EINVAL;
	199	break;
	200	case IIO_CHAN_INFO_CALIBSCALE:
	201	if (val >= 32 \|\| val < -32)
	202	return -EINVAL;
	203	break;
	204	default:
	205	return -EINVAL;
	206	}
	207
	208	reg = ad5764_chan_info_to_reg(chan, info);
	209	return ad5764_write(indio_dev, reg, (u16)val);
	210	}
	211
	212	static int ad5764_get_channel_vref(struct ad5764_state *st,
	213	unsigned int channel)
	214	{
	215	if (st->chip_info->int_vref)
	216	return st->chip_info->int_vref;
	217	else
	218	return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
	219	}
	220
	221	static int ad5764_read_raw(struct iio_dev *indio_dev,
	222	struct iio_chan_spec const chan, int val, int *val2, long info)
	223	{
	224	struct ad5764_state *st = iio_priv(indio_dev);
68b14d7e LPC	225	unsigned int reg;
	226	int vref;
	227	int ret;
	228
	229	switch (info) {
09f4eb40	230	case IIO_CHAN_INFO_RAW:
68b14d7e LPC	231	reg = AD5764_REG_DATA(chan->address);
	232	ret = ad5764_read(indio_dev, reg, val);
	233	if (ret < 0)
	234	return ret;
	235	*val >>= chan->scan_type.shift;
	236	return IIO_VAL_INT;
	237	case IIO_CHAN_INFO_CALIBBIAS:
	238	reg = AD5764_REG_OFFSET(chan->address);
	239	ret = ad5764_read(indio_dev, reg, val);
	240	if (ret < 0)
	241	return ret;
	242	val = sign_extend32(val, 7);
	243	return IIO_VAL_INT;
	244	case IIO_CHAN_INFO_CALIBSCALE:
	245	reg = AD5764_REG_FINE_GAIN(chan->address);
	246	ret = ad5764_read(indio_dev, reg, val);
	247	if (ret < 0)
	248	return ret;
	249	val = sign_extend32(val, 5);
	250	return IIO_VAL_INT;
	251	case IIO_CHAN_INFO_SCALE:
3f83dae8	252	/* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
68b14d7e LPC	253	vref = ad5764_get_channel_vref(st, chan->channel);
	254	if (vref < 0)
	255	return vref;
	256
3f83dae8 LPC	257	val = vref 4 / 1000;
	258	*val2 = chan->scan_type.realbits;
	259	return IIO_VAL_FRACTIONAL_LOG2;
68b14d7e LPC	260	case IIO_CHAN_INFO_OFFSET:
	261	*val = -(1 << chan->scan_type.realbits) / 2;
	262	return IIO_VAL_INT;
	263	}
	264
	265	return -EINVAL;
	266	}
	267
	268	static const struct iio_info ad5764_info = {
	269	.read_raw = ad5764_read_raw,
	270	.write_raw = ad5764_write_raw,
68b14d7e LPC	271	};
68b14d7e LPC	272
fc52692c	273	static int ad5764_probe(struct spi_device *spi)
68b14d7e LPC	274	{
	275	enum ad5764_type type = spi_get_device_id(spi)->driver_data;
	276	struct iio_dev *indio_dev;
	277	struct ad5764_state *st;
	278	int ret;
	279
7ff0de3f	280	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
68b14d7e LPC	281	if (indio_dev == NULL) {
	282	dev_err(&spi->dev, "Failed to allocate iio device\n");
	283	return -ENOMEM;
	284	}
	285
	286	st = iio_priv(indio_dev);
	287	spi_set_drvdata(spi, indio_dev);
	288
	289	st->spi = spi;
	290	st->chip_info = &ad5764_chip_infos[type];
	291
	292	indio_dev->dev.parent = &spi->dev;
	293	indio_dev->name = spi_get_device_id(spi)->name;
	294	indio_dev->info = &ad5764_info;
	295	indio_dev->modes = INDIO_DIRECT_MODE;
	296	indio_dev->num_channels = AD5764_NUM_CHANNELS;
	297	indio_dev->channels = st->chip_info->channels;
	298
	299	if (st->chip_info->int_vref == 0) {
	300	st->vref_reg[0].supply = "vrefAB";
	301	st->vref_reg[1].supply = "vrefCD";
	302
7ff0de3f	303	ret = devm_regulator_bulk_get(&st->spi->dev,
68b14d7e LPC	304	ARRAY_SIZE(st->vref_reg), st->vref_reg);
	305	if (ret) {
	306	dev_err(&spi->dev, "Failed to request vref regulators: %d\n",
	307	ret);
7ff0de3f	308	return ret;
68b14d7e LPC	309	}
	310
	311	ret = regulator_bulk_enable(ARRAY_SIZE(st->vref_reg),
	312	st->vref_reg);
	313	if (ret) {
	314	dev_err(&spi->dev, "Failed to enable vref regulators: %d\n",
	315	ret);
7ff0de3f	316	return ret;
68b14d7e LPC	317	}
	318	}
	319
	320	ret = iio_device_register(indio_dev);
	321	if (ret) {
	322	dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
	323	goto error_disable_reg;
	324	}
	325
	326	return 0;
	327
	328	error_disable_reg:
	329	if (st->chip_info->int_vref == 0)
	330	regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
68b14d7e LPC	331	return ret;
	332	}
	333
fc52692c	334	static int ad5764_remove(struct spi_device *spi)
68b14d7e LPC	335	{
	336	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	337	struct ad5764_state *st = iio_priv(indio_dev);
	338
	339	iio_device_unregister(indio_dev);
	340
7ff0de3f	341	if (st->chip_info->int_vref == 0)
68b14d7e	342	regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
68b14d7e LPC	343
	344	return 0;
	345	}
	346
	347	static const struct spi_device_id ad5764_ids[] = {
	348	{ "ad5744", ID_AD5744 },
	349	{ "ad5744r", ID_AD5744R },
	350	{ "ad5764", ID_AD5764 },
	351	{ "ad5764r", ID_AD5764R },
	352	{ }
	353	};
	354	MODULE_DEVICE_TABLE(spi, ad5764_ids);
	355
	356	static struct spi_driver ad5764_driver = {
	357	.driver = {
	358	.name = "ad5764",
68b14d7e LPC	359	},
68b14d7e LPC	360	.probe = ad5764_probe,
fc52692c	361	.remove = ad5764_remove,
68b14d7e LPC	362	.id_table = ad5764_ids,
68b14d7e LPC	363	};
519ff1d2	364	module_spi_driver(ad5764_driver);
68b14d7e LPC	365
	366	MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
	367	MODULE_DESCRIPTION("Analog Devices AD5744/AD5744R/AD5764/AD5764R DAC");
	368	MODULE_LICENSE("GPL v2");