[linux.git] / drivers / iio / dac / ad5686.c

// SPDX-License-Identifier: GPL-2.0
/*
 * AD5686R, AD5685R, AD5684R Digital to analog converters  driver
 *
 * Copyright 2011 Analog Devices Inc.
 */

#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#include "ad5686.h"

static const char * const ad5686_powerdown_modes[] = {
	"1kohm_to_gnd",
	"100kohm_to_gnd",
	"three_state"
};

static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
				     const struct iio_chan_spec *chan)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
}

static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
				     const struct iio_chan_spec *chan,
				     unsigned int mode)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
	st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2));

	return 0;
}

static const struct iio_enum ad5686_powerdown_mode_enum = {
	.items = ad5686_powerdown_modes,
	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
	.get = ad5686_get_powerdown_mode,
	.set = ad5686_set_powerdown_mode,
};

static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
		uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
				       (0x3 << (chan->channel * 2))));
}

static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
					  uintptr_t private,
					  const struct iio_chan_spec *chan,
					  const char *buf,
					  size_t len)
{
	bool readin;
	int ret;
	struct ad5686_state *st = iio_priv(indio_dev);
	unsigned int val, ref_bit_msk;
	u8 shift, address = 0;

	ret = strtobool(buf, &readin);
	if (ret)
		return ret;

	if (readin)
		st->pwr_down_mask |= (0x3 << (chan->channel * 2));
	else
		st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));

	switch (st->chip_info->regmap_type) {
	case AD5310_REGMAP:
		shift = 9;
		ref_bit_msk = AD5310_REF_BIT_MSK;
		break;
	case AD5683_REGMAP:
		shift = 13;
		ref_bit_msk = AD5683_REF_BIT_MSK;
		break;
	case AD5686_REGMAP:
		shift = 0;
		ref_bit_msk = 0;
		/* AD5674R/AD5679R have 16 channels and 2 powerdown registers */
		if (chan->channel > 0x7)
			address = 0x8;
		break;
	case AD5693_REGMAP:
		shift = 13;
		ref_bit_msk = AD5693_REF_BIT_MSK;
		break;
	default:
		return -EINVAL;
	}

	val = ((st->pwr_down_mask & st->pwr_down_mode) << shift);
	if (!st->use_internal_vref)
		val |= ref_bit_msk;

	ret = st->write(st, AD5686_CMD_POWERDOWN_DAC,
			address, val >> (address * 2));

	return ret ? ret : len;
}

static int ad5686_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	struct ad5686_state *st = iio_priv(indio_dev);
	int ret;

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&indio_dev->mlock);
		ret = st->read(st, chan->address);
		mutex_unlock(&indio_dev->mlock);
		if (ret < 0)
			return ret;
		*val = (ret >> chan->scan_type.shift) &
			GENMASK(chan->scan_type.realbits - 1, 0);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		*val = st->vref_mv;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}

static int ad5686_write_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int val,
			    int val2,
			    long mask)
{
	struct ad5686_state *st = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		if (val > (1 << chan->scan_type.realbits) || val < 0)
			return -EINVAL;

		mutex_lock(&indio_dev->mlock);
		ret = st->write(st,
				AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
				chan->address,
				val << chan->scan_type.shift);
		mutex_unlock(&indio_dev->mlock);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static const struct iio_info ad5686_info = {
	.read_raw = ad5686_read_raw,
	.write_raw = ad5686_write_raw,
};

static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
	{
		.name = "powerdown",
		.read = ad5686_read_dac_powerdown,
		.write = ad5686_write_dac_powerdown,
		.shared = IIO_SEPARATE,
	},
	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum),
	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
	{ },
};

#define AD5868_CHANNEL(chan, addr, bits, _shift) {		\
		.type = IIO_VOLTAGE,				\
		.indexed = 1,					\
		.output = 1,					\
		.channel = chan,				\
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
		.address = addr,				\
		.scan_type = {					\
			.sign = 'u',				\
			.realbits = (bits),			\
			.storagebits = 16,			\
			.shift = (_shift),			\
		},						\
		.ext_info = ad5686_ext_info,			\
}

#define DECLARE_AD5693_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 0, bits, _shift),		\
}

#define DECLARE_AD5686_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 1, bits, _shift),		\
		AD5868_CHANNEL(1, 2, bits, _shift),		\
		AD5868_CHANNEL(2, 4, bits, _shift),		\
		AD5868_CHANNEL(3, 8, bits, _shift),		\
}

#define DECLARE_AD5676_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 0, bits, _shift),		\
		AD5868_CHANNEL(1, 1, bits, _shift),		\
		AD5868_CHANNEL(2, 2, bits, _shift),		\
		AD5868_CHANNEL(3, 3, bits, _shift),		\
		AD5868_CHANNEL(4, 4, bits, _shift),		\
		AD5868_CHANNEL(5, 5, bits, _shift),		\
		AD5868_CHANNEL(6, 6, bits, _shift),		\
		AD5868_CHANNEL(7, 7, bits, _shift),		\
}

#define DECLARE_AD5679_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 0, bits, _shift),		\
		AD5868_CHANNEL(1, 1, bits, _shift),		\
		AD5868_CHANNEL(2, 2, bits, _shift),		\
		AD5868_CHANNEL(3, 3, bits, _shift),		\
		AD5868_CHANNEL(4, 4, bits, _shift),		\
		AD5868_CHANNEL(5, 5, bits, _shift),		\
		AD5868_CHANNEL(6, 6, bits, _shift),		\
		AD5868_CHANNEL(7, 7, bits, _shift),		\
		AD5868_CHANNEL(8, 8, bits, _shift),		\
		AD5868_CHANNEL(9, 9, bits, _shift),		\
		AD5868_CHANNEL(10, 10, bits, _shift),		\
		AD5868_CHANNEL(11, 11, bits, _shift),		\
		AD5868_CHANNEL(12, 12, bits, _shift),		\
		AD5868_CHANNEL(13, 13, bits, _shift),		\
		AD5868_CHANNEL(14, 14, bits, _shift),		\
		AD5868_CHANNEL(15, 15, bits, _shift),		\
}

DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2);
DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4);
DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0);
DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0);
DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4);
DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2);
DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0);
DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0);
DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2);
DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4);

static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
	[ID_AD5310R] = {
		.channels = ad5310r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5310_REGMAP,
	},
	[ID_AD5311R] = {
		.channels = ad5311r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5671R] = {
		.channels = ad5672_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5672R] = {
		.channels = ad5672_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5674R] = {
		.channels = ad5674r_channels,
		.int_vref_mv = 2500,
		.num_channels = 16,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5675R] = {
		.channels = ad5676_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5676] = {
		.channels = ad5676_channels,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5676R] = {
		.channels = ad5676_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5679R] = {
		.channels = ad5679r_channels,
		.int_vref_mv = 2500,
		.num_channels = 16,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5681R] = {
		.channels = ad5691r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5682R] = {
		.channels = ad5692r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5683] = {
		.channels = ad5693_channels,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5683R] = {
		.channels = ad5693_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5684] = {
		.channels = ad5684_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5684R] = {
		.channels = ad5684_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5685R] = {
		.channels = ad5685r_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5686] = {
		.channels = ad5686_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5686R] = {
		.channels = ad5686_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5691R] = {
		.channels = ad5691r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5692R] = {
		.channels = ad5692r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5693] = {
		.channels = ad5693_channels,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5693R] = {
		.channels = ad5693_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5694] = {
		.channels = ad5684_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5694R] = {
		.channels = ad5684_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5696] = {
		.channels = ad5686_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5696R] = {
		.channels = ad5686_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
};

int ad5686_probe(struct device *dev,
		 enum ad5686_supported_device_ids chip_type,
		 const char *name, ad5686_write_func write,
		 ad5686_read_func read)
{
	struct ad5686_state *st;
	struct iio_dev *indio_dev;
	unsigned int val, ref_bit_msk;
	u8 cmd;
	int ret, i, voltage_uv = 0;

	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
	if (indio_dev == NULL)
		return  -ENOMEM;

	st = iio_priv(indio_dev);
	dev_set_drvdata(dev, indio_dev);

	st->dev = dev;
	st->write = write;
	st->read = read;

	st->reg = devm_regulator_get_optional(dev, "vcc");
	if (!IS_ERR(st->reg)) {
		ret = regulator_enable(st->reg);
		if (ret)
			return ret;

		ret = regulator_get_voltage(st->reg);
		if (ret < 0)
			goto error_disable_reg;

		voltage_uv = ret;
	}

	st->chip_info = &ad5686_chip_info_tbl[chip_type];

	if (voltage_uv)
		st->vref_mv = voltage_uv / 1000;
	else
		st->vref_mv = st->chip_info->int_vref_mv;

	/* Set all the power down mode for all channels to 1K pulldown */
	for (i = 0; i < st->chip_info->num_channels; i++)
		st->pwr_down_mode |= (0x01 << (i * 2));

	indio_dev->dev.parent = dev;
	indio_dev->name = name;
	indio_dev->info = &ad5686_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channels;
	indio_dev->num_channels = st->chip_info->num_channels;

	switch (st->chip_info->regmap_type) {
	case AD5310_REGMAP:
		cmd = AD5686_CMD_CONTROL_REG;
		ref_bit_msk = AD5310_REF_BIT_MSK;
		st->use_internal_vref = !voltage_uv;
		break;
	case AD5683_REGMAP:
		cmd = AD5686_CMD_CONTROL_REG;
		ref_bit_msk = AD5683_REF_BIT_MSK;
		st->use_internal_vref = !voltage_uv;
		break;
	case AD5686_REGMAP:
		cmd = AD5686_CMD_INTERNAL_REFER_SETUP;
		ref_bit_msk = 0;
		break;
	case AD5693_REGMAP:
		cmd = AD5686_CMD_CONTROL_REG;
		ref_bit_msk = AD5693_REF_BIT_MSK;
		st->use_internal_vref = !voltage_uv;
		break;
	default:
		ret = -EINVAL;
		goto error_disable_reg;
	}

	val = (voltage_uv | ref_bit_msk);

	ret = st->write(st, cmd, 0, !!val);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_disable_reg;

	return 0;

error_disable_reg:
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);
	return ret;
}
EXPORT_SYMBOL_GPL(ad5686_probe);

int ad5686_remove(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct ad5686_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);

	return 0;
}
EXPORT_SYMBOL_GPL(ad5686_remove);

MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
cbd5dd38	1	// SPDX-License-Identifier: GPL-2.0
c2f37c8d MH	2	/*
	3	* AD5686R, AD5685R, AD5684R Digital to analog converters driver
	4	*
	5	* Copyright 2011 Analog Devices Inc.
c2f37c8d MH	6	*/
	7
	8	#include <linux/interrupt.h>
c2f37c8d MH	9	#include <linux/fs.h>
c2f37c8d MH	10	#include <linux/device.h>
99c97852	11	#include <linux/module.h>
c2f37c8d	12	#include <linux/kernel.h>
c2f37c8d MH	13	#include <linux/slab.h>
	14	#include <linux/sysfs.h>
	15	#include <linux/regulator/consumer.h>
	16
06458e27 JC	17	#include <linux/iio/iio.h>
06458e27 JC	18	#include <linux/iio/sysfs.h>
c2f37c8d	19
0357e488	20	#include "ad5686.h"
c2f37c8d	21
fe4586a8 LPC	22	static const char * const ad5686_powerdown_modes[] = {
	23	"1kohm_to_gnd",
	24	"100kohm_to_gnd",
	25	"three_state"
	26	};
	27
	28	static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
25ffba7a	29	const struct iio_chan_spec *chan)
c2f37c8d	30	{
c2f37c8d	31	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	32
fe4586a8	33	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
c2f37c8d MH	34	}
c2f37c8d MH	35
fe4586a8	36	static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
25ffba7a SP	37	const struct iio_chan_spec *chan,
25ffba7a SP	38	unsigned int mode)
c2f37c8d	39	{
c2f37c8d	40	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	41
fe4586a8 LPC	42	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
fe4586a8 LPC	43	st->pwr_down_mode \|= ((mode + 1) << (chan->channel * 2));
c2f37c8d	44
fe4586a8	45	return 0;
c2f37c8d MH	46	}
c2f37c8d MH	47
fe4586a8 LPC	48	static const struct iio_enum ad5686_powerdown_mode_enum = {
	49	.items = ad5686_powerdown_modes,
	50	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
	51	.get = ad5686_get_powerdown_mode,
	52	.set = ad5686_set_powerdown_mode,
	53	};
	54
	55	static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
25ffba7a	56	uintptr_t private, const struct iio_chan_spec chan, char buf)
c2f37c8d	57	{
c2f37c8d	58	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d MH	59
c2f37c8d MH	60	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
25ffba7a	61	(0x3 << (chan->channel * 2))));
c2f37c8d MH	62	}
c2f37c8d MH	63
fe4586a8	64	static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
25ffba7a SP	65	uintptr_t private,
	66	const struct iio_chan_spec *chan,
	67	const char *buf,
	68	size_t len)
c2f37c8d MH	69	{
	70	bool readin;
	71	int ret;
c2f37c8d	72	struct ad5686_state *st = iio_priv(indio_dev);
be1b24d2	73	unsigned int val, ref_bit_msk;
192778fb	74	u8 shift, address = 0;
c2f37c8d MH	75
	76	ret = strtobool(buf, &readin);
	77	if (ret)
	78	return ret;
	79
7737fa6d	80	if (readin)
fe4586a8	81	st->pwr_down_mask \|= (0x3 << (chan->channel * 2));
c2f37c8d	82	else
fe4586a8	83	st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));
c2f37c8d	84
be1b24d2	85	switch (st->chip_info->regmap_type) {
12d323cf SP	86	case AD5310_REGMAP:
	87	shift = 9;
	88	ref_bit_msk = AD5310_REF_BIT_MSK;
	89	break;
1dbae4c6 SP	90	case AD5683_REGMAP:
	91	shift = 13;
	92	ref_bit_msk = AD5683_REF_BIT_MSK;
	93	break;
be1b24d2 SP	94	case AD5686_REGMAP:
	95	shift = 0;
	96	ref_bit_msk = 0;
192778fb MC	97	/* AD5674R/AD5679R have 16 channels and 2 powerdown registers */
	98	if (chan->channel > 0x7)
	99	address = 0x8;
be1b24d2 SP	100	break;
	101	case AD5693_REGMAP:
	102	shift = 13;
	103	ref_bit_msk = AD5693_REF_BIT_MSK;
	104	break;
	105	default:
	106	return -EINVAL;
	107	}
	108
	109	val = ((st->pwr_down_mask & st->pwr_down_mode) << shift);
	110	if (!st->use_internal_vref)
	111	val \|= ref_bit_msk;
0357e488	112
192778fb MC	113	ret = st->write(st, AD5686_CMD_POWERDOWN_DAC,
192778fb MC	114	address, val >> (address * 2));
c2f37c8d MH	115
	116	return ret ? ret : len;
	117	}
	118
c2f37c8d MH	119	static int ad5686_read_raw(struct iio_dev *indio_dev,
	120	struct iio_chan_spec const *chan,
	121	int *val,
	122	int *val2,
	123	long m)
	124	{
	125	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d MH	126	int ret;
	127
	128	switch (m) {
09f4eb40	129	case IIO_CHAN_INFO_RAW:
c2f37c8d	130	mutex_lock(&indio_dev->mlock);
0357e488	131	ret = st->read(st, chan->address);
c2f37c8d MH	132	mutex_unlock(&indio_dev->mlock);
	133	if (ret < 0)
	134	return ret;
0e76df5c MC	135	*val = (ret >> chan->scan_type.shift) &
0e76df5c MC	136	GENMASK(chan->scan_type.realbits - 1, 0);
c2f37c8d	137	return IIO_VAL_INT;
c8a9f805	138	case IIO_CHAN_INFO_SCALE:
ecc7e948 LPC	139	*val = st->vref_mv;
	140	*val2 = chan->scan_type.realbits;
	141	return IIO_VAL_FRACTIONAL_LOG2;
c2f37c8d MH	142	}
	143	return -EINVAL;
	144	}
	145
	146	static int ad5686_write_raw(struct iio_dev *indio_dev,
25ffba7a SP	147	struct iio_chan_spec const *chan,
	148	int val,
	149	int val2,
	150	long mask)
c2f37c8d MH	151	{
	152	struct ad5686_state *st = iio_priv(indio_dev);
	153	int ret;
	154
	155	switch (mask) {
09f4eb40	156	case IIO_CHAN_INFO_RAW:
cd8eca6f	157	if (val > (1 << chan->scan_type.realbits) \|\| val < 0)
c2f37c8d MH	158	return -EINVAL;
	159
	160	mutex_lock(&indio_dev->mlock);
0357e488 SP	161	ret = st->write(st,
	162	AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
	163	chan->address,
	164	val << chan->scan_type.shift);
c2f37c8d MH	165	mutex_unlock(&indio_dev->mlock);
	166	break;
	167	default:
	168	ret = -EINVAL;
	169	}
	170
	171	return ret;
	172	}
	173
	174	static const struct iio_info ad5686_info = {
	175	.read_raw = ad5686_read_raw,
	176	.write_raw = ad5686_write_raw,
c2f37c8d MH	177	};
c2f37c8d MH	178
fe4586a8 LPC	179	static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
	180	{
	181	.name = "powerdown",
	182	.read = ad5686_read_dac_powerdown,
	183	.write = ad5686_write_dac_powerdown,
3704432f	184	.shared = IIO_SEPARATE,
fe4586a8	185	},
3704432f	186	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum),
fe4586a8 LPC	187	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
	188	{ },
	189	};
	190
f4a27306	191	#define AD5868_CHANNEL(chan, addr, bits, _shift) { \
fe4586a8 LPC	192	.type = IIO_VOLTAGE, \
	193	.indexed = 1, \
	194	.output = 1, \
	195	.channel = chan, \
d87a1d78 JC	196	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
d87a1d78 JC	197	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
f4a27306	198	.address = addr, \
44ba1593 JC	199	.scan_type = { \
	200	.sign = 'u', \
	201	.realbits = (bits), \
	202	.storagebits = 16, \
	203	.shift = (_shift), \
	204	}, \
fe4586a8 LPC	205	.ext_info = ad5686_ext_info, \
	206	}
	207
be1b24d2 SP	208	#define DECLARE_AD5693_CHANNELS(name, bits, _shift) \
	209	static struct iio_chan_spec name[] = { \
	210	AD5868_CHANNEL(0, 0, bits, _shift), \
	211	}
	212
f4a27306 SP	213	#define DECLARE_AD5686_CHANNELS(name, bits, _shift) \
	214	static struct iio_chan_spec name[] = { \
	215	AD5868_CHANNEL(0, 1, bits, _shift), \
	216	AD5868_CHANNEL(1, 2, bits, _shift), \
	217	AD5868_CHANNEL(2, 4, bits, _shift), \
	218	AD5868_CHANNEL(3, 8, bits, _shift), \
	219	}
	220
98baf78e SP	221	#define DECLARE_AD5676_CHANNELS(name, bits, _shift) \
	222	static struct iio_chan_spec name[] = { \
	223	AD5868_CHANNEL(0, 0, bits, _shift), \
	224	AD5868_CHANNEL(1, 1, bits, _shift), \
	225	AD5868_CHANNEL(2, 2, bits, _shift), \
	226	AD5868_CHANNEL(3, 3, bits, _shift), \
	227	AD5868_CHANNEL(4, 4, bits, _shift), \
	228	AD5868_CHANNEL(5, 5, bits, _shift), \
	229	AD5868_CHANNEL(6, 6, bits, _shift), \
	230	AD5868_CHANNEL(7, 7, bits, _shift), \
	231	}
	232
192778fb MC	233	#define DECLARE_AD5679_CHANNELS(name, bits, _shift) \
	234	static struct iio_chan_spec name[] = { \
	235	AD5868_CHANNEL(0, 0, bits, _shift), \
	236	AD5868_CHANNEL(1, 1, bits, _shift), \
	237	AD5868_CHANNEL(2, 2, bits, _shift), \
	238	AD5868_CHANNEL(3, 3, bits, _shift), \
	239	AD5868_CHANNEL(4, 4, bits, _shift), \
	240	AD5868_CHANNEL(5, 5, bits, _shift), \
	241	AD5868_CHANNEL(6, 6, bits, _shift), \
	242	AD5868_CHANNEL(7, 7, bits, _shift), \
	243	AD5868_CHANNEL(8, 8, bits, _shift), \
	244	AD5868_CHANNEL(9, 9, bits, _shift), \
	245	AD5868_CHANNEL(10, 10, bits, _shift), \
	246	AD5868_CHANNEL(11, 11, bits, _shift), \
	247	AD5868_CHANNEL(12, 12, bits, _shift), \
	248	AD5868_CHANNEL(13, 13, bits, _shift), \
	249	AD5868_CHANNEL(14, 14, bits, _shift), \
	250	AD5868_CHANNEL(15, 15, bits, _shift), \
	251	}
	252
12d323cf	253	DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2);
d8084a04	254	DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
98baf78e	255	DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
192778fb	256	DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4);
98baf78e	257	DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0);
192778fb	258	DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0);
f4a27306 SP	259	DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4);
	260	DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2);
	261	DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0);
be1b24d2 SP	262	DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0);
	263	DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2);
	264	DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4);
f4a27306	265
fe4586a8	266	static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
12d323cf SP	267	[ID_AD5310R] = {
	268	.channels = ad5310r_channels,
	269	.int_vref_mv = 2500,
	270	.num_channels = 1,
	271	.regmap_type = AD5310_REGMAP,
	272	},
d8084a04 SP	273	[ID_AD5311R] = {
	274	.channels = ad5311r_channels,
	275	.int_vref_mv = 2500,
	276	.num_channels = 1,
	277	.regmap_type = AD5693_REGMAP,
	278	},
4177381b SP	279	[ID_AD5671R] = {
	280	.channels = ad5672_channels,
	281	.int_vref_mv = 2500,
	282	.num_channels = 8,
be1b24d2	283	.regmap_type = AD5686_REGMAP,
4177381b	284	},
98baf78e SP	285	[ID_AD5672R] = {
	286	.channels = ad5672_channels,
	287	.int_vref_mv = 2500,
	288	.num_channels = 8,
be1b24d2	289	.regmap_type = AD5686_REGMAP,
98baf78e	290	},
192778fb MC	291	[ID_AD5674R] = {
	292	.channels = ad5674r_channels,
	293	.int_vref_mv = 2500,
	294	.num_channels = 16,
	295	.regmap_type = AD5686_REGMAP,
	296	},
4177381b SP	297	[ID_AD5675R] = {
	298	.channels = ad5676_channels,
	299	.int_vref_mv = 2500,
	300	.num_channels = 8,
be1b24d2	301	.regmap_type = AD5686_REGMAP,
4177381b	302	},
98baf78e SP	303	[ID_AD5676] = {
	304	.channels = ad5676_channels,
	305	.num_channels = 8,
be1b24d2	306	.regmap_type = AD5686_REGMAP,
98baf78e SP	307	},
	308	[ID_AD5676R] = {
	309	.channels = ad5676_channels,
	310	.int_vref_mv = 2500,
	311	.num_channels = 8,
be1b24d2	312	.regmap_type = AD5686_REGMAP,
98baf78e	313	},
192778fb MC	314	[ID_AD5679R] = {
	315	.channels = ad5679r_channels,
	316	.int_vref_mv = 2500,
	317	.num_channels = 16,
	318	.regmap_type = AD5686_REGMAP,
	319	},
1dbae4c6 SP	320	[ID_AD5681R] = {
	321	.channels = ad5691r_channels,
	322	.int_vref_mv = 2500,
	323	.num_channels = 1,
	324	.regmap_type = AD5683_REGMAP,
	325	},
	326	[ID_AD5682R] = {
	327	.channels = ad5692r_channels,
	328	.int_vref_mv = 2500,
	329	.num_channels = 1,
	330	.regmap_type = AD5683_REGMAP,
	331	},
	332	[ID_AD5683] = {
	333	.channels = ad5693_channels,
	334	.num_channels = 1,
	335	.regmap_type = AD5683_REGMAP,
	336	},
	337	[ID_AD5683R] = {
	338	.channels = ad5693_channels,
	339	.int_vref_mv = 2500,
	340	.num_channels = 1,
	341	.regmap_type = AD5683_REGMAP,
	342	},
fe4586a8	343	[ID_AD5684] = {
f4a27306 SP	344	.channels = ad5684_channels,
f4a27306 SP	345	.num_channels = 4,
be1b24d2	346	.regmap_type = AD5686_REGMAP,
98baf78e SP	347	},
	348	[ID_AD5684R] = {
	349	.channels = ad5684_channels,
fe4586a8	350	.int_vref_mv = 2500,
98baf78e	351	.num_channels = 4,
be1b24d2	352	.regmap_type = AD5686_REGMAP,
fe4586a8	353	},
fe642e2d	354	[ID_AD5685R] = {
f4a27306	355	.channels = ad5685r_channels,
fe4586a8	356	.int_vref_mv = 2500,
f4a27306	357	.num_channels = 4,
be1b24d2	358	.regmap_type = AD5686_REGMAP,
fe4586a8 LPC	359	},
fe4586a8 LPC	360	[ID_AD5686] = {
f4a27306 SP	361	.channels = ad5686_channels,
f4a27306 SP	362	.num_channels = 4,
be1b24d2	363	.regmap_type = AD5686_REGMAP,
98baf78e SP	364	},
	365	[ID_AD5686R] = {
	366	.channels = ad5686_channels,
fe4586a8	367	.int_vref_mv = 2500,
98baf78e	368	.num_channels = 4,
be1b24d2 SP	369	.regmap_type = AD5686_REGMAP,
	370	},
	371	[ID_AD5691R] = {
	372	.channels = ad5691r_channels,
	373	.int_vref_mv = 2500,
	374	.num_channels = 1,
	375	.regmap_type = AD5693_REGMAP,
	376	},
	377	[ID_AD5692R] = {
	378	.channels = ad5692r_channels,
	379	.int_vref_mv = 2500,
	380	.num_channels = 1,
	381	.regmap_type = AD5693_REGMAP,
	382	},
	383	[ID_AD5693] = {
	384	.channels = ad5693_channels,
	385	.num_channels = 1,
	386	.regmap_type = AD5693_REGMAP,
	387	},
	388	[ID_AD5693R] = {
	389	.channels = ad5693_channels,
	390	.int_vref_mv = 2500,
	391	.num_channels = 1,
	392	.regmap_type = AD5693_REGMAP,
fe4586a8	393	},
4177381b SP	394	[ID_AD5694] = {
	395	.channels = ad5684_channels,
	396	.num_channels = 4,
be1b24d2	397	.regmap_type = AD5686_REGMAP,
4177381b SP	398	},
	399	[ID_AD5694R] = {
	400	.channels = ad5684_channels,
	401	.int_vref_mv = 2500,
	402	.num_channels = 4,
be1b24d2	403	.regmap_type = AD5686_REGMAP,
4177381b SP	404	},
	405	[ID_AD5696] = {
	406	.channels = ad5686_channels,
	407	.num_channels = 4,
be1b24d2	408	.regmap_type = AD5686_REGMAP,
4177381b SP	409	},
	410	[ID_AD5696R] = {
	411	.channels = ad5686_channels,
	412	.int_vref_mv = 2500,
	413	.num_channels = 4,
be1b24d2	414	.regmap_type = AD5686_REGMAP,
4177381b	415	},
fe4586a8 LPC	416	};
fe4586a8 LPC	417
0357e488 SP	418	int ad5686_probe(struct device *dev,
	419	enum ad5686_supported_device_ids chip_type,
	420	const char *name, ad5686_write_func write,
	421	ad5686_read_func read)
c2f37c8d MH	422	{
	423	struct ad5686_state *st;
	424	struct iio_dev *indio_dev;
be1b24d2 SP	425	unsigned int val, ref_bit_msk;
	426	u8 cmd;
	427	int ret, i, voltage_uv = 0;
c2f37c8d	428
0357e488	429	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
c2f37c8d MH	430	if (indio_dev == NULL)
	431	return -ENOMEM;
	432
	433	st = iio_priv(indio_dev);
0357e488 SP	434	dev_set_drvdata(dev, indio_dev);
	435
	436	st->dev = dev;
	437	st->write = write;
	438	st->read = read;
c2f37c8d	439
0357e488	440	st->reg = devm_regulator_get_optional(dev, "vcc");
c2f37c8d MH	441	if (!IS_ERR(st->reg)) {
	442	ret = regulator_enable(st->reg);
	443	if (ret)
edf3fd41	444	return ret;
c2f37c8d	445
359570ad AL	446	ret = regulator_get_voltage(st->reg);
	447	if (ret < 0)
	448	goto error_disable_reg;
	449
	450	voltage_uv = ret;
c2f37c8d MH	451	}
c2f37c8d MH	452
0357e488	453	st->chip_info = &ad5686_chip_info_tbl[chip_type];
c2f37c8d MH	454
	455	if (voltage_uv)
	456	st->vref_mv = voltage_uv / 1000;
	457	else
	458	st->vref_mv = st->chip_info->int_vref_mv;
	459
fe4586a8	460	/* Set all the power down mode for all channels to 1K pulldown */
be1b24d2 SP	461	for (i = 0; i < st->chip_info->num_channels; i++)
be1b24d2 SP	462	st->pwr_down_mode \|= (0x01 << (i * 2));
fe4586a8	463
0357e488 SP	464	indio_dev->dev.parent = dev;
0357e488 SP	465	indio_dev->name = name;
c2f37c8d MH	466	indio_dev->info = &ad5686_info;
c2f37c8d MH	467	indio_dev->modes = INDIO_DIRECT_MODE;
f4a27306 SP	468	indio_dev->channels = st->chip_info->channels;
f4a27306 SP	469	indio_dev->num_channels = st->chip_info->num_channels;
c2f37c8d	470
be1b24d2	471	switch (st->chip_info->regmap_type) {
12d323cf SP	472	case AD5310_REGMAP:
	473	cmd = AD5686_CMD_CONTROL_REG;
	474	ref_bit_msk = AD5310_REF_BIT_MSK;
	475	st->use_internal_vref = !voltage_uv;
	476	break;
1dbae4c6 SP	477	case AD5683_REGMAP:
	478	cmd = AD5686_CMD_CONTROL_REG;
	479	ref_bit_msk = AD5683_REF_BIT_MSK;
	480	st->use_internal_vref = !voltage_uv;
	481	break;
be1b24d2 SP	482	case AD5686_REGMAP:
	483	cmd = AD5686_CMD_INTERNAL_REFER_SETUP;
	484	ref_bit_msk = 0;
	485	break;
	486	case AD5693_REGMAP:
	487	cmd = AD5686_CMD_CONTROL_REG;
	488	ref_bit_msk = AD5693_REF_BIT_MSK;
	489	st->use_internal_vref = !voltage_uv;
	490	break;
	491	default:
	492	ret = -EINVAL;
	493	goto error_disable_reg;
	494	}
	495
	496	val = (voltage_uv \| ref_bit_msk);
	497
	498	ret = st->write(st, cmd, 0, !!val);
c2f37c8d MH	499	if (ret)
	500	goto error_disable_reg;
	501
26d25ae3 JC	502	ret = iio_device_register(indio_dev);
	503	if (ret)
	504	goto error_disable_reg;
	505
c2f37c8d MH	506	return 0;
	507
	508	error_disable_reg:
	509	if (!IS_ERR(st->reg))
	510	regulator_disable(st->reg);
c2f37c8d MH	511	return ret;
c2f37c8d MH	512	}
0357e488	513	EXPORT_SYMBOL_GPL(ad5686_probe);
c2f37c8d	514
0357e488	515	int ad5686_remove(struct device *dev)
c2f37c8d	516	{
0357e488	517	struct iio_dev *indio_dev = dev_get_drvdata(dev);
c2f37c8d	518	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	519
d2fffd6c	520	iio_device_unregister(indio_dev);
edf3fd41	521	if (!IS_ERR(st->reg))
26a54797	522	regulator_disable(st->reg);
c2f37c8d MH	523
	524	return 0;
	525	}
0357e488	526	EXPORT_SYMBOL_GPL(ad5686_remove);
c2f37c8d	527
9920ed25	528	MODULE_AUTHOR("Michael Hennerich <[email protected]>");
c2f37c8d MH	529	MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
c2f37c8d MH	530	MODULE_LICENSE("GPL v2");