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ASoC: SOF: Intel: hda: add per-chip enable_sdw_irq() callback
[linux.git] / sound / soc / sof / intel / mtl.c
CommitLineData
064520e8
BL		 1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2022 Intel Corporation. All rights reserved.
4//
5// Authors: Ranjani Sridharan <[email protected]>
6//
7
8/*
9 * Hardware interface for audio DSP on Meteorlake.
10 */
11
12#include <linux/firmware.h>
13#include <sound/sof/ipc4/header.h>
d272b657 14#include <trace/events/sof_intel.h>
064520e8
BL		 15#include "../ipc4-priv.h"
16#include "../ops.h"
17#include "hda.h"
18#include "hda-ipc.h"
19#include "../sof-audio.h"
20#include "mtl.h"
21
22static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = {
23 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
24 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
25 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
26};
27
28static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
29{
30 /*
31 * clear busy interrupt to tell dsp controller this interrupt has been accepted,
32 * not trigger it again
33 */
34 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,
35 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY);
36 /*
37 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp
38 */
39 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,
40 MTL_DSP_REG_HFIPCXTDA_BUSY, 0);
41}
42
43static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
44{
45 /*
46 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it,
47 * don't send more reply to host
48 */
49 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,
50 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE);
51
52 /* unmask Done interrupt */
53 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
54 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE);
55}
56
57/* Check if an IPC IRQ occurred */
58static bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
59{
60 u32 irq_status;
61 u32 hfintipptr;
62
63 /* read Interrupt IP Pointer */
64 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
65 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
66
d272b657 67 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
064520e8
BL		 68
69 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC))
70 return true;
71
72 return false;
73}
74
75/* Check if an SDW IRQ occurred */
76static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
77{
78 u32 irq_status;
79 u32 hfintipptr;
80
81 /* read Interrupt IP Pointer */
82 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
83 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
84
85 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW))
86 return true;
87
88 return false;
89}
90
91static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
92{
483e4cdf 93 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
064520e8
BL		 94 struct sof_ipc4_msg *msg_data = msg->msg_data;
95
483e4cdf
PU		 96 if (hda_ipc4_tx_is_busy(sdev)) {
97 hdev->delayed_ipc_tx_msg = msg;
98 return 0;
99 }
100
101 hdev->delayed_ipc_tx_msg = NULL;
102
064520e8
BL		 103 /* send the message via mailbox */
104 if (msg_data->data_size)
105 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
106 msg_data->data_size);
107
108 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,
109 msg_data->extension);
110 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,
111 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY);
112
113 return 0;
114}
115
116static void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
117{
118 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
119 const struct sof_intel_dsp_desc *chip = hda->desc;
120
121 /* enable IPC DONE and BUSY interrupts */
122 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
123 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE,
124 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE);
125}
126
127static void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
128{
129 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
130 const struct sof_intel_dsp_desc *chip = hda->desc;
131
132 /* disable IPC DONE and BUSY interrupts */
133 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
134 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);
135}
136
137static int mtl_enable_interrupts(struct snd_sof_dev *sdev)
138{
139 u32 hfintipptr;
140 u32 irqinten;
141 u32 host_ipc;
142 u32 hipcie;
143 int ret;
144
145 /* read Interrupt IP Pointer */
146 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
147
148 /* Enable Host IPC and SOUNDWIRE */
149 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr,
150 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK,
151 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK);
152
153 /* check if operation was successful */
154 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
064520e8
BL		 155 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
156 (irqinten & host_ipc) == host_ipc,
157 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
158 if (ret < 0) {
159 dev_err(sdev->dev, "failed to enable Host IPC and/or SOUNDWIRE\n");
160 return ret;
161 }
162
163 /* Set Host IPC interrupt enable */
164 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE,
165 MTL_DSP_REG_HfHIPCIE_IE_MASK, MTL_DSP_REG_HfHIPCIE_IE_MASK);
166
167 /* check if operation was successful */
168 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK;
064520e8
BL		 169 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
170 (hipcie & host_ipc) == host_ipc,
171 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
172 if (ret < 0) {
173 dev_err(sdev->dev, "failed to set Host IPC interrupt enable\n");
174 return ret;
175 }
176
177 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE,
178 MTL_DSP_REG_HfSNDWIE_IE_MASK, MTL_DSP_REG_HfSNDWIE_IE_MASK);
179 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK;
064520e8
BL		 180 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
181 (hipcie & host_ipc) == host_ipc,
182 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
183 if (ret < 0)
184 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt enable\n");
185
186 return ret;
187}
188
189static int mtl_disable_interrupts(struct snd_sof_dev *sdev)
190{
191 u32 hfintipptr;
192 u32 irqinten;
193 u32 host_ipc;
194 u32 hipcie;
195 int ret1;
196 int ret;
197
198 /* read Interrupt IP Pointer */
199 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
200
201 /* Disable Host IPC and SOUNDWIRE */
202 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr,
203 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 0);
204
205 /* check if operation was successful */
206 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
064520e8
BL		 207 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
208 (irqinten & host_ipc) == 0,
209 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
210 /* Continue to disable other interrupts when error happens */
211 if (ret < 0)
212 dev_err(sdev->dev, "failed to disable Host IPC and SoundWire\n");
213
214 /* Set Host IPC interrupt disable */
215 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE,
216 MTL_DSP_REG_HfHIPCIE_IE_MASK, 0);
217
218 /* check if operation was successful */
219 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK;
064520e8
BL		 220 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
221 (hipcie & host_ipc) == 0,
222 HDA_DSP_REG_POLL_INTERVAL_US,
223 HDA_DSP_RESET_TIMEOUT_US);
224 if (ret1 < 0) {
225 dev_err(sdev->dev, "failed to set Host IPC interrupt disable\n");
226 if (!ret)
227 ret = ret1;
228 }
229
230 /* Set SoundWire IPC interrupt disable */
231 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE,
232 MTL_DSP_REG_HfSNDWIE_IE_MASK, 0);
233 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK;
064520e8
BL		 234 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
235 (hipcie & host_ipc) == 0,
236 HDA_DSP_REG_POLL_INTERVAL_US,
237 HDA_DSP_RESET_TIMEOUT_US);
238 if (ret1 < 0) {
239 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt disable\n");
240 if (!ret)
241 ret = ret1;
242 }
243
244 return ret;
245}
246
247/* pre fw run operations */
248static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
249{
250 u32 dsphfpwrsts;
251 u32 dsphfdsscs;
252 u32 cpa;
253 u32 pgs;
254 int ret;
255
256 /* Set the DSP subsystem power on */
257 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
258 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK);
259
260 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
261 usleep_range(1000, 1010);
262
263 /* poll with timeout to check if operation successful */
264 cpa = MTL_HFDSSCS_CPA_MASK;
064520e8
BL		 265 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
266 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
267 HDA_DSP_RESET_TIMEOUT_US);
268 if (ret < 0) {
269 dev_err(sdev->dev, "failed to enable DSP subsystem\n");
270 return ret;
271 }
272
273 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
274 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
275 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
276
277 usleep_range(1000, 1010);
278
279 /* poll with timeout to check if operation successful */
280 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
064520e8
BL		 281 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
282 (dsphfpwrsts & pgs) == pgs,
283 HDA_DSP_REG_POLL_INTERVAL_US,
284 HDA_DSP_RESET_TIMEOUT_US);
285 if (ret < 0)
286 dev_err(sdev->dev, "failed to power up gated DSP domain\n");
287
288 /* make sure SoundWire is not power-gated */
289 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL,
290 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));
291 return ret;
292}
293
294static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
295{
296 int ret;
297
298 if (sdev->first_boot) {
299 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
300
301 ret = hda_sdw_startup(sdev);
302 if (ret < 0) {
303 dev_err(sdev->dev, "could not startup SoundWire links\n");
304 return ret;
305 }
306
307 /* Check if IMR boot is usable */
308 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
309 hdev->imrboot_supported = true;
310 }
311
312 hda_sdw_int_enable(sdev, true);
313 return 0;
314}
315
316static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
317{
318 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
319 u32 romdbgsts;
320 u32 romdbgerr;
321 u32 fwsts;
322 u32 fwlec;
323
324 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
325 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
326 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY);
327 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR);
328
329 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec);
330 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts,
331 romdbgerr);
332 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3);
333 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n",
334 romdbgsts & BIT(24) ? "" : " not");
335}
336
337static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
338{
339 int val;
340
341 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);
342 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK)
343 return true;
344
345 return false;
346}
347
348static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
349{
350 unsigned int cpa;
351 u32 dspcxctl;
352 int ret;
353
354 /* Only the primary core can be powered up by the host */
355 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))
356 return 0;
357
358 /* Program the owner of the IP & shim registers (10: Host CPU) */
359 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
360 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL,
361 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT);
362
363 /* enable SPA bit */
364 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
365 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK,
366 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK);
367
368 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
369 usleep_range(1000, 1010);
370
371 /* poll with timeout to check if operation successful */
372 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK;
373 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
374 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
375 HDA_DSP_RESET_TIMEOUT_US);
740e5d87 376 if (ret < 0)
064520e8
BL		 377 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",
378 __func__);
064520e8
BL		 379
380 return ret;
381}
382
383static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
384{
385 u32 dspcxctl;
386 int ret;
387
388 /* Only the primary core can be powered down by the host */
389 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))
390 return 0;
391
392 /* disable SPA bit */
393 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
394 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0);
395
514bc59b 396 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
064520e8
BL		 397 usleep_range(1000, 1010);
398
399 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
400 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK),
401 HDA_DSP_REG_POLL_INTERVAL_US,
402 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
403 if (ret < 0)
404 dev_err(sdev->dev, "failed to power down primary core\n");
405
406 return ret;
407}
408
2090cb9b
FO		 409static int mtl_power_down_dsp(struct snd_sof_dev *sdev)
410{
411 u32 dsphfdsscs, cpa;
412 int ret;
413
414 /* first power down core */
415 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
416 if (ret) {
417 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
418 return ret;
419 }
420
421 /* Set the DSP subsystem power down */
422 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
423 MTL_HFDSSCS_SPA_MASK, 0);
424
514bc59b 425 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
2090cb9b
FO		 426 usleep_range(1000, 1010);
427
428 /* poll with timeout to check if operation successful */
429 cpa = MTL_HFDSSCS_CPA_MASK;
430 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
431 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
432 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
433 HDA_DSP_RESET_TIMEOUT_US);
434}
435
064520e8
BL		 436static int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
437{
438 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
439 const struct sof_intel_dsp_desc *chip = hda->desc;
440 unsigned int status;
441 u32 ipc_hdr;
442 int ret;
443
444 /* step 1: purge FW request */
445 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
446 if (!imr_boot)
447 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
448
449 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
450
451 /* step 2: power up primary core */
452 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
453 if (ret < 0) {
454 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
455 dev_err(sdev->dev, "dsp core 0/1 power up failed\n");
456 goto err;
457 }
458
459 dev_dbg(sdev->dev, "Primary core power up successful\n");
460
461 /* step 3: wait for IPC DONE bit from ROM */
462 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status,
463 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask),
464 HDA_DSP_REG_POLL_INTERVAL_US, MTL_DSP_PURGE_TIMEOUT_US);
465 if (ret < 0) {
466 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
467 dev_err(sdev->dev, "timeout waiting for purge IPC done\n");
468 goto err;
469 }
470
471 /* set DONE bit to clear the reply IPC message */
472 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask,
473 chip->ipc_ack_mask);
474
475 /* step 4: enable interrupts */
476 ret = mtl_enable_interrupts(sdev);
477 if (ret < 0) {
478 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
479 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__);
480 goto err;
481 }
482
483 mtl_enable_ipc_interrupts(sdev);
484
485 /*
486 * ACE workaround: don't wait for ROM INIT.
487 * The platform cannot catch ROM_INIT_DONE because of a very short
488 * timing window. Follow the recommendations and skip this part.
489 */
490
491 return 0;
492
493err:
494 snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0);
495 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
496 return ret;
497}
498
499static irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
500{
501 struct sof_ipc4_msg notification_data = {{ 0 }};
502 struct snd_sof_dev *sdev = context;
483e4cdf 503 bool ack_received = false;
064520e8
BL		 504 bool ipc_irq = false;
505 u32 hipcida;
506 u32 hipctdr;
507
508 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
c8ed7ce2 509 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
064520e8
BL		 510
511 /* reply message from DSP */
512 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) {
513 /* DSP received the message */
514 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
515 MTL_DSP_REG_HFIPCXCTL_DONE, 0);
516
517 mtl_ipc_dsp_done(sdev);
518
519 ipc_irq = true;
483e4cdf 520 ack_received = true;
064520e8
BL		 521 }
522
064520e8
BL		 523 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) {
524 /* Message from DSP (reply or notification) */
525 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
526 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK;
527
528 /*
529 * ACE fw sends a new fw ipc message to host to
530 * notify the status of the last host ipc message
531 */
532 if (primary & SOF_IPC4_MSG_DIR_MASK) {
533 /* Reply received */
1549a69b
PU		 534 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
535 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
064520e8 536
1549a69b
PU		 537 data->primary = primary;
538 data->extension = extension;
064520e8 539
1549a69b 540 spin_lock_irq(&sdev->ipc_lock);
064520e8 541
1549a69b 542 snd_sof_ipc_get_reply(sdev);
010c050f 543 mtl_ipc_host_done(sdev);
1549a69b 544 snd_sof_ipc_reply(sdev, data->primary);
064520e8 545
1549a69b
PU		 546 spin_unlock_irq(&sdev->ipc_lock);
547 } else {
548 dev_dbg_ratelimited(sdev->dev,
549 "IPC reply before FW_READY: %#x|%#x\n",
550 primary, extension);
551 }
064520e8
BL		 552 } else {
553 /* Notification received */
554 notification_data.primary = primary;
555 notification_data.extension = extension;
556
557 sdev->ipc->msg.rx_data = &notification_data;
558 snd_sof_ipc_msgs_rx(sdev);
559 sdev->ipc->msg.rx_data = NULL;
064520e8 560
010c050f
PU		 561 mtl_ipc_host_done(sdev);
562 }
064520e8
BL		 563
564 ipc_irq = true;
565 }
566
567 if (!ipc_irq) {
568 /* This interrupt is not shared so no need to return IRQ_NONE. */
b837870f 569 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
064520e8
BL		 570 }
571
483e4cdf
PU		 572 if (ack_received) {
573 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
574
575 if (hdev->delayed_ipc_tx_msg)
576 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg);
577 }
578
064520e8
BL		 579 return IRQ_HANDLED;
580}
581
582static int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
583{
584 return MTL_DSP_MBOX_UPLINK_OFFSET;
585}
586
587static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
588{
589 return MTL_SRAM_WINDOW_OFFSET(id);
590}
591
064520e8
BL		 592static void mtl_ipc_dump(struct snd_sof_dev *sdev)
593{
d01784ee 594 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
064520e8 595
d01784ee
PU		 596 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR);
597 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY);
064520e8 598 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
064520e8 599 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
d01784ee
PU		 600 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
601 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA);
602 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL);
064520e8 603
064520e8 604 dev_err(sdev->dev,
d01784ee
PU		 605 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
606 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
064520e8
BL		 607}
608
39df087f
RS		 609static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
610{
611 mtl_disable_ipc_interrupts(sdev);
612 return mtl_disable_interrupts(sdev);
613}
614
064520e8
BL		 615/* Meteorlake ops */
616struct snd_sof_dsp_ops sof_mtl_ops;
617EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
618
619int sof_mtl_ops_init(struct snd_sof_dev *sdev)
620{
621 struct sof_ipc4_fw_data *ipc4_data;
622
623 /* common defaults */
624 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
625
626 /* shutdown */
627 sof_mtl_ops.shutdown = hda_dsp_shutdown;
628
629 /* doorbell */
630 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread;
631
632 /* ipc */
633 sof_mtl_ops.send_msg = mtl_ipc_send_msg;
634 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
635 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
636
637 /* debug */
638 sof_mtl_ops.debug_map = mtl_dsp_debugfs;
639 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs);
640 sof_mtl_ops.dbg_dump = mtl_dsp_dump;
641 sof_mtl_ops.ipc_dump = mtl_ipc_dump;
642
643 /* pre/post fw run */
644 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
645 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run;
646
647 /* parse platform specific extended manifest */
648 sof_mtl_ops.parse_platform_ext_manifest = NULL;
649
650 /* dsp core get/put */
651 /* TODO: add core_get and core_put */
652
064520e8
BL		 653 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
654 if (!sdev->private)
655 return -ENOMEM;
656
657 ipc4_data = sdev->private;
658 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
659
cc4a3a19
PU		 660 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
661
3ab2c21e
PU		 662 /* External library loading support */
663 ipc4_data->load_library = hda_dsp_ipc4_load_library;
664
064520e8
BL		 665 /* set DAI ops */
666 hda_set_dai_drv_ops(sdev, &sof_mtl_ops);
667
668 return 0;
669};
670EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
671
672const struct sof_intel_dsp_desc mtl_chip_info = {
673 .cores_num = 3,
674 .init_core_mask = BIT(0),
675 .host_managed_cores_mask = BIT(0),
676 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
677 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
678 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
679 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
680 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
681 .rom_status_reg = MTL_DSP_ROM_STS,
682 .rom_init_timeout = 300,
9ccbc2e1 683 .ssp_count = MTL_SSP_COUNT,
064520e8
BL		 684 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
685 .sdw_shim_base = SDW_SHIM_BASE_ACE,
686 .sdw_alh_base = SDW_ALH_BASE_ACE,
f8632adc 687 .d0i3_offset = MTL_HDA_VS_D0I3C,
064520e8
BL		 688 .check_sdw_irq = mtl_dsp_check_sdw_irq,
689 .check_ipc_irq = mtl_dsp_check_ipc_irq,
690 .cl_init = mtl_dsp_cl_init,
2090cb9b 691 .power_down_dsp = mtl_power_down_dsp,
39df087f 692 .disable_interrupts = mtl_dsp_disable_interrupts,
064520e8
BL		 693 .hw_ip_version = SOF_INTEL_ACE_1_0,
694};
695EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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