[linux.git] / drivers / mailbox / ti-msgmgr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Texas Instruments' Message Manager Driver
 *
 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
 *	Nishanth Menon
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/soc/ti/ti-msgmgr.h>

#define Q_DATA_OFFSET(proxy, queue, reg)	\
		     ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
#define Q_STATE_OFFSET(queue)			((queue) * 0x4)
#define Q_STATE_ENTRY_COUNT_MASK		(0xFFF000)

/**
 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
 * @queue_id:	Queue Number for this path
 * @proxy_id:	Proxy ID representing the processor in SoC
 * @is_tx:	Is this a receive path?
 */
struct ti_msgmgr_valid_queue_desc {
	u8 queue_id;
	u8 proxy_id;
	bool is_tx;
};

/**
 * struct ti_msgmgr_desc - Description of message manager integration
 * @queue_count:	Number of Queues
 * @max_message_size:	Message size in bytes
 * @max_messages:	Number of messages
 * @q_slices:		Number of queue engines
 * @q_proxies:		Number of queue proxies per page
 * @data_first_reg:	First data register for proxy data region
 * @data_last_reg:	Last data register for proxy data region
 * @tx_polled:		Do I need to use polled mechanism for tx
 * @tx_poll_timeout_ms: Timeout in ms if polled
 * @valid_queues:	List of Valid queues that the processor can access
 * @num_valid_queues:	Number of valid queues
 *
 * This structure is used in of match data to describe how integration
 * for a specific compatible SoC is done.
 */
struct ti_msgmgr_desc {
	u8 queue_count;
	u8 max_message_size;
	u8 max_messages;
	u8 q_slices;
	u8 q_proxies;
	u8 data_first_reg;
	u8 data_last_reg;
	bool tx_polled;
	int tx_poll_timeout_ms;
	const struct ti_msgmgr_valid_queue_desc *valid_queues;
	int num_valid_queues;
};

/**
 * struct ti_queue_inst - Description of a queue instance
 * @name:	Queue Name
 * @queue_id:	Queue Identifier as mapped on SoC
 * @proxy_id:	Proxy Identifier as mapped on SoC
 * @irq:	IRQ for Rx Queue
 * @is_tx:	'true' if transmit queue, else, 'false'
 * @queue_buff_start: First register of Data Buffer
 * @queue_buff_end: Last (or confirmation) register of Data buffer
 * @queue_state: Queue status register
 * @chan:	Mailbox channel
 * @rx_buff:	Receive buffer pointer allocated at probe, max_message_size
 */
struct ti_queue_inst {
	char name[30];
	u8 queue_id;
	u8 proxy_id;
	int irq;
	bool is_tx;
	void __iomem *queue_buff_start;
	void __iomem *queue_buff_end;
	void __iomem *queue_state;
	struct mbox_chan *chan;
	u32 *rx_buff;
};

/**
 * struct ti_msgmgr_inst - Description of a Message Manager Instance
 * @dev:	device pointer corresponding to the Message Manager instance
 * @desc:	Description of the SoC integration
 * @queue_proxy_region:	Queue proxy region where queue buffers are located
 * @queue_state_debug_region:	Queue status register regions
 * @num_valid_queues:	Number of valid queues defined for the processor
 *		Note: other queues are probably reserved for other processors
 *		in the SoC.
 * @qinsts:	Array of valid Queue Instances for the Processor
 * @mbox:	Mailbox Controller
 * @chans:	Array for channels corresponding to the Queue Instances.
 */
struct ti_msgmgr_inst {
	struct device *dev;
	const struct ti_msgmgr_desc *desc;
	void __iomem *queue_proxy_region;
	void __iomem *queue_state_debug_region;
	u8 num_valid_queues;
	struct ti_queue_inst *qinsts;
	struct mbox_controller mbox;
	struct mbox_chan *chans;
};

/**
 * ti_msgmgr_queue_get_num_messages() - Get the number of pending messages
 * @qinst:	Queue instance for which we check the number of pending messages
 *
 * Return: number of messages pending in the queue (0 == no pending messages)
 */
static inline int ti_msgmgr_queue_get_num_messages(struct ti_queue_inst *qinst)
{
	u32 val;

	/*
	 * We cannot use relaxed operation here - update may happen
	 * real-time.
	 */
	val = readl(qinst->queue_state) & Q_STATE_ENTRY_COUNT_MASK;
	val >>= __ffs(Q_STATE_ENTRY_COUNT_MASK);

	return val;
}

/**
 * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue
 * @irq:	Interrupt number
 * @p:		Channel Pointer
 *
 * Return: -EINVAL if there is no instance
 * IRQ_NONE if the interrupt is not ours.
 * IRQ_HANDLED if the rx interrupt was successfully handled.
 */
static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p)
{
	struct mbox_chan *chan = p;
	struct device *dev = chan->mbox->dev;
	struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
	struct ti_queue_inst *qinst = chan->con_priv;
	const struct ti_msgmgr_desc *desc;
	int msg_count, num_words;
	struct ti_msgmgr_message message;
	void __iomem *data_reg;
	u32 *word_data;

	if (WARN_ON(!inst)) {
		dev_err(dev, "no platform drv data??\n");
		return -EINVAL;
	}

	/* Do I have an invalid interrupt source? */
	if (qinst->is_tx) {
		dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n",
			qinst->name);
		return IRQ_NONE;
	}

	/* Do I actually have messages to read? */
	msg_count = ti_msgmgr_queue_get_num_messages(qinst);
	if (!msg_count) {
		/* Shared IRQ? */
		dev_dbg(dev, "Spurious event - 0 pending data!\n");
		return IRQ_NONE;
	}

	/*
	 * I have no idea about the protocol being used to communicate with the
	 * remote producer - 0 could be valid data, so I wont make a judgement
	 * of how many bytes I should be reading. Let the client figure this
	 * out.. I just read the full message and pass it on..
	 */
	desc = inst->desc;
	message.len = desc->max_message_size;
	message.buf = (u8 *)qinst->rx_buff;

	/*
	 * NOTE about register access involved here:
	 * the hardware block is implemented with 32bit access operations and no
	 * support for data splitting.  We don't want the hardware to misbehave
	 * with sub 32bit access - For example: if the last register read is
	 * split into byte wise access, it can result in the queue getting
	 * stuck or indeterminate behavior. An out of order read operation may
	 * result in weird data results as well.
	 * Hence, we do not use memcpy_fromio or __ioread32_copy here, instead
	 * we depend on readl for the purpose.
	 *
	 * Also note that the final register read automatically marks the
	 * queue message as read.
	 */
	for (data_reg = qinst->queue_buff_start, word_data = qinst->rx_buff,
	     num_words = (desc->max_message_size / sizeof(u32));
	     num_words; num_words--, data_reg += sizeof(u32), word_data++)
		*word_data = readl(data_reg);

	/*
	 * Last register read automatically clears the IRQ if only 1 message
	 * is pending - so send the data up the stack..
	 * NOTE: Client is expected to be as optimal as possible, since
	 * we invoke the handler in IRQ context.
	 */
	mbox_chan_received_data(chan, (void *)&message);

	return IRQ_HANDLED;
}

/**
 * ti_msgmgr_queue_peek_data() - Peek to see if there are any rx messages.
 * @chan:	Channel Pointer
 *
 * Return: 'true' if there is pending rx data, 'false' if there is none.
 */
static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan)
{
	struct ti_queue_inst *qinst = chan->con_priv;
	int msg_count;

	if (qinst->is_tx)
		return false;

	msg_count = ti_msgmgr_queue_get_num_messages(qinst);

	return msg_count ? true : false;
}

/**
 * ti_msgmgr_last_tx_done() - See if all the tx messages are sent
 * @chan:	Channel pointer
 *
 * Return: 'true' is no pending tx data, 'false' if there are any.
 */
static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan)
{
	struct ti_queue_inst *qinst = chan->con_priv;
	int msg_count;

	if (!qinst->is_tx)
		return false;

	msg_count = ti_msgmgr_queue_get_num_messages(qinst);

	/* if we have any messages pending.. */
	return msg_count ? false : true;
}

/**
 * ti_msgmgr_send_data() - Send data
 * @chan:	Channel Pointer
 * @data:	ti_msgmgr_message * Message Pointer
 *
 * Return: 0 if all goes good, else appropriate error messages.
 */
static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
{
	struct device *dev = chan->mbox->dev;
	struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
	const struct ti_msgmgr_desc *desc;
	struct ti_queue_inst *qinst = chan->con_priv;
	int num_words, trail_bytes;
	struct ti_msgmgr_message *message = data;
	void __iomem *data_reg;
	u32 *word_data;

	if (WARN_ON(!inst)) {
		dev_err(dev, "no platform drv data??\n");
		return -EINVAL;
	}
	desc = inst->desc;

	if (desc->max_message_size < message->len) {
		dev_err(dev, "Queue %s message length %zu > max %d\n",
			qinst->name, message->len, desc->max_message_size);
		return -EINVAL;
	}

	/* NOTE: Constraints similar to rx path exists here as well */
	for (data_reg = qinst->queue_buff_start,
	     num_words = message->len / sizeof(u32),
	     word_data = (u32 *)message->buf;
	     num_words; num_words--, data_reg += sizeof(u32), word_data++)
		writel(*word_data, data_reg);

	trail_bytes = message->len % sizeof(u32);
	if (trail_bytes) {
		u32 data_trail = *word_data;

		/* Ensure all unused data is 0 */
		data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
		writel(data_trail, data_reg);
		data_reg++;
	}
	/*
	 * 'data_reg' indicates next register to write. If we did not already
	 * write on tx complete reg(last reg), we must do so for transmit
	 */
	if (data_reg <= qinst->queue_buff_end)
		writel(0, qinst->queue_buff_end);

	return 0;
}

/**
 * ti_msgmgr_queue_startup() - Startup queue
 * @chan:	Channel pointer
 *
 * Return: 0 if all goes good, else return corresponding error message
 */
static int ti_msgmgr_queue_startup(struct mbox_chan *chan)
{
	struct ti_queue_inst *qinst = chan->con_priv;
	struct device *dev = chan->mbox->dev;
	int ret;

	if (!qinst->is_tx) {
		/*
		 * With the expectation that the IRQ might be shared in SoC
		 */
		ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt,
				  IRQF_SHARED, qinst->name, chan);
		if (ret) {
			dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n",
				qinst->irq, qinst->name, ret);
			return ret;
		}
	}

	return 0;
}

/**
 * ti_msgmgr_queue_shutdown() - Shutdown the queue
 * @chan:	Channel pointer
 */
static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan)
{
	struct ti_queue_inst *qinst = chan->con_priv;

	if (!qinst->is_tx)
		free_irq(qinst->irq, chan);
}

/**
 * ti_msgmgr_of_xlate() - Translation of phandle to queue
 * @mbox:	Mailbox controller
 * @p:		phandle pointer
 *
 * Return: Mailbox channel corresponding to the queue, else return error
 * pointer.
 */
static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox,
					    const struct of_phandle_args *p)
{
	struct ti_msgmgr_inst *inst;
	int req_qid, req_pid;
	struct ti_queue_inst *qinst;
	int i;

	inst = container_of(mbox, struct ti_msgmgr_inst, mbox);
	if (WARN_ON(!inst))
		return ERR_PTR(-EINVAL);

	/* #mbox-cells is 2 */
	if (p->args_count != 2) {
		dev_err(inst->dev, "Invalid arguments in dt[%d] instead of 2\n",
			p->args_count);
		return ERR_PTR(-EINVAL);
	}
	req_qid = p->args[0];
	req_pid = p->args[1];

	for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues;
	     i++, qinst++) {
		if (req_qid == qinst->queue_id && req_pid == qinst->proxy_id)
			return qinst->chan;
	}

	dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %s\n",
		req_qid, req_pid, p->np->name);
	return ERR_PTR(-ENOENT);
}

/**
 * ti_msgmgr_queue_setup() - Setup data structures for each queue instance
 * @idx:	index of the queue
 * @dev:	pointer to the message manager device
 * @np:		pointer to the of node
 * @inst:	Queue instance pointer
 * @d:		Message Manager instance description data
 * @qd:		Queue description data
 * @qinst:	Queue instance pointer
 * @chan:	pointer to mailbox channel
 *
 * Return: 0 if all went well, else return corresponding error
 */
static int ti_msgmgr_queue_setup(int idx, struct device *dev,
				 struct device_node *np,
				 struct ti_msgmgr_inst *inst,
				 const struct ti_msgmgr_desc *d,
				 const struct ti_msgmgr_valid_queue_desc *qd,
				 struct ti_queue_inst *qinst,
				 struct mbox_chan *chan)
{
	qinst->proxy_id = qd->proxy_id;
	qinst->queue_id = qd->queue_id;

	if (qinst->queue_id > d->queue_count) {
		dev_err(dev, "Queue Data [idx=%d] queuid %d > %d\n",
			idx, qinst->queue_id, d->queue_count);
		return -ERANGE;
	}

	qinst->is_tx = qd->is_tx;
	snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d",
		 dev_name(dev), qinst->is_tx ? "tx" : "rx", qinst->queue_id,
		 qinst->proxy_id);

	if (!qinst->is_tx) {
		char of_rx_irq_name[7];

		snprintf(of_rx_irq_name, sizeof(of_rx_irq_name),
			 "rx_%03d", qinst->queue_id);

		qinst->irq = of_irq_get_byname(np, of_rx_irq_name);
		if (qinst->irq < 0) {
			dev_crit(dev,
				 "[%d]QID %d PID %d:No IRQ[%s]: %d\n",
				 idx, qinst->queue_id, qinst->proxy_id,
				 of_rx_irq_name, qinst->irq);
			return qinst->irq;
		}
		/* Allocate usage buffer for rx */
		qinst->rx_buff = devm_kzalloc(dev,
					      d->max_message_size, GFP_KERNEL);
		if (!qinst->rx_buff)
			return -ENOMEM;
	}

	qinst->queue_buff_start = inst->queue_proxy_region +
	    Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_first_reg);
	qinst->queue_buff_end = inst->queue_proxy_region +
	    Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_last_reg);
	qinst->queue_state = inst->queue_state_debug_region +
	    Q_STATE_OFFSET(qinst->queue_id);
	qinst->chan = chan;

	chan->con_priv = qinst;

	dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n",
		idx, qinst->queue_id, qinst->proxy_id, qinst->irq,
		qinst->queue_buff_start, qinst->queue_buff_end);
	return 0;
}

/* Queue operations */
static const struct mbox_chan_ops ti_msgmgr_chan_ops = {
	.startup = ti_msgmgr_queue_startup,
	.shutdown = ti_msgmgr_queue_shutdown,
	.peek_data = ti_msgmgr_queue_peek_data,
	.last_tx_done = ti_msgmgr_last_tx_done,
	.send_data = ti_msgmgr_send_data,
};

/* Keystone K2G SoC integration details */
static const struct ti_msgmgr_valid_queue_desc k2g_valid_queues[] = {
	{.queue_id = 0, .proxy_id = 0, .is_tx = true,},
	{.queue_id = 1, .proxy_id = 0, .is_tx = true,},
	{.queue_id = 2, .proxy_id = 0, .is_tx = true,},
	{.queue_id = 3, .proxy_id = 0, .is_tx = true,},
	{.queue_id = 5, .proxy_id = 2, .is_tx = false,},
	{.queue_id = 56, .proxy_id = 1, .is_tx = true,},
	{.queue_id = 57, .proxy_id = 2, .is_tx = false,},
	{.queue_id = 58, .proxy_id = 3, .is_tx = true,},
	{.queue_id = 59, .proxy_id = 4, .is_tx = true,},
	{.queue_id = 60, .proxy_id = 5, .is_tx = true,},
	{.queue_id = 61, .proxy_id = 6, .is_tx = true,},
};

static const struct ti_msgmgr_desc k2g_desc = {
	.queue_count = 64,
	.max_message_size = 64,
	.max_messages = 128,
	.q_slices = 1,
	.q_proxies = 1,
	.data_first_reg = 16,
	.data_last_reg = 31,
	.tx_polled = false,
	.valid_queues = k2g_valid_queues,
	.num_valid_queues = ARRAY_SIZE(k2g_valid_queues),
};

static const struct of_device_id ti_msgmgr_of_match[] = {
	{.compatible = "ti,k2g-message-manager", .data = &k2g_desc},
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match);

static int ti_msgmgr_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct device_node *np;
	struct resource *res;
	const struct ti_msgmgr_desc *desc;
	struct ti_msgmgr_inst *inst;
	struct ti_queue_inst *qinst;
	struct mbox_controller *mbox;
	struct mbox_chan *chans;
	int queue_count;
	int i;
	int ret = -EINVAL;
	const struct ti_msgmgr_valid_queue_desc *queue_desc;

	if (!dev->of_node) {
		dev_err(dev, "no OF information\n");
		return -EINVAL;
	}
	np = dev->of_node;

	of_id = of_match_device(ti_msgmgr_of_match, dev);
	if (!of_id) {
		dev_err(dev, "OF data missing\n");
		return -EINVAL;
	}
	desc = of_id->data;

	inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
	if (!inst)
		return -ENOMEM;

	inst->dev = dev;
	inst->desc = desc;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
					   "queue_proxy_region");
	inst->queue_proxy_region = devm_ioremap_resource(dev, res);
	if (IS_ERR(inst->queue_proxy_region))
		return PTR_ERR(inst->queue_proxy_region);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
					   "queue_state_debug_region");
	inst->queue_state_debug_region = devm_ioremap_resource(dev, res);
	if (IS_ERR(inst->queue_state_debug_region))
		return PTR_ERR(inst->queue_state_debug_region);

	dev_dbg(dev, "proxy region=%p, queue_state=%p\n",
		inst->queue_proxy_region, inst->queue_state_debug_region);

	queue_count = desc->num_valid_queues;
	if (!queue_count || queue_count > desc->queue_count) {
		dev_crit(dev, "Invalid Number of queues %d. Max %d\n",
			 queue_count, desc->queue_count);
		return -ERANGE;
	}
	inst->num_valid_queues = queue_count;

	qinst = devm_kzalloc(dev, sizeof(*qinst) * queue_count, GFP_KERNEL);
	if (!qinst)
		return -ENOMEM;
	inst->qinsts = qinst;

	chans = devm_kzalloc(dev, sizeof(*chans) * queue_count, GFP_KERNEL);
	if (!chans)
		return -ENOMEM;
	inst->chans = chans;

	for (i = 0, queue_desc = desc->valid_queues;
	     i < queue_count; i++, qinst++, chans++, queue_desc++) {
		ret = ti_msgmgr_queue_setup(i, dev, np, inst,
					    desc, queue_desc, qinst, chans);
		if (ret)
			return ret;
	}

	mbox = &inst->mbox;
	mbox->dev = dev;
	mbox->ops = &ti_msgmgr_chan_ops;
	mbox->chans = inst->chans;
	mbox->num_chans = inst->num_valid_queues;
	mbox->txdone_irq = false;
	mbox->txdone_poll = desc->tx_polled;
	if (desc->tx_polled)
		mbox->txpoll_period = desc->tx_poll_timeout_ms;
	mbox->of_xlate = ti_msgmgr_of_xlate;

	platform_set_drvdata(pdev, inst);
	ret = mbox_controller_register(mbox);
	if (ret)
		dev_err(dev, "Failed to register mbox_controller(%d)\n", ret);

	return ret;
}

static int ti_msgmgr_remove(struct platform_device *pdev)
{
	struct ti_msgmgr_inst *inst;

	inst = platform_get_drvdata(pdev);
	mbox_controller_unregister(&inst->mbox);

	return 0;
}

static struct platform_driver ti_msgmgr_driver = {
	.probe = ti_msgmgr_probe,
	.remove = ti_msgmgr_remove,
	.driver = {
		   .name = "ti-msgmgr",
		   .of_match_table = of_match_ptr(ti_msgmgr_of_match),
	},
};
module_platform_driver(ti_msgmgr_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI message manager driver");
MODULE_AUTHOR("Nishanth Menon");
MODULE_ALIAS("platform:ti-msgmgr");
Commit	Line	Data
4f0ceb87	1	// SPDX-License-Identifier: GPL-2.0
aace66b1 NM	2	/*
	3	* Texas Instruments' Message Manager Driver
	4	*
4f0ceb87	5	* Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
aace66b1	6	* Nishanth Menon
aace66b1 NM	7	*/
	8
	9	#define pr_fmt(fmt) "%s: " fmt, __func__
	10
	11	#include <linux/device.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mailbox_controller.h>
	16	#include <linux/module.h>
	17	#include <linux/of_device.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/soc/ti/ti-msgmgr.h>
	22
	23	#define Q_DATA_OFFSET(proxy, queue, reg) \
	24	((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
	25	#define Q_STATE_OFFSET(queue) ((queue) * 0x4)
	26	#define Q_STATE_ENTRY_COUNT_MASK (0xFFF000)
	27
	28	/**
	29	* struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
	30	* @queue_id: Queue Number for this path
	31	* @proxy_id: Proxy ID representing the processor in SoC
	32	* @is_tx: Is this a receive path?
	33	*/
	34	struct ti_msgmgr_valid_queue_desc {
	35	u8 queue_id;
	36	u8 proxy_id;
	37	bool is_tx;
	38	};
	39
	40	/**
	41	* struct ti_msgmgr_desc - Description of message manager integration
	42	* @queue_count: Number of Queues
	43	* @max_message_size: Message size in bytes
	44	* @max_messages: Number of messages
	45	* @q_slices: Number of queue engines
	46	* @q_proxies: Number of queue proxies per page
	47	* @data_first_reg: First data register for proxy data region
	48	* @data_last_reg: Last data register for proxy data region
	49	* @tx_polled: Do I need to use polled mechanism for tx
	50	* @tx_poll_timeout_ms: Timeout in ms if polled
	51	* @valid_queues: List of Valid queues that the processor can access
	52	* @num_valid_queues: Number of valid queues
	53	*
	54	* This structure is used in of match data to describe how integration
	55	* for a specific compatible SoC is done.
	56	*/
	57	struct ti_msgmgr_desc {
	58	u8 queue_count;
	59	u8 max_message_size;
	60	u8 max_messages;
	61	u8 q_slices;
	62	u8 q_proxies;
	63	u8 data_first_reg;
	64	u8 data_last_reg;
	65	bool tx_polled;
	66	int tx_poll_timeout_ms;
	67	const struct ti_msgmgr_valid_queue_desc *valid_queues;
	68	int num_valid_queues;
	69	};
	70
71	/**
72	* struct ti_queue_inst - Description of a queue instance
73	* @name: Queue Name
74	* @queue_id: Queue Identifier as mapped on SoC
75	* @proxy_id: Proxy Identifier as mapped on SoC
76	* @irq: IRQ for Rx Queue
77	* @is_tx: 'true' if transmit queue, else, 'false'
78	* @queue_buff_start: First register of Data Buffer
79	* @queue_buff_end: Last (or confirmation) register of Data buffer
80	* @queue_state: Queue status register
81	* @chan: Mailbox channel
82	* @rx_buff: Receive buffer pointer allocated at probe, max_message_size
83	*/
84	struct ti_queue_inst {
85	char name[30];
86	u8 queue_id;
87	u8 proxy_id;
88	int irq;
89	bool is_tx;
90	void __iomem *queue_buff_start;
91	void __iomem *queue_buff_end;
92	void __iomem *queue_state;
93	struct mbox_chan *chan;
94	u32 *rx_buff;
95	};
96
97	/**
98	* struct ti_msgmgr_inst - Description of a Message Manager Instance
99	* @dev: device pointer corresponding to the Message Manager instance
100	* @desc: Description of the SoC integration
101	* @queue_proxy_region: Queue proxy region where queue buffers are located
102	* @queue_state_debug_region: Queue status register regions
103	* @num_valid_queues: Number of valid queues defined for the processor
104	* Note: other queues are probably reserved for other processors
105	* in the SoC.
106	* @qinsts: Array of valid Queue Instances for the Processor
107	* @mbox: Mailbox Controller
108	* @chans: Array for channels corresponding to the Queue Instances.
109	*/
110	struct ti_msgmgr_inst {
111	struct device *dev;
112	const struct ti_msgmgr_desc *desc;
113	void __iomem *queue_proxy_region;
114	void __iomem *queue_state_debug_region;
115	u8 num_valid_queues;
116	struct ti_queue_inst *qinsts;
117	struct mbox_controller mbox;
118	struct mbox_chan *chans;
119	};
120
121	/**
122	* ti_msgmgr_queue_get_num_messages() - Get the number of pending messages
123	* @qinst: Queue instance for which we check the number of pending messages
124	*
125	* Return: number of messages pending in the queue (0 == no pending messages)
126	*/
127	static inline int ti_msgmgr_queue_get_num_messages(struct ti_queue_inst *qinst)
128	{
129	u32 val;
130
131	/*
132	* We cannot use relaxed operation here - update may happen
133	* real-time.
134	*/
135	val = readl(qinst->queue_state) & Q_STATE_ENTRY_COUNT_MASK;
136	val >>= __ffs(Q_STATE_ENTRY_COUNT_MASK);
137
138	return val;
139	}
140
141	/**
142	* ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue
143	* @irq: Interrupt number
144	* @p: Channel Pointer
145	*
146	* Return: -EINVAL if there is no instance
147	* IRQ_NONE if the interrupt is not ours.
148	* IRQ_HANDLED if the rx interrupt was successfully handled.
149	*/
150	static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p)
151	{
152	struct mbox_chan *chan = p;
153	struct device *dev = chan->mbox->dev;
154	struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
155	struct ti_queue_inst *qinst = chan->con_priv;
156	const struct ti_msgmgr_desc *desc;
157	int msg_count, num_words;
158	struct ti_msgmgr_message message;
159	void __iomem *data_reg;
160	u32 *word_data;
161
162	if (WARN_ON(!inst)) {
163	dev_err(dev, "no platform drv data??\n");
164	return -EINVAL;
165	}
166
167	/* Do I have an invalid interrupt source? */
168	if (qinst->is_tx) {
169	dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n",
170	qinst->name);
171	return IRQ_NONE;
172	}
173
174	/* Do I actually have messages to read? */
175	msg_count = ti_msgmgr_queue_get_num_messages(qinst);
176	if (!msg_count) {
177	/* Shared IRQ? */
178	dev_dbg(dev, "Spurious event - 0 pending data!\n");
179	return IRQ_NONE;
180	}
181
182	/*
183	* I have no idea about the protocol being used to communicate with the
184	* remote producer - 0 could be valid data, so I wont make a judgement
185	* of how many bytes I should be reading. Let the client figure this
186	* out.. I just read the full message and pass it on..
187	*/
188	desc = inst->desc;
189	message.len = desc->max_message_size;
190	message.buf = (u8 *)qinst->rx_buff;
191
192	/*
193	* NOTE about register access involved here:
194	* the hardware block is implemented with 32bit access operations and no
195	* support for data splitting. We don't want the hardware to misbehave
196	* with sub 32bit access - For example: if the last register read is
197	* split into byte wise access, it can result in the queue getting
198	* stuck or indeterminate behavior. An out of order read operation may
199	* result in weird data results as well.
200	* Hence, we do not use memcpy_fromio or __ioread32_copy here, instead
201	* we depend on readl for the purpose.
202	*
203	* Also note that the final register read automatically marks the
204	* queue message as read.
205	*/
206	for (data_reg = qinst->queue_buff_start, word_data = qinst->rx_buff,
207	num_words = (desc->max_message_size / sizeof(u32));
208	num_words; num_words--, data_reg += sizeof(u32), word_data++)
209	*word_data = readl(data_reg);
210
211	/*
212	* Last register read automatically clears the IRQ if only 1 message
213	* is pending - so send the data up the stack..
214	* NOTE: Client is expected to be as optimal as possible, since
215	* we invoke the handler in IRQ context.
216	*/
217	mbox_chan_received_data(chan, (void *)&message);
218
219	return IRQ_HANDLED;
220	}
221
222	/**
223	* ti_msgmgr_queue_peek_data() - Peek to see if there are any rx messages.
224	* @chan: Channel Pointer
225	*
226	* Return: 'true' if there is pending rx data, 'false' if there is none.
227	*/
228	static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan)
229	{
230	struct ti_queue_inst *qinst = chan->con_priv;
231	int msg_count;
232
233	if (qinst->is_tx)
234	return false;
235
236	msg_count = ti_msgmgr_queue_get_num_messages(qinst);
237
238	return msg_count ? true : false;
239	}
240
241	/**
242	* ti_msgmgr_last_tx_done() - See if all the tx messages are sent
243	* @chan: Channel pointer
244	*
245	* Return: 'true' is no pending tx data, 'false' if there are any.
246	*/
247	static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan)
248	{
249	struct ti_queue_inst *qinst = chan->con_priv;
250	int msg_count;
251
252	if (!qinst->is_tx)
253	return false;
254
255	msg_count = ti_msgmgr_queue_get_num_messages(qinst);
256
257	/* if we have any messages pending.. */
258	return msg_count ? false : true;
259	}
260
261	/**
262	* ti_msgmgr_send_data() - Send data
263	* @chan: Channel Pointer
264	* @data: ti_msgmgr_message * Message Pointer
265	*
266	* Return: 0 if all goes good, else appropriate error messages.
267	*/
268	static int ti_msgmgr_send_data(struct mbox_chan chan, void data)
269	{
270	struct device *dev = chan->mbox->dev;
271	struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
272	const struct ti_msgmgr_desc *desc;
273	struct ti_queue_inst *qinst = chan->con_priv;
274	int num_words, trail_bytes;
275	struct ti_msgmgr_message *message = data;
276	void __iomem *data_reg;
277	u32 *word_data;
278
279	if (WARN_ON(!inst)) {
280	dev_err(dev, "no platform drv data??\n");
281	return -EINVAL;
282	}
283	desc = inst->desc;
284
285	if (desc->max_message_size < message->len) {
ca64af43	286	dev_err(dev, "Queue %s message length %zu > max %d\n",
aace66b1 NM	287	qinst->name, message->len, desc->max_message_size);
	288	return -EINVAL;
	289	}
	290
	291	/* NOTE: Constraints similar to rx path exists here as well */
	292	for (data_reg = qinst->queue_buff_start,
	293	num_words = message->len / sizeof(u32),
	294	word_data = (u32 *)message->buf;
	295	num_words; num_words--, data_reg += sizeof(u32), word_data++)
	296	writel(*word_data, data_reg);
	297
	298	trail_bytes = message->len % sizeof(u32);
	299	if (trail_bytes) {
	300	u32 data_trail = *word_data;
	301
	302	/* Ensure all unused data is 0 */
	303	data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
	304	writel(data_trail, data_reg);
	305	data_reg++;
	306	}
	307	/*
	308	* 'data_reg' indicates next register to write. If we did not already
	309	* write on tx complete reg(last reg), we must do so for transmit
	310	*/
	311	if (data_reg <= qinst->queue_buff_end)
	312	writel(0, qinst->queue_buff_end);
	313
	314	return 0;
	315	}
	316
	317	/**
	318	* ti_msgmgr_queue_startup() - Startup queue
	319	* @chan: Channel pointer
	320	*
	321	* Return: 0 if all goes good, else return corresponding error message
	322	*/
	323	static int ti_msgmgr_queue_startup(struct mbox_chan *chan)
	324	{
	325	struct ti_queue_inst *qinst = chan->con_priv;
	326	struct device *dev = chan->mbox->dev;
	327	int ret;
	328
	329	if (!qinst->is_tx) {
	330	/*
	331	* With the expectation that the IRQ might be shared in SoC
	332	*/
	333	ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt,
	334	IRQF_SHARED, qinst->name, chan);
	335	if (ret) {
	336	dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n",
	337	qinst->irq, qinst->name, ret);
	338	return ret;
	339	}
	340	}
	341
	342	return 0;
	343	}
	344
	345	/**
	346	* ti_msgmgr_queue_shutdown() - Shutdown the queue
	347	* @chan: Channel pointer
	348	*/
	349	static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan)
	350	{
351	struct ti_queue_inst *qinst = chan->con_priv;
352
353	if (!qinst->is_tx)
354	free_irq(qinst->irq, chan);
355	}
356
357	/**
358	* ti_msgmgr_of_xlate() - Translation of phandle to queue
359	* @mbox: Mailbox controller
360	* @p: phandle pointer
361	*
362	* Return: Mailbox channel corresponding to the queue, else return error
363	* pointer.
364	*/
365	static struct mbox_chan ti_msgmgr_of_xlate(struct mbox_controller mbox,
366	const struct of_phandle_args *p)
367	{
368	struct ti_msgmgr_inst *inst;
369	int req_qid, req_pid;
370	struct ti_queue_inst *qinst;
371	int i;
372
373	inst = container_of(mbox, struct ti_msgmgr_inst, mbox);
374	if (WARN_ON(!inst))
375	return ERR_PTR(-EINVAL);
376
377	/* #mbox-cells is 2 */
378	if (p->args_count != 2) {
379	dev_err(inst->dev, "Invalid arguments in dt[%d] instead of 2\n",
380	p->args_count);
381	return ERR_PTR(-EINVAL);
382	}
383	req_qid = p->args[0];
384	req_pid = p->args[1];
385
386	for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues;
387	i++, qinst++) {
388	if (req_qid == qinst->queue_id && req_pid == qinst->proxy_id)
389	return qinst->chan;
390	}
391
392	dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %s\n",
393	req_qid, req_pid, p->np->name);
394	return ERR_PTR(-ENOENT);
395	}
396
397	/**
398	* ti_msgmgr_queue_setup() - Setup data structures for each queue instance
399	* @idx: index of the queue
400	* @dev: pointer to the message manager device
401	* @np: pointer to the of node
402	* @inst: Queue instance pointer
403	* @d: Message Manager instance description data
404	* @qd: Queue description data
405	* @qinst: Queue instance pointer
406	* @chan: pointer to mailbox channel
407	*
408	* Return: 0 if all went well, else return corresponding error
409	*/
410	static int ti_msgmgr_queue_setup(int idx, struct device *dev,
411	struct device_node *np,
412	struct ti_msgmgr_inst *inst,
413	const struct ti_msgmgr_desc *d,
414	const struct ti_msgmgr_valid_queue_desc *qd,
415	struct ti_queue_inst *qinst,
416	struct mbox_chan *chan)
417	{
418	qinst->proxy_id = qd->proxy_id;
419	qinst->queue_id = qd->queue_id;
420
421	if (qinst->queue_id > d->queue_count) {
422	dev_err(dev, "Queue Data [idx=%d] queuid %d > %d\n",
423	idx, qinst->queue_id, d->queue_count);
424	return -ERANGE;
425	}
426
427	qinst->is_tx = qd->is_tx;
428	snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d",
429	dev_name(dev), qinst->is_tx ? "tx" : "rx", qinst->queue_id,
430	qinst->proxy_id);
431
432	if (!qinst->is_tx) {
433	char of_rx_irq_name[7];
434
435	snprintf(of_rx_irq_name, sizeof(of_rx_irq_name),
436	"rx_%03d", qinst->queue_id);
437
438	qinst->irq = of_irq_get_byname(np, of_rx_irq_name);
439	if (qinst->irq < 0) {
440	dev_crit(dev,
441	"[%d]QID %d PID %d:No IRQ[%s]: %d\n",
442	idx, qinst->queue_id, qinst->proxy_id,
443	of_rx_irq_name, qinst->irq);
444	return qinst->irq;
445	}
446	/* Allocate usage buffer for rx */
447	qinst->rx_buff = devm_kzalloc(dev,
448	d->max_message_size, GFP_KERNEL);
449	if (!qinst->rx_buff)
450	return -ENOMEM;
451	}
452
453	qinst->queue_buff_start = inst->queue_proxy_region +
454	Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_first_reg);
455	qinst->queue_buff_end = inst->queue_proxy_region +
456	Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_last_reg);
457	qinst->queue_state = inst->queue_state_debug_region +
458	Q_STATE_OFFSET(qinst->queue_id);
459	qinst->chan = chan;
460
461	chan->con_priv = qinst;
462
463	dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n",
464	idx, qinst->queue_id, qinst->proxy_id, qinst->irq,
465	qinst->queue_buff_start, qinst->queue_buff_end);
466	return 0;
467	}
468
469	/* Queue operations */
470	static const struct mbox_chan_ops ti_msgmgr_chan_ops = {
471	.startup = ti_msgmgr_queue_startup,
472	.shutdown = ti_msgmgr_queue_shutdown,
473	.peek_data = ti_msgmgr_queue_peek_data,
474	.last_tx_done = ti_msgmgr_last_tx_done,
475	.send_data = ti_msgmgr_send_data,
476	};
477
478	/* Keystone K2G SoC integration details */
479	static const struct ti_msgmgr_valid_queue_desc k2g_valid_queues[] = {
480	{.queue_id = 0, .proxy_id = 0, .is_tx = true,},
481	{.queue_id = 1, .proxy_id = 0, .is_tx = true,},
482	{.queue_id = 2, .proxy_id = 0, .is_tx = true,},
483	{.queue_id = 3, .proxy_id = 0, .is_tx = true,},
484	{.queue_id = 5, .proxy_id = 2, .is_tx = false,},
485	{.queue_id = 56, .proxy_id = 1, .is_tx = true,},
486	{.queue_id = 57, .proxy_id = 2, .is_tx = false,},
487	{.queue_id = 58, .proxy_id = 3, .is_tx = true,},
488	{.queue_id = 59, .proxy_id = 4, .is_tx = true,},
489	{.queue_id = 60, .proxy_id = 5, .is_tx = true,},
490	{.queue_id = 61, .proxy_id = 6, .is_tx = true,},
491	};
492
493	static const struct ti_msgmgr_desc k2g_desc = {
494	.queue_count = 64,
495	.max_message_size = 64,
496	.max_messages = 128,
497	.q_slices = 1,
498	.q_proxies = 1,
499	.data_first_reg = 16,
500	.data_last_reg = 31,
501	.tx_polled = false,
502	.valid_queues = k2g_valid_queues,
503	.num_valid_queues = ARRAY_SIZE(k2g_valid_queues),
504	};
505
506	static const struct of_device_id ti_msgmgr_of_match[] = {
507	{.compatible = "ti,k2g-message-manager", .data = &k2g_desc},
508	{ /* Sentinel */ }
509	};
510	MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match);
511
512	static int ti_msgmgr_probe(struct platform_device *pdev)
513	{
514	struct device *dev = &pdev->dev;
515	const struct of_device_id *of_id;
516	struct device_node *np;
517	struct resource *res;
518	const struct ti_msgmgr_desc *desc;
519	struct ti_msgmgr_inst *inst;
520	struct ti_queue_inst *qinst;
521	struct mbox_controller *mbox;
522	struct mbox_chan *chans;
523	int queue_count;
524	int i;
525	int ret = -EINVAL;
526	const struct ti_msgmgr_valid_queue_desc *queue_desc;
527
528	if (!dev->of_node) {
529	dev_err(dev, "no OF information\n");
530	return -EINVAL;
531	}
532	np = dev->of_node;
533
534	of_id = of_match_device(ti_msgmgr_of_match, dev);
535	if (!of_id) {
536	dev_err(dev, "OF data missing\n");
537	return -EINVAL;
538	}
539	desc = of_id->data;
540
541	inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
542	if (!inst)
543	return -ENOMEM;
544
545	inst->dev = dev;
546	inst->desc = desc;
547
548	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
549	"queue_proxy_region");
550	inst->queue_proxy_region = devm_ioremap_resource(dev, res);
551	if (IS_ERR(inst->queue_proxy_region))
552	return PTR_ERR(inst->queue_proxy_region);
553
554	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
555	"queue_state_debug_region");
556	inst->queue_state_debug_region = devm_ioremap_resource(dev, res);
557	if (IS_ERR(inst->queue_state_debug_region))
558	return PTR_ERR(inst->queue_state_debug_region);
559
560	dev_dbg(dev, "proxy region=%p, queue_state=%p\n",
561	inst->queue_proxy_region, inst->queue_state_debug_region);
562
563	queue_count = desc->num_valid_queues;
564	if (!queue_count \|\| queue_count > desc->queue_count) {
565	dev_crit(dev, "Invalid Number of queues %d. Max %d\n",
566	queue_count, desc->queue_count);
567	return -ERANGE;
568	}
569	inst->num_valid_queues = queue_count;
570
571	qinst = devm_kzalloc(dev, sizeof(qinst) queue_count, GFP_KERNEL);
572	if (!qinst)
573	return -ENOMEM;
574	inst->qinsts = qinst;
575
576	chans = devm_kzalloc(dev, sizeof(chans) queue_count, GFP_KERNEL);
577	if (!chans)
578	return -ENOMEM;
579	inst->chans = chans;
580
581	for (i = 0, queue_desc = desc->valid_queues;
582	i < queue_count; i++, qinst++, chans++, queue_desc++) {
583	ret = ti_msgmgr_queue_setup(i, dev, np, inst,
584	desc, queue_desc, qinst, chans);
585	if (ret)
586	return ret;
587	}
588
589	mbox = &inst->mbox;
590	mbox->dev = dev;
591	mbox->ops = &ti_msgmgr_chan_ops;
592	mbox->chans = inst->chans;
593	mbox->num_chans = inst->num_valid_queues;
594	mbox->txdone_irq = false;
595	mbox->txdone_poll = desc->tx_polled;
596	if (desc->tx_polled)
597	mbox->txpoll_period = desc->tx_poll_timeout_ms;
598	mbox->of_xlate = ti_msgmgr_of_xlate;
599
600	platform_set_drvdata(pdev, inst);
601	ret = mbox_controller_register(mbox);
602	if (ret)
603	dev_err(dev, "Failed to register mbox_controller(%d)\n", ret);
604
605	return ret;
606	}
607
608	static int ti_msgmgr_remove(struct platform_device *pdev)
609	{
610	struct ti_msgmgr_inst *inst;
611
612	inst = platform_get_drvdata(pdev);
613	mbox_controller_unregister(&inst->mbox);
614
615	return 0;
616	}
617
618	static struct platform_driver ti_msgmgr_driver = {
619	.probe = ti_msgmgr_probe,
620	.remove = ti_msgmgr_remove,
621	.driver = {
622	.name = "ti-msgmgr",
623	.of_match_table = of_match_ptr(ti_msgmgr_of_match),
624	},
625	};
626	module_platform_driver(ti_msgmgr_driver);
627
628	MODULE_LICENSE("GPL v2");
629	MODULE_DESCRIPTION("TI message manager driver");
630	MODULE_AUTHOR("Nishanth Menon");
631	MODULE_ALIAS("platform:ti-msgmgr");