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ASoC: wm_adsp: Add support for SYSTEM firmware controls
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
2159ad93
MB		 35#include "wm_adsp.h"
36
37#define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45#define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47
48#define ADSP1_CONTROL_1 0x00
49#define ADSP1_CONTROL_2 0x02
50#define ADSP1_CONTROL_3 0x03
51#define ADSP1_CONTROL_4 0x04
52#define ADSP1_CONTROL_5 0x06
53#define ADSP1_CONTROL_6 0x07
54#define ADSP1_CONTROL_7 0x08
55#define ADSP1_CONTROL_8 0x09
56#define ADSP1_CONTROL_9 0x0A
57#define ADSP1_CONTROL_10 0x0B
58#define ADSP1_CONTROL_11 0x0C
59#define ADSP1_CONTROL_12 0x0D
60#define ADSP1_CONTROL_13 0x0F
61#define ADSP1_CONTROL_14 0x10
62#define ADSP1_CONTROL_15 0x11
63#define ADSP1_CONTROL_16 0x12
64#define ADSP1_CONTROL_17 0x13
65#define ADSP1_CONTROL_18 0x14
66#define ADSP1_CONTROL_19 0x16
67#define ADSP1_CONTROL_20 0x17
68#define ADSP1_CONTROL_21 0x18
69#define ADSP1_CONTROL_22 0x1A
70#define ADSP1_CONTROL_23 0x1B
71#define ADSP1_CONTROL_24 0x1C
72#define ADSP1_CONTROL_25 0x1E
73#define ADSP1_CONTROL_26 0x20
74#define ADSP1_CONTROL_27 0x21
75#define ADSP1_CONTROL_28 0x22
76#define ADSP1_CONTROL_29 0x23
77#define ADSP1_CONTROL_30 0x24
78#define ADSP1_CONTROL_31 0x26
79
80/*
81 * ADSP1 Control 19
82 */
83#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86
87
88/*
89 * ADSP1 Control 30
90 */
91#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103#define ADSP1_START 0x0001 /* DSP1_START */
104#define ADSP1_START_MASK 0x0001 /* DSP1_START */
105#define ADSP1_START_SHIFT 0 /* DSP1_START */
106#define ADSP1_START_WIDTH 1 /* DSP1_START */
107
94e205bf
CR		 108/*
109 * ADSP1 Control 31
110 */
111#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
114
2d30b575
MB		 115#define ADSP2_CONTROL 0x0
116#define ADSP2_CLOCKING 0x1
117#define ADSP2_STATUS1 0x4
118#define ADSP2_WDMA_CONFIG_1 0x30
119#define ADSP2_WDMA_CONFIG_2 0x31
120#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 121
10337b07
RF		 122#define ADSP2_SCRATCH0 0x40
123#define ADSP2_SCRATCH1 0x41
124#define ADSP2_SCRATCH2 0x42
125#define ADSP2_SCRATCH3 0x43
126
2159ad93
MB		 127/*
128 * ADSP2 Control
129 */
130
131#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
132#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
133#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
134#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
135#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
136#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
137#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
138#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
139#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
140#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
141#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
142#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
143#define ADSP2_START 0x0001 /* DSP1_START */
144#define ADSP2_START_MASK 0x0001 /* DSP1_START */
145#define ADSP2_START_SHIFT 0 /* DSP1_START */
146#define ADSP2_START_WIDTH 1 /* DSP1_START */
147
973838a0
MB		 148/*
149 * ADSP2 clocking
150 */
151#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
152#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
153#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
154
2159ad93
MB		 155/*
156 * ADSP2 Status 1
157 */
158#define ADSP2_RAM_RDY 0x0001
159#define ADSP2_RAM_RDY_MASK 0x0001
160#define ADSP2_RAM_RDY_SHIFT 0
161#define ADSP2_RAM_RDY_WIDTH 1
162
9ee78757
CK		 163#define ADSP_MAX_STD_CTRL_SIZE 512
164
f4f0c4c6
RF		 165#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
166#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
167
168/*
169 * Event control messages
170 */
171#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
172
cf17c83c
MB		 173struct wm_adsp_buf {
174 struct list_head list;
175 void *buf;
176};
177
178static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
179 struct list_head *list)
180{
181 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
182
183 if (buf == NULL)
184 return NULL;
185
cdcd7f72 186 buf->buf = vmalloc(len);
cf17c83c 187 if (!buf->buf) {
cdcd7f72 188 vfree(buf);
cf17c83c
MB		 189 return NULL;
190 }
cdcd7f72 191 memcpy(buf->buf, src, len);
cf17c83c
MB		 192
193 if (list)
194 list_add_tail(&buf->list, list);
195
196 return buf;
197}
198
199static void wm_adsp_buf_free(struct list_head *list)
200{
201 while (!list_empty(list)) {
202 struct wm_adsp_buf *buf = list_first_entry(list,
203 struct wm_adsp_buf,
204 list);
205 list_del(&buf->list);
cdcd7f72 206 vfree(buf->buf);
cf17c83c
MB		 207 kfree(buf);
208 }
209}
210
04d1300f
CK		 211#define WM_ADSP_FW_MBC_VSS 0
212#define WM_ADSP_FW_HIFI 1
213#define WM_ADSP_FW_TX 2
214#define WM_ADSP_FW_TX_SPK 3
215#define WM_ADSP_FW_RX 4
216#define WM_ADSP_FW_RX_ANC 5
217#define WM_ADSP_FW_CTRL 6
218#define WM_ADSP_FW_ASR 7
219#define WM_ADSP_FW_TRACE 8
220#define WM_ADSP_FW_SPK_PROT 9
221#define WM_ADSP_FW_MISC 10
222
223#define WM_ADSP_NUM_FW 11
dd84f925 224
1023dbd9 225static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 226 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
227 [WM_ADSP_FW_HIFI] = "MasterHiFi",
228 [WM_ADSP_FW_TX] = "Tx",
229 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
230 [WM_ADSP_FW_RX] = "Rx",
231 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
232 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
233 [WM_ADSP_FW_ASR] = "ASR Assist",
234 [WM_ADSP_FW_TRACE] = "Dbg Trace",
235 [WM_ADSP_FW_SPK_PROT] = "Protection",
236 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 237};
238
2cd19bdb
CK		 239struct wm_adsp_system_config_xm_hdr {
240 __be32 sys_enable;
241 __be32 fw_id;
242 __be32 fw_rev;
243 __be32 boot_status;
244 __be32 watchdog;
245 __be32 dma_buffer_size;
246 __be32 rdma[6];
247 __be32 wdma[8];
248 __be32 build_job_name[3];
249 __be32 build_job_number;
250};
251
252struct wm_adsp_alg_xm_struct {
253 __be32 magic;
254 __be32 smoothing;
255 __be32 threshold;
256 __be32 host_buf_ptr;
257 __be32 start_seq;
258 __be32 high_water_mark;
259 __be32 low_water_mark;
260 __be64 smoothed_power;
261};
262
263struct wm_adsp_buffer {
264 __be32 X_buf_base; /* XM base addr of first X area */
265 __be32 X_buf_size; /* Size of 1st X area in words */
266 __be32 X_buf_base2; /* XM base addr of 2nd X area */
267 __be32 X_buf_brk; /* Total X size in words */
268 __be32 Y_buf_base; /* YM base addr of Y area */
269 __be32 wrap; /* Total size X and Y in words */
270 __be32 high_water_mark; /* Point at which IRQ is asserted */
271 __be32 irq_count; /* bits 1-31 count IRQ assertions */
272 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
273 __be32 next_write_index; /* word index of next write */
274 __be32 next_read_index; /* word index of next read */
275 __be32 error; /* error if any */
276 __be32 oldest_block_index; /* word index of oldest surviving */
277 __be32 requested_rewind; /* how many blocks rewind was done */
278 __be32 reserved_space; /* internal */
279 __be32 min_free; /* min free space since stream start */
280 __be32 blocks_written[2]; /* total blocks written (64 bit) */
281 __be32 words_written[2]; /* total words written (64 bit) */
282};
283
721be3be
CK		 284struct wm_adsp_compr;
285
2cd19bdb
CK		 286struct wm_adsp_compr_buf {
287 struct wm_adsp *dsp;
721be3be 288 struct wm_adsp_compr *compr;
2cd19bdb
CK		 289
290 struct wm_adsp_buffer_region *regions;
291 u32 host_buf_ptr;
565ace46
CK		 292
293 u32 error;
294 u32 irq_count;
295 int read_index;
296 int avail;
2cd19bdb
CK		 297};
298
406abc95
CK		 299struct wm_adsp_compr {
300 struct wm_adsp *dsp;
95fe9597 301 struct wm_adsp_compr_buf *buf;
406abc95
CK		 302
303 struct snd_compr_stream *stream;
304 struct snd_compressed_buffer size;
565ace46 305
83a40ce9 306 u32 *raw_buf;
565ace46 307 unsigned int copied_total;
da2b3358
CK		 308
309 unsigned int sample_rate;
406abc95
CK		 310};
311
312#define WM_ADSP_DATA_WORD_SIZE 3
313
314#define WM_ADSP_MIN_FRAGMENTS 1
315#define WM_ADSP_MAX_FRAGMENTS 256
316#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
317#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
318
2cd19bdb
CK		 319#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
320
321#define HOST_BUFFER_FIELD(field) \
322 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
323
324#define ALG_XM_FIELD(field) \
325 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
326
327static int wm_adsp_buffer_init(struct wm_adsp *dsp);
328static int wm_adsp_buffer_free(struct wm_adsp *dsp);
329
330struct wm_adsp_buffer_region {
331 unsigned int offset;
332 unsigned int cumulative_size;
333 unsigned int mem_type;
334 unsigned int base_addr;
335};
336
337struct wm_adsp_buffer_region_def {
338 unsigned int mem_type;
339 unsigned int base_offset;
340 unsigned int size_offset;
341};
342
3a9686c4 343static const struct wm_adsp_buffer_region_def default_regions[] = {
2cd19bdb
CK		 344 {
345 .mem_type = WMFW_ADSP2_XM,
346 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
347 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
348 },
349 {
350 .mem_type = WMFW_ADSP2_XM,
351 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
352 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
353 },
354 {
355 .mem_type = WMFW_ADSP2_YM,
356 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
357 .size_offset = HOST_BUFFER_FIELD(wrap),
358 },
359};
360
406abc95
CK		 361struct wm_adsp_fw_caps {
362 u32 id;
363 struct snd_codec_desc desc;
2cd19bdb 364 int num_regions;
3a9686c4 365 const struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 366};
367
e6d00f34 368static const struct wm_adsp_fw_caps ctrl_caps[] = {
406abc95
CK		 369 {
370 .id = SND_AUDIOCODEC_BESPOKE,
371 .desc = {
372 .max_ch = 1,
373 .sample_rates = { 16000 },
374 .num_sample_rates = 1,
375 .formats = SNDRV_PCM_FMTBIT_S16_LE,
376 },
e6d00f34
CK		 377 .num_regions = ARRAY_SIZE(default_regions),
378 .region_defs = default_regions,
406abc95
CK		 379 },
380};
381
7ce4283c
CK		 382static const struct wm_adsp_fw_caps trace_caps[] = {
383 {
384 .id = SND_AUDIOCODEC_BESPOKE,
385 .desc = {
386 .max_ch = 8,
387 .sample_rates = {
388 4000, 8000, 11025, 12000, 16000, 22050,
389 24000, 32000, 44100, 48000, 64000, 88200,
390 96000, 176400, 192000
391 },
392 .num_sample_rates = 15,
393 .formats = SNDRV_PCM_FMTBIT_S16_LE,
394 },
395 .num_regions = ARRAY_SIZE(default_regions),
396 .region_defs = default_regions,
406abc95
CK		 397 },
398};
399
400static const struct {
1023dbd9 401 const char *file;
406abc95
CK		 402 int compr_direction;
403 int num_caps;
404 const struct wm_adsp_fw_caps *caps;
20b7f7c5 405 bool voice_trigger;
1023dbd9 406} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 407 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
408 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
409 [WM_ADSP_FW_TX] = { .file = "tx" },
410 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
411 [WM_ADSP_FW_RX] = { .file = "rx" },
412 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 413 [WM_ADSP_FW_CTRL] = {
414 .file = "ctrl",
415 .compr_direction = SND_COMPRESS_CAPTURE,
e6d00f34
CK		 416 .num_caps = ARRAY_SIZE(ctrl_caps),
417 .caps = ctrl_caps,
20b7f7c5 418 .voice_trigger = true,
406abc95 419 },
04d1300f 420 [WM_ADSP_FW_ASR] = { .file = "asr" },
7ce4283c
CK		 421 [WM_ADSP_FW_TRACE] = {
422 .file = "trace",
423 .compr_direction = SND_COMPRESS_CAPTURE,
424 .num_caps = ARRAY_SIZE(trace_caps),
425 .caps = trace_caps,
426 },
04d1300f
CK		 427 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
428 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 429};
430
6ab2b7b4
DP		 431struct wm_coeff_ctl_ops {
432 int (*xget)(struct snd_kcontrol *kcontrol,
433 struct snd_ctl_elem_value *ucontrol);
434 int (*xput)(struct snd_kcontrol *kcontrol,
435 struct snd_ctl_elem_value *ucontrol);
436 int (*xinfo)(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_info *uinfo);
438};
439
6ab2b7b4
DP		 440struct wm_coeff_ctl {
441 const char *name;
2323736d 442 const char *fw_name;
3809f001 443 struct wm_adsp_alg_region alg_region;
6ab2b7b4 444 struct wm_coeff_ctl_ops ops;
3809f001 445 struct wm_adsp *dsp;
6ab2b7b4
DP		 446 unsigned int enabled:1;
447 struct list_head list;
448 void *cache;
2323736d 449 unsigned int offset;
6ab2b7b4 450 size_t len;
0c2e3f34 451 unsigned int set:1;
6ab2b7b4 452 struct snd_kcontrol *kcontrol;
9ee78757 453 struct soc_bytes_ext bytes_ext;
26c22a19 454 unsigned int flags;
8eb084d0 455 unsigned int type;
6ab2b7b4
DP		 456};
457
9ce5e6e6
RF		 458static const char *wm_adsp_mem_region_name(unsigned int type)
459{
460 switch (type) {
461 case WMFW_ADSP1_PM:
462 return "PM";
463 case WMFW_ADSP1_DM:
464 return "DM";
465 case WMFW_ADSP2_XM:
466 return "XM";
467 case WMFW_ADSP2_YM:
468 return "YM";
469 case WMFW_ADSP1_ZM:
470 return "ZM";
471 default:
472 return NULL;
473 }
474}
475
f9f55e31
RF		 476#ifdef CONFIG_DEBUG_FS
477static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
478{
479 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
480
f9f55e31
RF		 481 kfree(dsp->wmfw_file_name);
482 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 483}
484
485static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
486{
487 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
488
f9f55e31
RF		 489 kfree(dsp->bin_file_name);
490 dsp->bin_file_name = tmp;
f9f55e31
RF		 491}
492
493static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
494{
f9f55e31
RF		 495 kfree(dsp->wmfw_file_name);
496 kfree(dsp->bin_file_name);
497 dsp->wmfw_file_name = NULL;
498 dsp->bin_file_name = NULL;
f9f55e31
RF		 499}
500
501static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
502 char __user *user_buf,
503 size_t count, loff_t *ppos)
504{
505 struct wm_adsp *dsp = file->private_data;
506 ssize_t ret;
507
078e7183 508 mutex_lock(&dsp->pwr_lock);
f9f55e31 509
28823eba 510 if (!dsp->wmfw_file_name || !dsp->booted)
f9f55e31
RF		 511 ret = 0;
512 else
513 ret = simple_read_from_buffer(user_buf, count, ppos,
514 dsp->wmfw_file_name,
515 strlen(dsp->wmfw_file_name));
516
078e7183 517 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 518 return ret;
519}
520
521static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
522 char __user *user_buf,
523 size_t count, loff_t *ppos)
524{
525 struct wm_adsp *dsp = file->private_data;
526 ssize_t ret;
527
078e7183 528 mutex_lock(&dsp->pwr_lock);
f9f55e31 529
28823eba 530 if (!dsp->bin_file_name || !dsp->booted)
f9f55e31
RF		 531 ret = 0;
532 else
533 ret = simple_read_from_buffer(user_buf, count, ppos,
534 dsp->bin_file_name,
535 strlen(dsp->bin_file_name));
536
078e7183 537 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 538 return ret;
539}
540
541static const struct {
542 const char *name;
543 const struct file_operations fops;
544} wm_adsp_debugfs_fops[] = {
545 {
546 .name = "wmfw_file_name",
547 .fops = {
548 .open = simple_open,
549 .read = wm_adsp_debugfs_wmfw_read,
550 },
551 },
552 {
553 .name = "bin_file_name",
554 .fops = {
555 .open = simple_open,
556 .read = wm_adsp_debugfs_bin_read,
557 },
558 },
559};
560
561static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
562 struct snd_soc_codec *codec)
563{
564 struct dentry *root = NULL;
565 char *root_name;
566 int i;
567
568 if (!codec->component.debugfs_root) {
569 adsp_err(dsp, "No codec debugfs root\n");
570 goto err;
571 }
572
573 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
574 if (!root_name)
575 goto err;
576
577 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
578 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
579 kfree(root_name);
580
581 if (!root)
582 goto err;
583
28823eba
CK		 584 if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted))
585 goto err;
586
f9f55e31
RF		 587 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
588 goto err;
589
590 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
591 goto err;
592
593 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
594 &dsp->fw_id_version))
595 goto err;
596
597 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
598 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
599 S_IRUGO, root, dsp,
600 &wm_adsp_debugfs_fops[i].fops))
601 goto err;
602 }
603
604 dsp->debugfs_root = root;
605 return;
606
607err:
608 debugfs_remove_recursive(root);
609 adsp_err(dsp, "Failed to create debugfs\n");
610}
611
612static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
613{
614 wm_adsp_debugfs_clear(dsp);
615 debugfs_remove_recursive(dsp->debugfs_root);
616}
617#else
618static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
619 struct snd_soc_codec *codec)
620{
621}
622
623static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
624{
625}
626
627static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
628 const char *s)
629{
630}
631
632static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
633 const char *s)
634{
635}
636
637static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
638{
639}
640#endif
641
1023dbd9
MB		 642static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
643 struct snd_ctl_elem_value *ucontrol)
644{
ea53bf77 645 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 646 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 647 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 648
15c66570 649 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 650
651 return 0;
652}
653
654static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
655 struct snd_ctl_elem_value *ucontrol)
656{
ea53bf77 657 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 658 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 659 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 660 int ret = 0;
1023dbd9 661
15c66570 662 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 663 return 0;
664
15c66570 665 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
1023dbd9
MB		 666 return -EINVAL;
667
d27c5e15
CK		 668 mutex_lock(&dsp[e->shift_l].pwr_lock);
669
28823eba 670 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
d27c5e15
CK		 671 ret = -EBUSY;
672 else
15c66570 673 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
1023dbd9 674
d27c5e15 675 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 676
d27c5e15 677 return ret;
1023dbd9
MB		 678}
679
680static const struct soc_enum wm_adsp_fw_enum[] = {
681 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
682 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
683 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
684 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
685};
686
336d0442 687const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 688 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
689 wm_adsp_fw_get, wm_adsp_fw_put),
690 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
691 wm_adsp_fw_get, wm_adsp_fw_put),
692 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
693 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 694 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
695 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 696};
336d0442 697EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 698
699static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
700 int type)
701{
702 int i;
703
704 for (i = 0; i < dsp->num_mems; i++)
705 if (dsp->mem[i].type == type)
706 return &dsp->mem[i];
707
708 return NULL;
709}
710
3809f001 711static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 712 unsigned int offset)
713{
3809f001 714 if (WARN_ON(!mem))
6c452bda 715 return offset;
3809f001 716 switch (mem->type) {
45b9ee72 717 case WMFW_ADSP1_PM:
3809f001 718 return mem->base + (offset * 3);
45b9ee72 719 case WMFW_ADSP1_DM:
3809f001 720 return mem->base + (offset * 2);
45b9ee72 721 case WMFW_ADSP2_XM:
3809f001 722 return mem->base + (offset * 2);
45b9ee72 723 case WMFW_ADSP2_YM:
3809f001 724 return mem->base + (offset * 2);
45b9ee72 725 case WMFW_ADSP1_ZM:
3809f001 726 return mem->base + (offset * 2);
45b9ee72 727 default:
6c452bda 728 WARN(1, "Unknown memory region type");
45b9ee72
MB		 729 return offset;
730 }
731}
732
10337b07
RF		 733static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
734{
735 u16 scratch[4];
736 int ret;
737
738 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
739 scratch, sizeof(scratch));
740 if (ret) {
741 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
742 return;
743 }
744
745 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
746 be16_to_cpu(scratch[0]),
747 be16_to_cpu(scratch[1]),
748 be16_to_cpu(scratch[2]),
749 be16_to_cpu(scratch[3]));
750}
751
9ee78757
CK		 752static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
753{
754 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
755}
756
7585a5b0 757static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 758 struct snd_ctl_elem_info *uinfo)
759{
9ee78757
CK		 760 struct soc_bytes_ext *bytes_ext =
761 (struct soc_bytes_ext *)kctl->private_value;
762 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4
DP		 763
764 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
765 uinfo->count = ctl->len;
766 return 0;
767}
768
f4f0c4c6
RF		 769static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
770 unsigned int event_id)
771{
772 struct wm_adsp *dsp = ctl->dsp;
773 u32 val = cpu_to_be32(event_id);
774 unsigned int reg;
775 int i, ret;
776
777 ret = wm_coeff_base_reg(ctl, &reg);
778 if (ret)
779 return ret;
780
781 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
782 event_id, ctl->alg_region.alg,
783 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
784
785 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
786 if (ret) {
787 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
788 return ret;
789 }
790
791 /*
792 * Poll for ack, we initially poll at ~1ms intervals for firmwares
793 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
794 * to ack instantly so we do the first 1ms delay before reading the
795 * control to avoid a pointless bus transaction
796 */
797 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
798 switch (i) {
799 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
800 usleep_range(1000, 2000);
801 i++;
802 break;
803 default:
804 usleep_range(10000, 20000);
805 i += 10;
806 break;
807 }
808
809 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
810 if (ret) {
811 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
812 return ret;
813 }
814
815 if (val == 0) {
816 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
817 return 0;
818 }
819 }
820
821 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
822 reg, ctl->alg_region.alg,
823 wm_adsp_mem_region_name(ctl->alg_region.type),
824 ctl->offset);
825
826 return -ETIMEDOUT;
827}
828
c9f8dd71 829static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 830 const void *buf, size_t len)
831{
3809f001 832 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 833 const struct wm_adsp_region *mem;
3809f001 834 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 835 void *scratch;
836 int ret;
837 unsigned int reg;
838
3809f001 839 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 840 if (!mem) {
3809f001
CK		 841 adsp_err(dsp, "No base for region %x\n",
842 alg_region->type);
6ab2b7b4
DP		 843 return -EINVAL;
844 }
845
2323736d 846 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 847 reg = wm_adsp_region_to_reg(mem, reg);
848
4f8ea6d7 849 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 850 if (!scratch)
851 return -ENOMEM;
852
3809f001 853 ret = regmap_raw_write(dsp->regmap, reg, scratch,
4f8ea6d7 854 len);
6ab2b7b4 855 if (ret) {
3809f001 856 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
4f8ea6d7 857 len, reg, ret);
6ab2b7b4
DP		 858 kfree(scratch);
859 return ret;
860 }
4f8ea6d7 861 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
6ab2b7b4
DP		 862
863 kfree(scratch);
864
865 return 0;
866}
867
7585a5b0 868static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 869 struct snd_ctl_elem_value *ucontrol)
870{
9ee78757
CK		 871 struct soc_bytes_ext *bytes_ext =
872 (struct soc_bytes_ext *)kctl->private_value;
873 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 874 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 875 int ret = 0;
876
877 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 878
879 memcpy(ctl->cache, p, ctl->len);
880
65d17a9c 881 ctl->set = 1;
cef45771 882 if (ctl->enabled && ctl->dsp->running)
168d10e7 883 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 884
168d10e7
CK		 885 mutex_unlock(&ctl->dsp->pwr_lock);
886
887 return ret;
6ab2b7b4
DP		 888}
889
9ee78757
CK		 890static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
891 const unsigned int __user *bytes, unsigned int size)
892{
893 struct soc_bytes_ext *bytes_ext =
894 (struct soc_bytes_ext *)kctl->private_value;
895 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
896 int ret = 0;
897
898 mutex_lock(&ctl->dsp->pwr_lock);
899
900 if (copy_from_user(ctl->cache, bytes, size)) {
901 ret = -EFAULT;
902 } else {
903 ctl->set = 1;
cef45771 904 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 905 ret = wm_coeff_write_control(ctl, ctl->cache, size);
906 }
907
908 mutex_unlock(&ctl->dsp->pwr_lock);
909
910 return ret;
911}
912
c9f8dd71 913static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 914 void *buf, size_t len)
915{
3809f001 916 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 917 const struct wm_adsp_region *mem;
3809f001 918 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 919 void *scratch;
920 int ret;
921 unsigned int reg;
922
3809f001 923 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 924 if (!mem) {
3809f001
CK		 925 adsp_err(dsp, "No base for region %x\n",
926 alg_region->type);
6ab2b7b4
DP		 927 return -EINVAL;
928 }
929
2323736d 930 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 931 reg = wm_adsp_region_to_reg(mem, reg);
932
4f8ea6d7 933 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 934 if (!scratch)
935 return -ENOMEM;
936
4f8ea6d7 937 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
6ab2b7b4 938 if (ret) {
3809f001 939 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
5602a643 940 len, reg, ret);
6ab2b7b4
DP		 941 kfree(scratch);
942 return ret;
943 }
4f8ea6d7 944 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
6ab2b7b4 945
4f8ea6d7 946 memcpy(buf, scratch, len);
6ab2b7b4
DP		 947 kfree(scratch);
948
949 return 0;
950}
951
7585a5b0 952static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 953 struct snd_ctl_elem_value *ucontrol)
954{
9ee78757
CK		 955 struct soc_bytes_ext *bytes_ext =
956 (struct soc_bytes_ext *)kctl->private_value;
957 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 958 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 959 int ret = 0;
960
961 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 962
26c22a19 963 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 964 if (ctl->enabled && ctl->dsp->running)
168d10e7 965 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 966 else
168d10e7
CK		 967 ret = -EPERM;
968 } else {
cef45771 969 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
bc1765d6
CK		 970 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
971
168d10e7 972 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 973 }
974
168d10e7 975 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 976
168d10e7 977 return ret;
6ab2b7b4
DP		 978}
979
9ee78757
CK		 980static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
981 unsigned int __user *bytes, unsigned int size)
982{
983 struct soc_bytes_ext *bytes_ext =
984 (struct soc_bytes_ext *)kctl->private_value;
985 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
986 int ret = 0;
987
988 mutex_lock(&ctl->dsp->pwr_lock);
989
990 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 991 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 992 ret = wm_coeff_read_control(ctl, ctl->cache, size);
993 else
994 ret = -EPERM;
995 } else {
cef45771 996 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
9ee78757
CK		 997 ret = wm_coeff_read_control(ctl, ctl->cache, size);
998 }
999
1000 if (!ret && copy_to_user(bytes, ctl->cache, size))
1001 ret = -EFAULT;
1002
1003 mutex_unlock(&ctl->dsp->pwr_lock);
1004
1005 return ret;
1006}
1007
6ab2b7b4 1008struct wmfw_ctl_work {
3809f001 1009 struct wm_adsp *dsp;
6ab2b7b4
DP		 1010 struct wm_coeff_ctl *ctl;
1011 struct work_struct work;
1012};
1013
9ee78757
CK		 1014static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1015{
1016 unsigned int out, rd, wr, vol;
1017
1018 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1019 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1020 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1021 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1022
1023 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1024 } else {
1025 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1026 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1027 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1028
1029 out = 0;
1030 }
1031
1032 if (in) {
1033 if (in & WMFW_CTL_FLAG_READABLE)
1034 out |= rd;
1035 if (in & WMFW_CTL_FLAG_WRITEABLE)
1036 out |= wr;
1037 if (in & WMFW_CTL_FLAG_VOLATILE)
1038 out |= vol;
1039 } else {
1040 out |= rd | wr | vol;
1041 }
1042
1043 return out;
1044}
1045
3809f001 1046static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 1047{
1048 struct snd_kcontrol_new *kcontrol;
1049 int ret;
1050
92bb4c32 1051 if (!ctl || !ctl->name)
6ab2b7b4
DP		 1052 return -EINVAL;
1053
1054 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1055 if (!kcontrol)
1056 return -ENOMEM;
6ab2b7b4
DP		 1057
1058 kcontrol->name = ctl->name;
1059 kcontrol->info = wm_coeff_info;
1060 kcontrol->get = wm_coeff_get;
1061 kcontrol->put = wm_coeff_put;
9ee78757
CK		 1062 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1063 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1064 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
6ab2b7b4 1065
9ee78757
CK		 1066 ctl->bytes_ext.max = ctl->len;
1067 ctl->bytes_ext.get = wm_coeff_tlv_get;
1068 ctl->bytes_ext.put = wm_coeff_tlv_put;
1069
1070 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
26c22a19 1071
7d00cd97 1072 ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1);
6ab2b7b4
DP		 1073 if (ret < 0)
1074 goto err_kcontrol;
1075
1076 kfree(kcontrol);
1077
7d00cd97 1078 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name);
81ad93ec 1079
6ab2b7b4
DP		 1080 return 0;
1081
1082err_kcontrol:
1083 kfree(kcontrol);
1084 return ret;
1085}
1086
b21acc1c
CK		 1087static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1088{
1089 struct wm_coeff_ctl *ctl;
1090 int ret;
1091
1092 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1093 if (!ctl->enabled || ctl->set)
1094 continue;
26c22a19
CK		 1095 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1096 continue;
1097
7d00cd97 1098 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1099 if (ret < 0)
1100 return ret;
1101 }
1102
1103 return 0;
1104}
1105
1106static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1107{
1108 struct wm_coeff_ctl *ctl;
1109 int ret;
1110
1111 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1112 if (!ctl->enabled)
1113 continue;
26c22a19 1114 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
7d00cd97 1115 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1116 if (ret < 0)
1117 return ret;
1118 }
1119 }
1120
1121 return 0;
1122}
1123
f4f0c4c6
RF		 1124static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1125 unsigned int event)
1126{
1127 struct wm_coeff_ctl *ctl;
1128 int ret;
1129
1130 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1131 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1132 continue;
1133
1134 ret = wm_coeff_write_acked_control(ctl, event);
1135 if (ret)
1136 adsp_warn(dsp,
1137 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1138 event, ctl->alg_region.alg, ret);
1139 }
1140}
1141
b21acc1c
CK		 1142static void wm_adsp_ctl_work(struct work_struct *work)
1143{
1144 struct wmfw_ctl_work *ctl_work = container_of(work,
1145 struct wmfw_ctl_work,
1146 work);
1147
1148 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1149 kfree(ctl_work);
1150}
1151
66225e98
RF		 1152static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1153{
1154 kfree(ctl->cache);
1155 kfree(ctl->name);
1156 kfree(ctl);
1157}
1158
b21acc1c
CK		 1159static int wm_adsp_create_control(struct wm_adsp *dsp,
1160 const struct wm_adsp_alg_region *alg_region,
2323736d 1161 unsigned int offset, unsigned int len,
26c22a19 1162 const char *subname, unsigned int subname_len,
8eb084d0 1163 unsigned int flags, unsigned int type)
b21acc1c
CK		 1164{
1165 struct wm_coeff_ctl *ctl;
1166 struct wmfw_ctl_work *ctl_work;
1167 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
9ce5e6e6 1168 const char *region_name;
b21acc1c
CK		 1169 int ret;
1170
9ce5e6e6
RF		 1171 region_name = wm_adsp_mem_region_name(alg_region->type);
1172 if (!region_name) {
2323736d 1173 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 1174 return -EINVAL;
1175 }
1176
cb5b57a9
CK		 1177 switch (dsp->fw_ver) {
1178 case 0:
1179 case 1:
1180 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1181 dsp->num, region_name, alg_region->alg);
1182 break;
1183 default:
1184 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1185 "DSP%d%c %.12s %x", dsp->num, *region_name,
1186 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1187
1188 /* Truncate the subname from the start if it is too long */
1189 if (subname) {
1190 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1191 int skip = 0;
1192
1193 if (subname_len > avail)
1194 skip = subname_len - avail;
1195
1196 snprintf(name + ret,
1197 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1198 subname_len - skip, subname + skip);
1199 }
1200 break;
1201 }
b21acc1c 1202
7585a5b0 1203 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 1204 if (!strcmp(ctl->name, name)) {
1205 if (!ctl->enabled)
1206 ctl->enabled = 1;
1207 return 0;
1208 }
1209 }
1210
1211 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1212 if (!ctl)
1213 return -ENOMEM;
2323736d 1214 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 1215 ctl->alg_region = *alg_region;
1216 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1217 if (!ctl->name) {
1218 ret = -ENOMEM;
1219 goto err_ctl;
1220 }
1221 ctl->enabled = 1;
1222 ctl->set = 0;
1223 ctl->ops.xget = wm_coeff_get;
1224 ctl->ops.xput = wm_coeff_put;
1225 ctl->dsp = dsp;
1226
26c22a19 1227 ctl->flags = flags;
8eb084d0 1228 ctl->type = type;
2323736d 1229 ctl->offset = offset;
b21acc1c
CK		 1230 ctl->len = len;
1231 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1232 if (!ctl->cache) {
1233 ret = -ENOMEM;
1234 goto err_ctl_name;
1235 }
1236
2323736d
CK		 1237 list_add(&ctl->list, &dsp->ctl_list);
1238
8eb084d0
SH		 1239 if (flags & WMFW_CTL_FLAG_SYS)
1240 return 0;
1241
b21acc1c
CK		 1242 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1243 if (!ctl_work) {
1244 ret = -ENOMEM;
1245 goto err_ctl_cache;
1246 }
1247
1248 ctl_work->dsp = dsp;
1249 ctl_work->ctl = ctl;
1250 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1251 schedule_work(&ctl_work->work);
1252
1253 return 0;
1254
1255err_ctl_cache:
1256 kfree(ctl->cache);
1257err_ctl_name:
1258 kfree(ctl->name);
1259err_ctl:
1260 kfree(ctl);
1261
1262 return ret;
1263}
1264
2323736d
CK		 1265struct wm_coeff_parsed_alg {
1266 int id;
1267 const u8 *name;
1268 int name_len;
1269 int ncoeff;
1270};
1271
1272struct wm_coeff_parsed_coeff {
1273 int offset;
1274 int mem_type;
1275 const u8 *name;
1276 int name_len;
1277 int ctl_type;
1278 int flags;
1279 int len;
1280};
1281
cb5b57a9
CK		 1282static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1283{
1284 int length;
1285
1286 switch (bytes) {
1287 case 1:
1288 length = **pos;
1289 break;
1290 case 2:
8299ee81 1291 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1292 break;
1293 default:
1294 return 0;
1295 }
1296
1297 if (str)
1298 *str = *pos + bytes;
1299
1300 *pos += ((length + bytes) + 3) & ~0x03;
1301
1302 return length;
1303}
1304
1305static int wm_coeff_parse_int(int bytes, const u8 **pos)
1306{
1307 int val = 0;
1308
1309 switch (bytes) {
1310 case 2:
8299ee81 1311 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1312 break;
1313 case 4:
8299ee81 1314 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1315 break;
1316 default:
1317 break;
1318 }
1319
1320 *pos += bytes;
1321
1322 return val;
1323}
1324
2323736d
CK		 1325static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1326 struct wm_coeff_parsed_alg *blk)
1327{
1328 const struct wmfw_adsp_alg_data *raw;
1329
cb5b57a9
CK		 1330 switch (dsp->fw_ver) {
1331 case 0:
1332 case 1:
1333 raw = (const struct wmfw_adsp_alg_data *)*data;
1334 *data = raw->data;
2323736d 1335
cb5b57a9
CK		 1336 blk->id = le32_to_cpu(raw->id);
1337 blk->name = raw->name;
1338 blk->name_len = strlen(raw->name);
1339 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1340 break;
1341 default:
1342 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1343 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1344 &blk->name);
1345 wm_coeff_parse_string(sizeof(u16), data, NULL);
1346 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1347 break;
1348 }
2323736d
CK		 1349
1350 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1351 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1352 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1353}
1354
1355static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1356 struct wm_coeff_parsed_coeff *blk)
1357{
1358 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1359 const u8 *tmp;
1360 int length;
2323736d 1361
cb5b57a9
CK		 1362 switch (dsp->fw_ver) {
1363 case 0:
1364 case 1:
1365 raw = (const struct wmfw_adsp_coeff_data *)*data;
1366 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1367
1368 blk->offset = le16_to_cpu(raw->hdr.offset);
1369 blk->mem_type = le16_to_cpu(raw->hdr.type);
1370 blk->name = raw->name;
1371 blk->name_len = strlen(raw->name);
1372 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1373 blk->flags = le16_to_cpu(raw->flags);
1374 blk->len = le32_to_cpu(raw->len);
1375 break;
1376 default:
1377 tmp = *data;
1378 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1379 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1380 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1381 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1382 &blk->name);
1383 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1384 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1385 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1386 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1387 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1388
1389 *data = *data + sizeof(raw->hdr) + length;
1390 break;
1391 }
2323736d
CK		 1392
1393 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1394 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1395 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1396 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1397 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1398 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1399}
1400
f4f0c4c6
RF		 1401static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1402 const struct wm_coeff_parsed_coeff *coeff_blk,
1403 unsigned int f_required,
1404 unsigned int f_illegal)
1405{
1406 if ((coeff_blk->flags & f_illegal) ||
1407 ((coeff_blk->flags & f_required) != f_required)) {
1408 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1409 coeff_blk->flags, coeff_blk->ctl_type);
1410 return -EINVAL;
1411 }
1412
1413 return 0;
1414}
1415
2323736d
CK		 1416static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1417 const struct wmfw_region *region)
1418{
1419 struct wm_adsp_alg_region alg_region = {};
1420 struct wm_coeff_parsed_alg alg_blk;
1421 struct wm_coeff_parsed_coeff coeff_blk;
1422 const u8 *data = region->data;
1423 int i, ret;
1424
1425 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1426 for (i = 0; i < alg_blk.ncoeff; i++) {
1427 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1428
1429 switch (coeff_blk.ctl_type) {
1430 case SNDRV_CTL_ELEM_TYPE_BYTES:
1431 break;
f4f0c4c6
RF		 1432 case WMFW_CTL_TYPE_HOSTEVENT:
1433 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1434 WMFW_CTL_FLAG_SYS |
1435 WMFW_CTL_FLAG_VOLATILE |
1436 WMFW_CTL_FLAG_WRITEABLE |
1437 WMFW_CTL_FLAG_READABLE,
1438 0);
1439 if (ret)
1440 return -EINVAL;
1441 break;
2323736d
CK		 1442 default:
1443 adsp_err(dsp, "Unknown control type: %d\n",
1444 coeff_blk.ctl_type);
1445 return -EINVAL;
1446 }
1447
1448 alg_region.type = coeff_blk.mem_type;
1449 alg_region.alg = alg_blk.id;
1450
1451 ret = wm_adsp_create_control(dsp, &alg_region,
1452 coeff_blk.offset,
1453 coeff_blk.len,
1454 coeff_blk.name,
26c22a19 1455 coeff_blk.name_len,
8eb084d0
SH		 1456 coeff_blk.flags,
1457 coeff_blk.ctl_type);
2323736d
CK		 1458 if (ret < 0)
1459 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1460 coeff_blk.name_len, coeff_blk.name, ret);
1461 }
1462
1463 return 0;
1464}
1465
2159ad93
MB		 1466static int wm_adsp_load(struct wm_adsp *dsp)
1467{
cf17c83c 1468 LIST_HEAD(buf_list);
2159ad93
MB		 1469 const struct firmware *firmware;
1470 struct regmap *regmap = dsp->regmap;
1471 unsigned int pos = 0;
1472 const struct wmfw_header *header;
1473 const struct wmfw_adsp1_sizes *adsp1_sizes;
1474 const struct wmfw_adsp2_sizes *adsp2_sizes;
1475 const struct wmfw_footer *footer;
1476 const struct wmfw_region *region;
1477 const struct wm_adsp_region *mem;
1478 const char *region_name;
1479 char *file, *text;
cf17c83c 1480 struct wm_adsp_buf *buf;
2159ad93
MB		 1481 unsigned int reg;
1482 int regions = 0;
1483 int ret, offset, type, sizes;
1484
1485 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1486 if (file == NULL)
1487 return -ENOMEM;
1488
1023dbd9
MB		 1489 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1490 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1491 file[PAGE_SIZE - 1] = '\0';
1492
1493 ret = request_firmware(&firmware, file, dsp->dev);
1494 if (ret != 0) {
1495 adsp_err(dsp, "Failed to request '%s'\n", file);
1496 goto out;
1497 }
1498 ret = -EINVAL;
1499
1500 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1501 if (pos >= firmware->size) {
1502 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1503 file, firmware->size);
1504 goto out_fw;
1505 }
1506
7585a5b0 1507 header = (void *)&firmware->data[0];
2159ad93
MB		 1508
1509 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1510 adsp_err(dsp, "%s: invalid magic\n", file);
1511 goto out_fw;
1512 }
1513
2323736d
CK		 1514 switch (header->ver) {
1515 case 0:
c61e59fe
CK		 1516 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1517 file, header->ver);
1518 break;
2323736d 1519 case 1:
cb5b57a9 1520 case 2:
2323736d
CK		 1521 break;
1522 default:
2159ad93
MB		 1523 adsp_err(dsp, "%s: unknown file format %d\n",
1524 file, header->ver);
1525 goto out_fw;
1526 }
2323736d 1527
3626992a 1528 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1529 dsp->fw_ver = header->ver;
2159ad93
MB		 1530
1531 if (header->core != dsp->type) {
1532 adsp_err(dsp, "%s: invalid core %d != %d\n",
1533 file, header->core, dsp->type);
1534 goto out_fw;
1535 }
1536
1537 switch (dsp->type) {
1538 case WMFW_ADSP1:
1539 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1540 adsp1_sizes = (void *)&(header[1]);
1541 footer = (void *)&(adsp1_sizes[1]);
1542 sizes = sizeof(*adsp1_sizes);
1543
1544 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1545 file, le32_to_cpu(adsp1_sizes->dm),
1546 le32_to_cpu(adsp1_sizes->pm),
1547 le32_to_cpu(adsp1_sizes->zm));
1548 break;
1549
1550 case WMFW_ADSP2:
1551 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1552 adsp2_sizes = (void *)&(header[1]);
1553 footer = (void *)&(adsp2_sizes[1]);
1554 sizes = sizeof(*adsp2_sizes);
1555
1556 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1557 file, le32_to_cpu(adsp2_sizes->xm),
1558 le32_to_cpu(adsp2_sizes->ym),
1559 le32_to_cpu(adsp2_sizes->pm),
1560 le32_to_cpu(adsp2_sizes->zm));
1561 break;
1562
1563 default:
6c452bda 1564 WARN(1, "Unknown DSP type");
2159ad93
MB		 1565 goto out_fw;
1566 }
1567
1568 if (le32_to_cpu(header->len) != sizeof(*header) +
1569 sizes + sizeof(*footer)) {
1570 adsp_err(dsp, "%s: unexpected header length %d\n",
1571 file, le32_to_cpu(header->len));
1572 goto out_fw;
1573 }
1574
1575 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1576 le64_to_cpu(footer->timestamp));
1577
1578 while (pos < firmware->size &&
1579 pos - firmware->size > sizeof(*region)) {
1580 region = (void *)&(firmware->data[pos]);
1581 region_name = "Unknown";
1582 reg = 0;
1583 text = NULL;
1584 offset = le32_to_cpu(region->offset) & 0xffffff;
1585 type = be32_to_cpu(region->type) & 0xff;
1586 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1587
2159ad93
MB		 1588 switch (type) {
1589 case WMFW_NAME_TEXT:
1590 region_name = "Firmware name";
1591 text = kzalloc(le32_to_cpu(region->len) + 1,
1592 GFP_KERNEL);
1593 break;
2323736d
CK		 1594 case WMFW_ALGORITHM_DATA:
1595 region_name = "Algorithm";
1596 ret = wm_adsp_parse_coeff(dsp, region);
1597 if (ret != 0)
1598 goto out_fw;
1599 break;
2159ad93
MB		 1600 case WMFW_INFO_TEXT:
1601 region_name = "Information";
1602 text = kzalloc(le32_to_cpu(region->len) + 1,
1603 GFP_KERNEL);
1604 break;
1605 case WMFW_ABSOLUTE:
1606 region_name = "Absolute";
1607 reg = offset;
1608 break;
1609 case WMFW_ADSP1_PM:
2159ad93 1610 case WMFW_ADSP1_DM:
2159ad93 1611 case WMFW_ADSP2_XM:
2159ad93 1612 case WMFW_ADSP2_YM:
2159ad93 1613 case WMFW_ADSP1_ZM:
9ce5e6e6 1614 region_name = wm_adsp_mem_region_name(type);
45b9ee72 1615 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1616 break;
1617 default:
1618 adsp_warn(dsp,
1619 "%s.%d: Unknown region type %x at %d(%x)\n",
1620 file, regions, type, pos, pos);
1621 break;
1622 }
1623
1624 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1625 regions, le32_to_cpu(region->len), offset,
1626 region_name);
1627
1628 if (text) {
1629 memcpy(text, region->data, le32_to_cpu(region->len));
1630 adsp_info(dsp, "%s: %s\n", file, text);
1631 kfree(text);
1632 }
1633
1634 if (reg) {
cdcd7f72
CK		 1635 buf = wm_adsp_buf_alloc(region->data,
1636 le32_to_cpu(region->len),
1637 &buf_list);
1638 if (!buf) {
1639 adsp_err(dsp, "Out of memory\n");
1640 ret = -ENOMEM;
1641 goto out_fw;
1642 }
c1a7898d 1643
cdcd7f72
CK		 1644 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1645 le32_to_cpu(region->len));
1646 if (ret != 0) {
1647 adsp_err(dsp,
1648 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1649 file, regions,
1650 le32_to_cpu(region->len), offset,
1651 region_name, ret);
1652 goto out_fw;
2159ad93
MB		 1653 }
1654 }
1655
1656 pos += le32_to_cpu(region->len) + sizeof(*region);
1657 regions++;
1658 }
cf17c83c
MB		 1659
1660 ret = regmap_async_complete(regmap);
1661 if (ret != 0) {
1662 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1663 goto out_fw;
1664 }
1665
2159ad93
MB		 1666 if (pos > firmware->size)
1667 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1668 file, regions, pos - firmware->size);
1669
f9f55e31
RF		 1670 wm_adsp_debugfs_save_wmfwname(dsp, file);
1671
2159ad93 1672out_fw:
cf17c83c
MB		 1673 regmap_async_complete(regmap);
1674 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1675 release_firmware(firmware);
1676out:
1677 kfree(file);
1678
1679 return ret;
1680}
1681
2323736d
CK		 1682static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1683 const struct wm_adsp_alg_region *alg_region)
1684{
1685 struct wm_coeff_ctl *ctl;
1686
1687 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1688 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1689 alg_region->alg == ctl->alg_region.alg &&
1690 alg_region->type == ctl->alg_region.type) {
1691 ctl->alg_region.base = alg_region->base;
1692 }
1693 }
1694}
1695
3809f001 1696static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1697 unsigned int pos, unsigned int len)
db40517c 1698{
b618a185
CK		 1699 void *alg;
1700 int ret;
db40517c 1701 __be32 val;
db40517c 1702
3809f001 1703 if (n_algs == 0) {
b618a185
CK		 1704 adsp_err(dsp, "No algorithms\n");
1705 return ERR_PTR(-EINVAL);
db40517c
MB		 1706 }
1707
3809f001
CK		 1708 if (n_algs > 1024) {
1709 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1710 return ERR_PTR(-EINVAL);
1711 }
db40517c 1712
b618a185
CK		 1713 /* Read the terminator first to validate the length */
1714 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1715 if (ret != 0) {
1716 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1717 ret);
1718 return ERR_PTR(ret);
1719 }
db40517c 1720
b618a185
CK		 1721 if (be32_to_cpu(val) != 0xbedead)
1722 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1723 pos + len, be32_to_cpu(val));
d62f4bc6 1724
b618a185
CK		 1725 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1726 if (!alg)
1727 return ERR_PTR(-ENOMEM);
db40517c 1728
b618a185
CK		 1729 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1730 if (ret != 0) {
7d00cd97 1731 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
b618a185
CK		 1732 kfree(alg);
1733 return ERR_PTR(ret);
1734 }
ac50009f 1735
b618a185
CK		 1736 return alg;
1737}
ac50009f 1738
14197095
CK		 1739static struct wm_adsp_alg_region *
1740 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1741{
1742 struct wm_adsp_alg_region *alg_region;
1743
1744 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1745 if (id == alg_region->alg && type == alg_region->type)
1746 return alg_region;
1747 }
1748
1749 return NULL;
1750}
1751
d9d20e17
CK		 1752static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1753 int type, __be32 id,
1754 __be32 base)
1755{
1756 struct wm_adsp_alg_region *alg_region;
1757
1758 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1759 if (!alg_region)
1760 return ERR_PTR(-ENOMEM);
1761
1762 alg_region->type = type;
1763 alg_region->alg = be32_to_cpu(id);
1764 alg_region->base = be32_to_cpu(base);
1765
1766 list_add_tail(&alg_region->list, &dsp->alg_regions);
1767
2323736d
CK		 1768 if (dsp->fw_ver > 0)
1769 wm_adsp_ctl_fixup_base(dsp, alg_region);
1770
d9d20e17
CK		 1771 return alg_region;
1772}
1773
56574d54
RF		 1774static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1775{
1776 struct wm_adsp_alg_region *alg_region;
1777
1778 while (!list_empty(&dsp->alg_regions)) {
1779 alg_region = list_first_entry(&dsp->alg_regions,
1780 struct wm_adsp_alg_region,
1781 list);
1782 list_del(&alg_region->list);
1783 kfree(alg_region);
1784 }
1785}
1786
b618a185
CK		 1787static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1788{
1789 struct wmfw_adsp1_id_hdr adsp1_id;
1790 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1791 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1792 const struct wm_adsp_region *mem;
1793 unsigned int pos, len;
3809f001 1794 size_t n_algs;
b618a185 1795 int i, ret;
db40517c 1796
b618a185
CK		 1797 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1798 if (WARN_ON(!mem))
1799 return -EINVAL;
1800
1801 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1802 sizeof(adsp1_id));
1803 if (ret != 0) {
1804 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1805 ret);
1806 return ret;
1807 }
db40517c 1808
3809f001 1809 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1810 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1811 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1812 dsp->fw_id,
1813 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1814 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1815 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1816 n_algs);
b618a185 1817
d9d20e17
CK		 1818 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1819 adsp1_id.fw.id, adsp1_id.zm);
1820 if (IS_ERR(alg_region))
1821 return PTR_ERR(alg_region);
d62f4bc6 1822
d9d20e17
CK		 1823 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1824 adsp1_id.fw.id, adsp1_id.dm);
1825 if (IS_ERR(alg_region))
1826 return PTR_ERR(alg_region);
db40517c 1827
b618a185 1828 pos = sizeof(adsp1_id) / 2;
3809f001 1829 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1830
3809f001 1831 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1832 if (IS_ERR(adsp1_alg))
1833 return PTR_ERR(adsp1_alg);
1834
3809f001 1835 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1836 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1837 i, be32_to_cpu(adsp1_alg[i].alg.id),
1838 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1839 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1840 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1841 be32_to_cpu(adsp1_alg[i].dm),
1842 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1843
d9d20e17
CK		 1844 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1845 adsp1_alg[i].alg.id,
1846 adsp1_alg[i].dm);
1847 if (IS_ERR(alg_region)) {
1848 ret = PTR_ERR(alg_region);
b618a185
CK		 1849 goto out;
1850 }
2323736d
CK		 1851 if (dsp->fw_ver == 0) {
1852 if (i + 1 < n_algs) {
1853 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1854 len -= be32_to_cpu(adsp1_alg[i].dm);
1855 len *= 4;
1856 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 1857 len, NULL, 0, 0,
1858 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 1859 } else {
1860 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1861 be32_to_cpu(adsp1_alg[i].alg.id));
1862 }
b618a185 1863 }
ac50009f 1864
d9d20e17
CK		 1865 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1866 adsp1_alg[i].alg.id,
1867 adsp1_alg[i].zm);
1868 if (IS_ERR(alg_region)) {
1869 ret = PTR_ERR(alg_region);
b618a185
CK		 1870 goto out;
1871 }
2323736d
CK		 1872 if (dsp->fw_ver == 0) {
1873 if (i + 1 < n_algs) {
1874 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1875 len -= be32_to_cpu(adsp1_alg[i].zm);
1876 len *= 4;
1877 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 1878 len, NULL, 0, 0,
1879 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 1880 } else {
1881 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1882 be32_to_cpu(adsp1_alg[i].alg.id));
1883 }
b618a185 1884 }
db40517c
MB		 1885 }
1886
b618a185
CK		 1887out:
1888 kfree(adsp1_alg);
1889 return ret;
1890}
db40517c 1891
b618a185
CK		 1892static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1893{
1894 struct wmfw_adsp2_id_hdr adsp2_id;
1895 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1896 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1897 const struct wm_adsp_region *mem;
1898 unsigned int pos, len;
3809f001 1899 size_t n_algs;
b618a185
CK		 1900 int i, ret;
1901
1902 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1903 if (WARN_ON(!mem))
d62f4bc6 1904 return -EINVAL;
d62f4bc6 1905
b618a185
CK		 1906 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1907 sizeof(adsp2_id));
db40517c 1908 if (ret != 0) {
b618a185
CK		 1909 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1910 ret);
db40517c
MB		 1911 return ret;
1912 }
1913
3809f001 1914 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1915 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1916 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1917 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1918 dsp->fw_id,
f9f55e31
RF		 1919 (dsp->fw_id_version & 0xff0000) >> 16,
1920 (dsp->fw_id_version & 0xff00) >> 8,
1921 dsp->fw_id_version & 0xff,
3809f001 1922 n_algs);
b618a185 1923
d9d20e17
CK		 1924 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1925 adsp2_id.fw.id, adsp2_id.xm);
1926 if (IS_ERR(alg_region))
1927 return PTR_ERR(alg_region);
db40517c 1928
d9d20e17
CK		 1929 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1930 adsp2_id.fw.id, adsp2_id.ym);
1931 if (IS_ERR(alg_region))
1932 return PTR_ERR(alg_region);
db40517c 1933
d9d20e17
CK		 1934 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1935 adsp2_id.fw.id, adsp2_id.zm);
1936 if (IS_ERR(alg_region))
1937 return PTR_ERR(alg_region);
db40517c 1938
b618a185 1939 pos = sizeof(adsp2_id) / 2;
3809f001 1940 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1941
3809f001 1942 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1943 if (IS_ERR(adsp2_alg))
1944 return PTR_ERR(adsp2_alg);
471f4885 1945
3809f001 1946 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1947 adsp_info(dsp,
1948 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1949 i, be32_to_cpu(adsp2_alg[i].alg.id),
1950 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1951 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1952 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1953 be32_to_cpu(adsp2_alg[i].xm),
1954 be32_to_cpu(adsp2_alg[i].ym),
1955 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1956
d9d20e17
CK		 1957 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1958 adsp2_alg[i].alg.id,
1959 adsp2_alg[i].xm);
1960 if (IS_ERR(alg_region)) {
1961 ret = PTR_ERR(alg_region);
b618a185
CK		 1962 goto out;
1963 }
2323736d
CK		 1964 if (dsp->fw_ver == 0) {
1965 if (i + 1 < n_algs) {
1966 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1967 len -= be32_to_cpu(adsp2_alg[i].xm);
1968 len *= 4;
1969 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 1970 len, NULL, 0, 0,
1971 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 1972 } else {
1973 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1974 be32_to_cpu(adsp2_alg[i].alg.id));
1975 }
b618a185 1976 }
471f4885 1977
d9d20e17
CK		 1978 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1979 adsp2_alg[i].alg.id,
1980 adsp2_alg[i].ym);
1981 if (IS_ERR(alg_region)) {
1982 ret = PTR_ERR(alg_region);
b618a185
CK		 1983 goto out;
1984 }
2323736d
CK		 1985 if (dsp->fw_ver == 0) {
1986 if (i + 1 < n_algs) {
1987 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1988 len -= be32_to_cpu(adsp2_alg[i].ym);
1989 len *= 4;
1990 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 1991 len, NULL, 0, 0,
1992 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 1993 } else {
1994 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1995 be32_to_cpu(adsp2_alg[i].alg.id));
1996 }
b618a185 1997 }
471f4885 1998
d9d20e17
CK		 1999 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2000 adsp2_alg[i].alg.id,
2001 adsp2_alg[i].zm);
2002 if (IS_ERR(alg_region)) {
2003 ret = PTR_ERR(alg_region);
b618a185
CK		 2004 goto out;
2005 }
2323736d
CK		 2006 if (dsp->fw_ver == 0) {
2007 if (i + 1 < n_algs) {
2008 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2009 len -= be32_to_cpu(adsp2_alg[i].zm);
2010 len *= 4;
2011 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2012 len, NULL, 0, 0,
2013 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2014 } else {
2015 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2016 be32_to_cpu(adsp2_alg[i].alg.id));
2017 }
db40517c
MB		 2018 }
2019 }
2020
2021out:
b618a185 2022 kfree(adsp2_alg);
db40517c
MB		 2023 return ret;
2024}
2025
2159ad93
MB		 2026static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2027{
cf17c83c 2028 LIST_HEAD(buf_list);
2159ad93
MB		 2029 struct regmap *regmap = dsp->regmap;
2030 struct wmfw_coeff_hdr *hdr;
2031 struct wmfw_coeff_item *blk;
2032 const struct firmware *firmware;
471f4885
MB		 2033 const struct wm_adsp_region *mem;
2034 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 2035 const char *region_name;
2036 int ret, pos, blocks, type, offset, reg;
2037 char *file;
cf17c83c 2038 struct wm_adsp_buf *buf;
2159ad93
MB		 2039
2040 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2041 if (file == NULL)
2042 return -ENOMEM;
2043
1023dbd9
MB		 2044 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2045 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 2046 file[PAGE_SIZE - 1] = '\0';
2047
2048 ret = request_firmware(&firmware, file, dsp->dev);
2049 if (ret != 0) {
2050 adsp_warn(dsp, "Failed to request '%s'\n", file);
2051 ret = 0;
2052 goto out;
2053 }
2054 ret = -EINVAL;
2055
2056 if (sizeof(*hdr) >= firmware->size) {
2057 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2058 file, firmware->size);
2059 goto out_fw;
2060 }
2061
7585a5b0 2062 hdr = (void *)&firmware->data[0];
2159ad93
MB		 2063 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2064 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 2065 goto out_fw;
2159ad93
MB		 2066 }
2067
c712326d
MB		 2068 switch (be32_to_cpu(hdr->rev) & 0xff) {
2069 case 1:
2070 break;
2071 default:
2072 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2073 file, be32_to_cpu(hdr->rev) & 0xff);
2074 ret = -EINVAL;
2075 goto out_fw;
2076 }
2077
2159ad93
MB		 2078 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2079 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2080 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2081 le32_to_cpu(hdr->ver) & 0xff);
2082
2083 pos = le32_to_cpu(hdr->len);
2084
2085 blocks = 0;
2086 while (pos < firmware->size &&
2087 pos - firmware->size > sizeof(*blk)) {
7585a5b0 2088 blk = (void *)(&firmware->data[pos]);
2159ad93 2089
c712326d
MB		 2090 type = le16_to_cpu(blk->type);
2091 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 2092
2093 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2094 file, blocks, le32_to_cpu(blk->id),
2095 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2096 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2097 le32_to_cpu(blk->ver) & 0xff);
2098 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2099 file, blocks, le32_to_cpu(blk->len), offset, type);
2100
2101 reg = 0;
2102 region_name = "Unknown";
2103 switch (type) {
c712326d
MB		 2104 case (WMFW_NAME_TEXT << 8):
2105 case (WMFW_INFO_TEXT << 8):
2159ad93 2106 break;
c712326d 2107 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 2108 /*
2109 * Old files may use this for global
2110 * coefficients.
2111 */
2112 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2113 offset == 0) {
2114 region_name = "global coefficients";
2115 mem = wm_adsp_find_region(dsp, type);
2116 if (!mem) {
2117 adsp_err(dsp, "No ZM\n");
2118 break;
2119 }
2120 reg = wm_adsp_region_to_reg(mem, 0);
2121
2122 } else {
2123 region_name = "register";
2124 reg = offset;
2125 }
2159ad93 2126 break;
471f4885
MB		 2127
2128 case WMFW_ADSP1_DM:
2129 case WMFW_ADSP1_ZM:
2130 case WMFW_ADSP2_XM:
2131 case WMFW_ADSP2_YM:
2132 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2133 file, blocks, le32_to_cpu(blk->len),
2134 type, le32_to_cpu(blk->id));
2135
2136 mem = wm_adsp_find_region(dsp, type);
2137 if (!mem) {
2138 adsp_err(dsp, "No base for region %x\n", type);
2139 break;
2140 }
2141
14197095
CK		 2142 alg_region = wm_adsp_find_alg_region(dsp, type,
2143 le32_to_cpu(blk->id));
2144 if (alg_region) {
2145 reg = alg_region->base;
2146 reg = wm_adsp_region_to_reg(mem, reg);
2147 reg += offset;
2148 } else {
471f4885
MB		 2149 adsp_err(dsp, "No %x for algorithm %x\n",
2150 type, le32_to_cpu(blk->id));
14197095 2151 }
471f4885
MB		 2152 break;
2153
2159ad93 2154 default:
25c62f7e
MB		 2155 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2156 file, blocks, type, pos);
2159ad93
MB		 2157 break;
2158 }
2159
2160 if (reg) {
cf17c83c
MB		 2161 buf = wm_adsp_buf_alloc(blk->data,
2162 le32_to_cpu(blk->len),
2163 &buf_list);
a76fefab
MB		 2164 if (!buf) {
2165 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 2166 ret = -ENOMEM;
2167 goto out_fw;
a76fefab
MB		 2168 }
2169
20da6d5a
MB		 2170 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2171 file, blocks, le32_to_cpu(blk->len),
2172 reg);
cf17c83c
MB		 2173 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2174 le32_to_cpu(blk->len));
2159ad93
MB		 2175 if (ret != 0) {
2176 adsp_err(dsp,
43bc3bf6
DP		 2177 "%s.%d: Failed to write to %x in %s: %d\n",
2178 file, blocks, reg, region_name, ret);
2159ad93
MB		 2179 }
2180 }
2181
be951017 2182 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 2183 blocks++;
2184 }
2185
cf17c83c
MB		 2186 ret = regmap_async_complete(regmap);
2187 if (ret != 0)
2188 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2189
2159ad93
MB		 2190 if (pos > firmware->size)
2191 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2192 file, blocks, pos - firmware->size);
2193
f9f55e31
RF		 2194 wm_adsp_debugfs_save_binname(dsp, file);
2195
2159ad93 2196out_fw:
9da7a5a9 2197 regmap_async_complete(regmap);
2159ad93 2198 release_firmware(firmware);
cf17c83c 2199 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 2200out:
2201 kfree(file);
f4b82812 2202 return ret;
2159ad93
MB		 2203}
2204
3809f001 2205int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 2206{
3809f001 2207 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 2208
078e7183
CK		 2209 mutex_init(&dsp->pwr_lock);
2210
5e7a7a22
MB		 2211 return 0;
2212}
2213EXPORT_SYMBOL_GPL(wm_adsp1_init);
2214
2159ad93
MB		 2215int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2216 struct snd_kcontrol *kcontrol,
2217 int event)
2218{
72718517 2219 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 2220 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2221 struct wm_adsp *dsp = &dsps[w->shift];
6ab2b7b4 2222 struct wm_coeff_ctl *ctl;
2159ad93 2223 int ret;
7585a5b0 2224 unsigned int val;
2159ad93 2225
00200107 2226 dsp->card = codec->component.card;
92bb4c32 2227
078e7183
CK		 2228 mutex_lock(&dsp->pwr_lock);
2229
2159ad93
MB		 2230 switch (event) {
2231 case SND_SOC_DAPM_POST_PMU:
2232 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2233 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2234
94e205bf
CR		 2235 /*
2236 * For simplicity set the DSP clock rate to be the
2237 * SYSCLK rate rather than making it configurable.
2238 */
7585a5b0 2239 if (dsp->sysclk_reg) {
94e205bf
CR		 2240 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2241 if (ret != 0) {
2242 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2243 ret);
078e7183 2244 goto err_mutex;
94e205bf
CR		 2245 }
2246
7d00cd97 2247 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
94e205bf
CR		 2248
2249 ret = regmap_update_bits(dsp->regmap,
2250 dsp->base + ADSP1_CONTROL_31,
2251 ADSP1_CLK_SEL_MASK, val);
2252 if (ret != 0) {
2253 adsp_err(dsp, "Failed to set clock rate: %d\n",
2254 ret);
078e7183 2255 goto err_mutex;
94e205bf
CR		 2256 }
2257 }
2258
2159ad93
MB		 2259 ret = wm_adsp_load(dsp);
2260 if (ret != 0)
078e7183 2261 goto err_ena;
2159ad93 2262
b618a185 2263 ret = wm_adsp1_setup_algs(dsp);
db40517c 2264 if (ret != 0)
078e7183 2265 goto err_ena;
db40517c 2266
2159ad93
MB		 2267 ret = wm_adsp_load_coeff(dsp);
2268 if (ret != 0)
078e7183 2269 goto err_ena;
2159ad93 2270
0c2e3f34 2271 /* Initialize caches for enabled and unset controls */
81ad93ec 2272 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2273 if (ret != 0)
078e7183 2274 goto err_ena;
6ab2b7b4 2275
0c2e3f34 2276 /* Sync set controls */
81ad93ec 2277 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2278 if (ret != 0)
078e7183 2279 goto err_ena;
6ab2b7b4 2280
28823eba
CK		 2281 dsp->booted = true;
2282
2159ad93
MB		 2283 /* Start the core running */
2284 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2285 ADSP1_CORE_ENA | ADSP1_START,
2286 ADSP1_CORE_ENA | ADSP1_START);
28823eba
CK		 2287
2288 dsp->running = true;
2159ad93
MB		 2289 break;
2290
2291 case SND_SOC_DAPM_PRE_PMD:
28823eba
CK		 2292 dsp->running = false;
2293 dsp->booted = false;
2294
2159ad93
MB		 2295 /* Halt the core */
2296 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2297 ADSP1_CORE_ENA | ADSP1_START, 0);
2298
2299 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2300 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2301
2302 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2303 ADSP1_SYS_ENA, 0);
6ab2b7b4 2304
81ad93ec 2305 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2306 ctl->enabled = 0;
b0101b4f 2307
56574d54
RF		 2308
2309 wm_adsp_free_alg_regions(dsp);
2159ad93
MB		 2310 break;
2311
2312 default:
2313 break;
2314 }
2315
078e7183
CK		 2316 mutex_unlock(&dsp->pwr_lock);
2317
2159ad93
MB		 2318 return 0;
2319
078e7183 2320err_ena:
2159ad93
MB		 2321 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2322 ADSP1_SYS_ENA, 0);
078e7183
CK		 2323err_mutex:
2324 mutex_unlock(&dsp->pwr_lock);
2325
2159ad93
MB		 2326 return ret;
2327}
2328EXPORT_SYMBOL_GPL(wm_adsp1_event);
2329
2330static int wm_adsp2_ena(struct wm_adsp *dsp)
2331{
2332 unsigned int val;
2333 int ret, count;
2334
1552c325
MB		 2335 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2336 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 2337 if (ret != 0)
2338 return ret;
2339
2340 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2341 for (count = 0; count < 10; ++count) {
7d00cd97 2342 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2159ad93
MB		 2343 if (ret != 0)
2344 return ret;
939fd1e8
CK		 2345
2346 if (val & ADSP2_RAM_RDY)
2347 break;
2348
1fa96f3f 2349 usleep_range(250, 500);
939fd1e8 2350 }
2159ad93
MB		 2351
2352 if (!(val & ADSP2_RAM_RDY)) {
2353 adsp_err(dsp, "Failed to start DSP RAM\n");
2354 return -EBUSY;
2355 }
2356
2357 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2358
2359 return 0;
2360}
2361
18b1a902 2362static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2363{
d8a64d6a
CK		 2364 struct wm_adsp *dsp = container_of(work,
2365 struct wm_adsp,
2366 boot_work);
2159ad93
MB		 2367 int ret;
2368
078e7183
CK		 2369 mutex_lock(&dsp->pwr_lock);
2370
90d19ba5
CK		 2371 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2372 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2373 if (ret != 0)
2374 goto err_mutex;
2375
d8a64d6a
CK		 2376 ret = wm_adsp2_ena(dsp);
2377 if (ret != 0)
078e7183 2378 goto err_mutex;
2159ad93 2379
d8a64d6a
CK		 2380 ret = wm_adsp_load(dsp);
2381 if (ret != 0)
078e7183 2382 goto err_ena;
2159ad93 2383
b618a185 2384 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2385 if (ret != 0)
078e7183 2386 goto err_ena;
db40517c 2387
d8a64d6a
CK		 2388 ret = wm_adsp_load_coeff(dsp);
2389 if (ret != 0)
078e7183 2390 goto err_ena;
2159ad93 2391
d8a64d6a
CK		 2392 /* Initialize caches for enabled and unset controls */
2393 ret = wm_coeff_init_control_caches(dsp);
2394 if (ret != 0)
078e7183 2395 goto err_ena;
6ab2b7b4 2396
28823eba 2397 dsp->booted = true;
d8a64d6a 2398
90d19ba5
CK		 2399 /* Turn DSP back off until we are ready to run */
2400 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2401 ADSP2_SYS_ENA, 0);
2402 if (ret != 0)
2403 goto err_ena;
2404
078e7183
CK		 2405 mutex_unlock(&dsp->pwr_lock);
2406
d8a64d6a 2407 return;
6ab2b7b4 2408
078e7183 2409err_ena:
d8a64d6a
CK		 2410 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2411 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2412err_mutex:
2413 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2414}
2415
d82d767f
CK		 2416static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2417{
2418 int ret;
2419
2420 ret = regmap_update_bits_async(dsp->regmap,
2421 dsp->base + ADSP2_CLOCKING,
2422 ADSP2_CLK_SEL_MASK,
2423 freq << ADSP2_CLK_SEL_SHIFT);
2424 if (ret != 0)
2425 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2426}
2427
12db5edd 2428int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
d82d767f
CK		 2429 struct snd_kcontrol *kcontrol, int event,
2430 unsigned int freq)
12db5edd 2431{
72718517 2432 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2433 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2434 struct wm_adsp *dsp = &dsps[w->shift];
57a60cc3 2435 struct wm_coeff_ctl *ctl;
12db5edd 2436
00200107 2437 dsp->card = codec->component.card;
12db5edd
CK		 2438
2439 switch (event) {
2440 case SND_SOC_DAPM_PRE_PMU:
d82d767f 2441 wm_adsp2_set_dspclk(dsp, freq);
12db5edd
CK		 2442 queue_work(system_unbound_wq, &dsp->boot_work);
2443 break;
57a60cc3
CK		 2444 case SND_SOC_DAPM_PRE_PMD:
2445 wm_adsp_debugfs_clear(dsp);
2446
2447 dsp->fw_id = 0;
2448 dsp->fw_id_version = 0;
2449
2450 dsp->booted = false;
2451
2452 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2453 ADSP2_MEM_ENA, 0);
2454
2455 list_for_each_entry(ctl, &dsp->ctl_list, list)
2456 ctl->enabled = 0;
2457
2458 wm_adsp_free_alg_regions(dsp);
2459
2460 adsp_dbg(dsp, "Shutdown complete\n");
2461 break;
12db5edd
CK		 2462 default:
2463 break;
cab27258 2464 }
12db5edd
CK		 2465
2466 return 0;
2467}
2468EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2469
d8a64d6a
CK		 2470int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2471 struct snd_kcontrol *kcontrol, int event)
2472{
72718517 2473 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2474 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2475 struct wm_adsp *dsp = &dsps[w->shift];
d8a64d6a
CK		 2476 int ret;
2477
d8a64d6a
CK		 2478 switch (event) {
2479 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2480 flush_work(&dsp->boot_work);
2481
28823eba 2482 if (!dsp->booted)
d8a64d6a 2483 return -EIO;
6ab2b7b4 2484
90d19ba5
CK		 2485 ret = wm_adsp2_ena(dsp);
2486 if (ret != 0)
2487 goto err;
2488
cef45771
CK		 2489 /* Sync set controls */
2490 ret = wm_coeff_sync_controls(dsp);
2491 if (ret != 0)
2492 goto err;
2493
d8a64d6a
CK		 2494 ret = regmap_update_bits(dsp->regmap,
2495 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2496 ADSP2_CORE_ENA | ADSP2_START,
2497 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2498 if (ret != 0)
2499 goto err;
2cd19bdb 2500
28823eba
CK		 2501 dsp->running = true;
2502
612047f0
CK		 2503 mutex_lock(&dsp->pwr_lock);
2504
2cd19bdb
CK		 2505 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2506 ret = wm_adsp_buffer_init(dsp);
2507
612047f0
CK		 2508 mutex_unlock(&dsp->pwr_lock);
2509
2159ad93
MB		 2510 break;
2511
2512 case SND_SOC_DAPM_PRE_PMD:
f4f0c4c6
RF		 2513 /* Tell the firmware to cleanup */
2514 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2515
10337b07
RF		 2516 /* Log firmware state, it can be useful for analysis */
2517 wm_adsp2_show_fw_status(dsp);
2518
078e7183
CK		 2519 mutex_lock(&dsp->pwr_lock);
2520
1023dbd9
MB		 2521 dsp->running = false;
2522
2159ad93 2523 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
57a60cc3 2524 ADSP2_CORE_ENA | ADSP2_START, 0);
973838a0 2525
2d30b575 2526 /* Make sure DMAs are quiesced */
6facd2d1 2527 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2d30b575
MB		 2528 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2529 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
6facd2d1
ST		 2530
2531 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2532 ADSP2_SYS_ENA, 0);
2d30b575 2533
2cd19bdb
CK		 2534 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2535 wm_adsp_buffer_free(dsp);
2536
078e7183
CK		 2537 mutex_unlock(&dsp->pwr_lock);
2538
57a60cc3 2539 adsp_dbg(dsp, "Execution stopped\n");
2159ad93
MB		 2540 break;
2541
2542 default:
2543 break;
2544 }
2545
2546 return 0;
2547err:
2548 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2549 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2550 return ret;
2551}
2552EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2553
f5e2ce92
RF		 2554int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2555{
f9f55e31
RF		 2556 wm_adsp2_init_debugfs(dsp, codec);
2557
218e5087 2558 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2559 &wm_adsp_fw_controls[dsp->num - 1],
2560 1);
f5e2ce92
RF		 2561}
2562EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2563
2564int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2565{
f9f55e31
RF		 2566 wm_adsp2_cleanup_debugfs(dsp);
2567
f5e2ce92
RF		 2568 return 0;
2569}
2570EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2571
81ac58b1 2572int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2573{
2574 int ret;
2575
10a2b662
MB		 2576 /*
2577 * Disable the DSP memory by default when in reset for a small
2578 * power saving.
2579 */
3809f001 2580 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2581 ADSP2_MEM_ENA, 0);
2582 if (ret != 0) {
3809f001 2583 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2584 return ret;
2585 }
2586
3809f001
CK		 2587 INIT_LIST_HEAD(&dsp->alg_regions);
2588 INIT_LIST_HEAD(&dsp->ctl_list);
2589 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2590
078e7183
CK		 2591 mutex_init(&dsp->pwr_lock);
2592
973838a0
MB		 2593 return 0;
2594}
2595EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2596
66225e98
RF		 2597void wm_adsp2_remove(struct wm_adsp *dsp)
2598{
2599 struct wm_coeff_ctl *ctl;
2600
2601 while (!list_empty(&dsp->ctl_list)) {
2602 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2603 list);
2604 list_del(&ctl->list);
2605 wm_adsp_free_ctl_blk(ctl);
2606 }
2607}
2608EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2609
edd71350
CK		 2610static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2611{
2612 return compr->buf != NULL;
2613}
2614
2615static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2616{
2617 /*
2618 * Note this will be more complex once each DSP can support multiple
2619 * streams
2620 */
2621 if (!compr->dsp->buffer)
2622 return -EINVAL;
2623
2624 compr->buf = compr->dsp->buffer;
721be3be 2625 compr->buf->compr = compr;
edd71350
CK		 2626
2627 return 0;
2628}
2629
721be3be
CK		 2630static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2631{
2632 if (!compr)
2633 return;
2634
2635 /* Wake the poll so it can see buffer is no longer attached */
2636 if (compr->stream)
2637 snd_compr_fragment_elapsed(compr->stream);
2638
2639 if (wm_adsp_compr_attached(compr)) {
2640 compr->buf->compr = NULL;
2641 compr->buf = NULL;
2642 }
2643}
2644
406abc95
CK		 2645int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2646{
2647 struct wm_adsp_compr *compr;
2648 int ret = 0;
2649
2650 mutex_lock(&dsp->pwr_lock);
2651
2652 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2653 adsp_err(dsp, "Firmware does not support compressed API\n");
2654 ret = -ENXIO;
2655 goto out;
2656 }
2657
2658 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2659 adsp_err(dsp, "Firmware does not support stream direction\n");
2660 ret = -EINVAL;
2661 goto out;
2662 }
2663
95fe9597
CK		 2664 if (dsp->compr) {
2665 /* It is expect this limitation will be removed in future */
2666 adsp_err(dsp, "Only a single stream supported per DSP\n");
2667 ret = -EBUSY;
2668 goto out;
2669 }
2670
406abc95
CK		 2671 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2672 if (!compr) {
2673 ret = -ENOMEM;
2674 goto out;
2675 }
2676
2677 compr->dsp = dsp;
2678 compr->stream = stream;
2679
2680 dsp->compr = compr;
2681
2682 stream->runtime->private_data = compr;
2683
2684out:
2685 mutex_unlock(&dsp->pwr_lock);
2686
2687 return ret;
2688}
2689EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2690
2691int wm_adsp_compr_free(struct snd_compr_stream *stream)
2692{
2693 struct wm_adsp_compr *compr = stream->runtime->private_data;
2694 struct wm_adsp *dsp = compr->dsp;
2695
2696 mutex_lock(&dsp->pwr_lock);
2697
721be3be 2698 wm_adsp_compr_detach(compr);
406abc95
CK		 2699 dsp->compr = NULL;
2700
83a40ce9 2701 kfree(compr->raw_buf);
406abc95
CK		 2702 kfree(compr);
2703
2704 mutex_unlock(&dsp->pwr_lock);
2705
2706 return 0;
2707}
2708EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
2709
2710static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
2711 struct snd_compr_params *params)
2712{
2713 struct wm_adsp_compr *compr = stream->runtime->private_data;
2714 struct wm_adsp *dsp = compr->dsp;
2715 const struct wm_adsp_fw_caps *caps;
2716 const struct snd_codec_desc *desc;
2717 int i, j;
2718
2719 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
2720 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
2721 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
2722 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
2723 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
2724 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
2725 params->buffer.fragment_size,
2726 params->buffer.fragments);
2727
2728 return -EINVAL;
2729 }
2730
2731 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
2732 caps = &wm_adsp_fw[dsp->fw].caps[i];
2733 desc = &caps->desc;
2734
2735 if (caps->id != params->codec.id)
2736 continue;
2737
2738 if (stream->direction == SND_COMPRESS_PLAYBACK) {
2739 if (desc->max_ch < params->codec.ch_out)
2740 continue;
2741 } else {
2742 if (desc->max_ch < params->codec.ch_in)
2743 continue;
2744 }
2745
2746 if (!(desc->formats & (1 << params->codec.format)))
2747 continue;
2748
2749 for (j = 0; j < desc->num_sample_rates; ++j)
2750 if (desc->sample_rates[j] == params->codec.sample_rate)
2751 return 0;
2752 }
2753
2754 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
2755 params->codec.id, params->codec.ch_in, params->codec.ch_out,
2756 params->codec.sample_rate, params->codec.format);
2757 return -EINVAL;
2758}
2759
565ace46
CK		 2760static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
2761{
2762 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
2763}
2764
406abc95
CK		 2765int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
2766 struct snd_compr_params *params)
2767{
2768 struct wm_adsp_compr *compr = stream->runtime->private_data;
83a40ce9 2769 unsigned int size;
406abc95
CK		 2770 int ret;
2771
2772 ret = wm_adsp_compr_check_params(stream, params);
2773 if (ret)
2774 return ret;
2775
2776 compr->size = params->buffer;
2777
2778 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
2779 compr->size.fragment_size, compr->size.fragments);
2780
83a40ce9
CK		 2781 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
2782 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
2783 if (!compr->raw_buf)
2784 return -ENOMEM;
2785
da2b3358
CK		 2786 compr->sample_rate = params->codec.sample_rate;
2787
406abc95
CK		 2788 return 0;
2789}
2790EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
2791
2792int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
2793 struct snd_compr_caps *caps)
2794{
2795 struct wm_adsp_compr *compr = stream->runtime->private_data;
2796 int fw = compr->dsp->fw;
2797 int i;
2798
2799 if (wm_adsp_fw[fw].caps) {
2800 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
2801 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
2802
2803 caps->num_codecs = i;
2804 caps->direction = wm_adsp_fw[fw].compr_direction;
2805
2806 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
2807 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
2808 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
2809 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
2810 }
2811
2812 return 0;
2813}
2814EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
2815
2cd19bdb
CK		 2816static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
2817 unsigned int mem_addr,
2818 unsigned int num_words, u32 *data)
2819{
2820 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2821 unsigned int i, reg;
2822 int ret;
2823
2824 if (!mem)
2825 return -EINVAL;
2826
2827 reg = wm_adsp_region_to_reg(mem, mem_addr);
2828
2829 ret = regmap_raw_read(dsp->regmap, reg, data,
2830 sizeof(*data) * num_words);
2831 if (ret < 0)
2832 return ret;
2833
2834 for (i = 0; i < num_words; ++i)
2835 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
2836
2837 return 0;
2838}
2839
2840static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
2841 unsigned int mem_addr, u32 *data)
2842{
2843 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
2844}
2845
2846static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
2847 unsigned int mem_addr, u32 data)
2848{
2849 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2850 unsigned int reg;
2851
2852 if (!mem)
2853 return -EINVAL;
2854
2855 reg = wm_adsp_region_to_reg(mem, mem_addr);
2856
2857 data = cpu_to_be32(data & 0x00ffffffu);
2858
2859 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
2860}
2861
2862static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
2863 unsigned int field_offset, u32 *data)
2864{
2865 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
2866 buf->host_buf_ptr + field_offset, data);
2867}
2868
2869static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
2870 unsigned int field_offset, u32 data)
2871{
2872 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
2873 buf->host_buf_ptr + field_offset, data);
2874}
2875
2876static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
2877{
2878 struct wm_adsp_alg_region *alg_region;
2879 struct wm_adsp *dsp = buf->dsp;
2880 u32 xmalg, addr, magic;
2881 int i, ret;
2882
2883 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
2884 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
2885
2886 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
2887 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
2888 if (ret < 0)
2889 return ret;
2890
2891 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
2892 return -EINVAL;
2893
2894 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
2895 for (i = 0; i < 5; ++i) {
2896 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
2897 &buf->host_buf_ptr);
2898 if (ret < 0)
2899 return ret;
2900
2901 if (buf->host_buf_ptr)
2902 break;
2903
2904 usleep_range(1000, 2000);
2905 }
2906
2907 if (!buf->host_buf_ptr)
2908 return -EIO;
2909
2910 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
2911
2912 return 0;
2913}
2914
2915static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
2916{
2917 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
2918 struct wm_adsp_buffer_region *region;
2919 u32 offset = 0;
2920 int i, ret;
2921
2922 for (i = 0; i < caps->num_regions; ++i) {
2923 region = &buf->regions[i];
2924
2925 region->offset = offset;
2926 region->mem_type = caps->region_defs[i].mem_type;
2927
2928 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
2929 &region->base_addr);
2930 if (ret < 0)
2931 return ret;
2932
2933 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
2934 &offset);
2935 if (ret < 0)
2936 return ret;
2937
2938 region->cumulative_size = offset;
2939
2940 adsp_dbg(buf->dsp,
2941 "region=%d type=%d base=%04x off=%04x size=%04x\n",
2942 i, region->mem_type, region->base_addr,
2943 region->offset, region->cumulative_size);
2944 }
2945
2946 return 0;
2947}
2948
2949static int wm_adsp_buffer_init(struct wm_adsp *dsp)
2950{
2951 struct wm_adsp_compr_buf *buf;
2952 int ret;
2953
2954 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
2955 if (!buf)
2956 return -ENOMEM;
2957
2958 buf->dsp = dsp;
565ace46
CK		 2959 buf->read_index = -1;
2960 buf->irq_count = 0xFFFFFFFF;
2cd19bdb
CK		 2961
2962 ret = wm_adsp_buffer_locate(buf);
2963 if (ret < 0) {
2964 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
2965 goto err_buffer;
2966 }
2967
2968 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
2969 sizeof(*buf->regions), GFP_KERNEL);
2970 if (!buf->regions) {
2971 ret = -ENOMEM;
2972 goto err_buffer;
2973 }
2974
2975 ret = wm_adsp_buffer_populate(buf);
2976 if (ret < 0) {
2977 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
2978 goto err_regions;
2979 }
2980
2981 dsp->buffer = buf;
2982
2983 return 0;
2984
2985err_regions:
2986 kfree(buf->regions);
2987err_buffer:
2988 kfree(buf);
2989 return ret;
2990}
2991
2992static int wm_adsp_buffer_free(struct wm_adsp *dsp)
2993{
2994 if (dsp->buffer) {
721be3be
CK		 2995 wm_adsp_compr_detach(dsp->buffer->compr);
2996
2cd19bdb
CK		 2997 kfree(dsp->buffer->regions);
2998 kfree(dsp->buffer);
2999
3000 dsp->buffer = NULL;
3001 }
3002
3003 return 0;
3004}
3005
95fe9597
CK		 3006int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3007{
3008 struct wm_adsp_compr *compr = stream->runtime->private_data;
3009 struct wm_adsp *dsp = compr->dsp;
3010 int ret = 0;
3011
3012 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3013
3014 mutex_lock(&dsp->pwr_lock);
3015
3016 switch (cmd) {
3017 case SNDRV_PCM_TRIGGER_START:
3018 if (wm_adsp_compr_attached(compr))
3019 break;
3020
3021 ret = wm_adsp_compr_attach(compr);
3022 if (ret < 0) {
3023 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3024 ret);
3025 break;
3026 }
565ace46
CK		 3027
3028 /* Trigger the IRQ at one fragment of data */
3029 ret = wm_adsp_buffer_write(compr->buf,
3030 HOST_BUFFER_FIELD(high_water_mark),
3031 wm_adsp_compr_frag_words(compr));
3032 if (ret < 0) {
3033 adsp_err(dsp, "Failed to set high water mark: %d\n",
3034 ret);
3035 break;
3036 }
95fe9597
CK		 3037 break;
3038 case SNDRV_PCM_TRIGGER_STOP:
3039 break;
3040 default:
3041 ret = -EINVAL;
3042 break;
3043 }
3044
3045 mutex_unlock(&dsp->pwr_lock);
3046
3047 return ret;
3048}
3049EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3050
565ace46
CK		 3051static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3052{
3053 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3054
3055 return buf->regions[last_region].cumulative_size;
3056}
3057
3058static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3059{
3060 u32 next_read_index, next_write_index;
3061 int write_index, read_index, avail;
3062 int ret;
3063
3064 /* Only sync read index if we haven't already read a valid index */
3065 if (buf->read_index < 0) {
3066 ret = wm_adsp_buffer_read(buf,
3067 HOST_BUFFER_FIELD(next_read_index),
3068 &next_read_index);
3069 if (ret < 0)
3070 return ret;
3071
3072 read_index = sign_extend32(next_read_index, 23);
3073
3074 if (read_index < 0) {
3075 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3076 return 0;
3077 }
3078
3079 buf->read_index = read_index;
3080 }
3081
3082 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3083 &next_write_index);
3084 if (ret < 0)
3085 return ret;
3086
3087 write_index = sign_extend32(next_write_index, 23);
3088
3089 avail = write_index - buf->read_index;
3090 if (avail < 0)
3091 avail += wm_adsp_buffer_size(buf);
3092
3093 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
33d740e0 3094 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
565ace46
CK		 3095
3096 buf->avail = avail;
3097
3098 return 0;
3099}
3100
9771b18a
CK		 3101static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3102{
3103 int ret;
3104
3105 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3106 if (ret < 0) {
3107 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3108 return ret;
3109 }
3110 if (buf->error != 0) {
3111 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3112 return -EIO;
3113 }
3114
3115 return 0;
3116}
3117
565ace46
CK		 3118int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3119{
612047f0
CK		 3120 struct wm_adsp_compr_buf *buf;
3121 struct wm_adsp_compr *compr;
565ace46
CK		 3122 int ret = 0;
3123
3124 mutex_lock(&dsp->pwr_lock);
3125
612047f0
CK		 3126 buf = dsp->buffer;
3127 compr = dsp->compr;
3128
565ace46 3129 if (!buf) {
565ace46
CK		 3130 ret = -ENODEV;
3131 goto out;
3132 }
3133
3134 adsp_dbg(dsp, "Handling buffer IRQ\n");
3135
9771b18a
CK		 3136 ret = wm_adsp_buffer_get_error(buf);
3137 if (ret < 0)
5847609e 3138 goto out_notify; /* Wake poll to report error */
565ace46
CK		 3139
3140 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3141 &buf->irq_count);
3142 if (ret < 0) {
3143 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3144 goto out;
3145 }
3146
3147 ret = wm_adsp_buffer_update_avail(buf);
3148 if (ret < 0) {
3149 adsp_err(dsp, "Error reading avail: %d\n", ret);
3150 goto out;
3151 }
3152
20b7f7c5
CK		 3153 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3154 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3155
5847609e 3156out_notify:
c7dae7c4 3157 if (compr && compr->stream)
83a40ce9
CK		 3158 snd_compr_fragment_elapsed(compr->stream);
3159
565ace46
CK		 3160out:
3161 mutex_unlock(&dsp->pwr_lock);
3162
3163 return ret;
3164}
3165EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3166
3167static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3168{
3169 if (buf->irq_count & 0x01)
3170 return 0;
3171
3172 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3173 buf->irq_count);
3174
3175 buf->irq_count |= 0x01;
3176
3177 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3178 buf->irq_count);
3179}
3180
3181int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3182 struct snd_compr_tstamp *tstamp)
3183{
3184 struct wm_adsp_compr *compr = stream->runtime->private_data;
565ace46 3185 struct wm_adsp *dsp = compr->dsp;
612047f0 3186 struct wm_adsp_compr_buf *buf;
565ace46
CK		 3187 int ret = 0;
3188
3189 adsp_dbg(dsp, "Pointer request\n");
3190
3191 mutex_lock(&dsp->pwr_lock);
3192
612047f0
CK		 3193 buf = compr->buf;
3194
28ee3d73 3195 if (!compr->buf || compr->buf->error) {
8d280664 3196 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
565ace46
CK		 3197 ret = -EIO;
3198 goto out;
3199 }
3200
3201 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3202 ret = wm_adsp_buffer_update_avail(buf);
3203 if (ret < 0) {
3204 adsp_err(dsp, "Error reading avail: %d\n", ret);
3205 goto out;
3206 }
3207
3208 /*
3209 * If we really have less than 1 fragment available tell the
3210 * DSP to inform us once a whole fragment is available.
3211 */
3212 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
5847609e 3213 ret = wm_adsp_buffer_get_error(buf);
8d280664
CK		 3214 if (ret < 0) {
3215 if (compr->buf->error)
3216 snd_compr_stop_error(stream,
3217 SNDRV_PCM_STATE_XRUN);
5847609e 3218 goto out;
8d280664 3219 }
5847609e 3220
565ace46
CK		 3221 ret = wm_adsp_buffer_reenable_irq(buf);
3222 if (ret < 0) {
3223 adsp_err(dsp,
3224 "Failed to re-enable buffer IRQ: %d\n",
3225 ret);
3226 goto out;
3227 }
3228 }
3229 }
3230
3231 tstamp->copied_total = compr->copied_total;
3232 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
da2b3358 3233 tstamp->sampling_rate = compr->sample_rate;
565ace46
CK		 3234
3235out:
3236 mutex_unlock(&dsp->pwr_lock);
3237
3238 return ret;
3239}
3240EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3241
83a40ce9
CK		 3242static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3243{
3244 struct wm_adsp_compr_buf *buf = compr->buf;
3245 u8 *pack_in = (u8 *)compr->raw_buf;
3246 u8 *pack_out = (u8 *)compr->raw_buf;
3247 unsigned int adsp_addr;
3248 int mem_type, nwords, max_read;
3249 int i, j, ret;
3250
3251 /* Calculate read parameters */
3252 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3253 if (buf->read_index < buf->regions[i].cumulative_size)
3254 break;
3255
3256 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3257 return -EINVAL;
3258
3259 mem_type = buf->regions[i].mem_type;
3260 adsp_addr = buf->regions[i].base_addr +
3261 (buf->read_index - buf->regions[i].offset);
3262
3263 max_read = wm_adsp_compr_frag_words(compr);
3264 nwords = buf->regions[i].cumulative_size - buf->read_index;
3265
3266 if (nwords > target)
3267 nwords = target;
3268 if (nwords > buf->avail)
3269 nwords = buf->avail;
3270 if (nwords > max_read)
3271 nwords = max_read;
3272 if (!nwords)
3273 return 0;
3274
3275 /* Read data from DSP */
3276 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3277 nwords, compr->raw_buf);
3278 if (ret < 0)
3279 return ret;
3280
3281 /* Remove the padding bytes from the data read from the DSP */
3282 for (i = 0; i < nwords; i++) {
3283 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3284 *pack_out++ = *pack_in++;
3285
3286 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3287 }
3288
3289 /* update read index to account for words read */
3290 buf->read_index += nwords;
3291 if (buf->read_index == wm_adsp_buffer_size(buf))
3292 buf->read_index = 0;
3293
3294 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3295 buf->read_index);
3296 if (ret < 0)
3297 return ret;
3298
3299 /* update avail to account for words read */
3300 buf->avail -= nwords;
3301
3302 return nwords;
3303}
3304
3305static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3306 char __user *buf, size_t count)
3307{
3308 struct wm_adsp *dsp = compr->dsp;
3309 int ntotal = 0;
3310 int nwords, nbytes;
3311
3312 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3313
28ee3d73 3314 if (!compr->buf || compr->buf->error) {
8d280664 3315 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
83a40ce9 3316 return -EIO;
8d280664 3317 }
83a40ce9
CK		 3318
3319 count /= WM_ADSP_DATA_WORD_SIZE;
3320
3321 do {
3322 nwords = wm_adsp_buffer_capture_block(compr, count);
3323 if (nwords < 0) {
3324 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3325 return nwords;
3326 }
3327
3328 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3329
3330 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3331
3332 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3333 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3334 ntotal, nbytes);
3335 return -EFAULT;
3336 }
3337
3338 count -= nwords;
3339 ntotal += nbytes;
3340 } while (nwords > 0 && count > 0);
3341
3342 compr->copied_total += ntotal;
3343
3344 return ntotal;
3345}
3346
3347int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3348 size_t count)
3349{
3350 struct wm_adsp_compr *compr = stream->runtime->private_data;
3351 struct wm_adsp *dsp = compr->dsp;
3352 int ret;
3353
3354 mutex_lock(&dsp->pwr_lock);
3355
3356 if (stream->direction == SND_COMPRESS_CAPTURE)
3357 ret = wm_adsp_compr_read(compr, buf, count);
3358 else
3359 ret = -ENOTSUPP;
3360
3361 mutex_unlock(&dsp->pwr_lock);
3362
3363 return ret;
3364}
3365EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3366
0a37c6ef 3367MODULE_LICENSE("GPL v2");
Empty description
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