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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac
[linux.git] / sound / pci / ens1370.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
c1017a4c 3 * Copyright (c) by Jaroslav Kysela <[email protected]>,
1da177e4
LT		 4 * Thomas Sailer <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
f31a31b9
KB		 22/* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
631dd1a8 25 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
f31a31b9
KB		 26 * by Kurt J. Bosch
27 */
28
1da177e4
LT		 29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/gameport.h>
65a77217 36#include <linux/module.h>
62932df8
IM		 37#include <linux/mutex.h>
38
1da177e4
LT		 39#include <sound/core.h>
40#include <sound/control.h>
41#include <sound/pcm.h>
42#include <sound/rawmidi.h>
43#ifdef CHIP1371
44#include <sound/ac97_codec.h>
45#else
46#include <sound/ak4531_codec.h>
47#endif
48#include <sound/initval.h>
49#include <sound/asoundef.h>
50
51#ifndef CHIP1371
52#undef CHIP1370
53#define CHIP1370
54#endif
55
56#ifdef CHIP1370
57#define DRIVER_NAME "ENS1370"
58#else
59#define DRIVER_NAME "ENS1371"
60#endif
61
62
c1017a4c 63MODULE_AUTHOR("Jaroslav Kysela <[email protected]>, Thomas Sailer <[email protected]>");
1da177e4
LT		 64MODULE_LICENSE("GPL");
65#ifdef CHIP1370
66MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
67MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
68 "{Creative Labs,SB PCI64/128 (ES1370)}}");
69#endif
70#ifdef CHIP1371
71MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
72MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
73 "{Ensoniq,AudioPCI ES1373},"
74 "{Creative Labs,Ectiva EV1938},"
75 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
76 "{Creative Labs,Vibra PCI128},"
77 "{Ectiva,EV1938}}");
78#endif
79
80#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
81#define SUPPORT_JOYSTICK
82#endif
83
84static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
85static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 86static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
1da177e4
LT		 87#ifdef SUPPORT_JOYSTICK
88#ifdef CHIP1371
89static int joystick_port[SNDRV_CARDS];
90#else
a67ff6a5 91static bool joystick[SNDRV_CARDS];
1da177e4
LT		 92#endif
93#endif
156b2aa3
CL		 94#ifdef CHIP1371
95static int spdif[SNDRV_CARDS];
96static int lineio[SNDRV_CARDS];
97#endif
1da177e4
LT		 98
99module_param_array(index, int, NULL, 0444);
100MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
101module_param_array(id, charp, NULL, 0444);
102MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
103module_param_array(enable, bool, NULL, 0444);
104MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
105#ifdef SUPPORT_JOYSTICK
106#ifdef CHIP1371
107module_param_array(joystick_port, int, NULL, 0444);
108MODULE_PARM_DESC(joystick_port, "Joystick port address.");
109#else
110module_param_array(joystick, bool, NULL, 0444);
111MODULE_PARM_DESC(joystick, "Enable joystick.");
112#endif
113#endif /* SUPPORT_JOYSTICK */
156b2aa3
CL		 114#ifdef CHIP1371
115module_param_array(spdif, int, NULL, 0444);
116MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
117module_param_array(lineio, int, NULL, 0444);
118MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
119#endif
1da177e4 120
1da177e4
LT		 121/* ES1371 chip ID */
122/* This is a little confusing because all ES1371 compatible chips have the
123 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
124 This is only significant if you want to enable features on the later parts.
125 Yes, I know it's stupid and why didn't we use the sub IDs?
126*/
127#define ES1371REV_ES1373_A 0x04
128#define ES1371REV_ES1373_B 0x06
129#define ES1371REV_CT5880_A 0x07
130#define CT5880REV_CT5880_C 0x02
131#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
132#define CT5880REV_CT5880_E 0x04 /* mw */
133#define ES1371REV_ES1371_B 0x09
134#define EV1938REV_EV1938_A 0x00
135#define ES1371REV_ES1373_8 0x08
136
137/*
138 * Direct registers
139 */
140
141#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
142
143#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
144#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
145#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
146#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
147#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
148#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
149#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
150#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
151#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
152#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
153#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
154#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
155#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
156#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
157#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
158#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
159#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
160#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
161#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
162#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
163#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
164#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
165#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
166#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
167#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
168#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
169#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
170#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
171#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
172#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
173#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
174#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
175#define ES_BREQ (1<<7) /* memory bus request enable */
176#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
177#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
178#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
179#define ES_UART_EN (1<<3) /* UART enable */
180#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
181#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
182#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
183#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
184#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
185#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
186#define ES_INTR (1<<31) /* Interrupt is pending */
187#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
188#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
189#define ES_1373_REAR_BIT26 (1<<26)
190#define ES_1373_REAR_BIT24 (1<<24)
191#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
192#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
193#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
194#define ES_1371_TEST (1<<16) /* test ASIC */
195#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
196#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
197#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
198#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
199#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
200#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
201#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
202#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
203#define ES_MCCB (1<<4) /* CCB interrupt pending */
204#define ES_UART (1<<3) /* UART interrupt pending */
205#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
206#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
207#define ES_ADC (1<<0) /* ADC channel interrupt pending */
208#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
209#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
210#define ES_RXINT (1<<7) /* RX interrupt occurred */
211#define ES_TXINT (1<<2) /* TX interrupt occurred */
212#define ES_TXRDY (1<<1) /* transmitter ready */
213#define ES_RXRDY (1<<0) /* receiver ready */
214#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
215#define ES_RXINTEN (1<<7) /* RX interrupt enable */
216#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
217#define ES_TXINTENM (0x03<<5) /* mask for above */
218#define ES_TXINTENI(i) (((i)>>5)&0x03)
219#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
220#define ES_CNTRLM (0x03<<0) /* mask for above */
221#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
222#define ES_TEST_MODE (1<<0) /* test mode enabled */
223#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
224#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
225#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
226#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
227#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
228#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
229#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
230#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
231#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
6ebb8a4a 232#define EV_1938_CODEC_MAGIC (1<<26)
1da177e4
LT		 233#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
234#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
235#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
236#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
237
238#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
239#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
240#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
241#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
242#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
243#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
244#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
245#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
246#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
247#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
248#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
249#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
250#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
251
252#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
253#define ES_1371_JFAST (1<<31) /* fast joystick timing */
254#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
255#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
256#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
257#define ES_1371_VMPUM (0x03<<27) /* mask for above */
258#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
259#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
260#define ES_1371_VCDCM (0x03<<25) /* mask for above */
261#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
262#define ES_1371_FIRQ (1<<24) /* force an interrupt */
263#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
264#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
265#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
266#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
267#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
268#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
269#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
270#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
271#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
272#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
273#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
274#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
275
276#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
277
278#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
279#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
280#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
281#define ES_P2_END_INCM (0x07<<19) /* mask for above */
282#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
283#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
284#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
285#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
286#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
287#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
288#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
289#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
290#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
291#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
292#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
293#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
294#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
295#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
296#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
297#define ES_R1_MODEM (0x03<<4) /* mask for above */
298#define ES_R1_MODEI(i) (((i)>>4)&0x03)
299#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
300#define ES_P2_MODEM (0x03<<2) /* mask for above */
301#define ES_P2_MODEI(i) (((i)>>2)&0x03)
302#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
303#define ES_P1_MODEM (0x03<<0) /* mask for above */
304#define ES_P1_MODEI(i) (((i)>>0)&0x03)
305
306#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
307#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
308#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
309#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
310#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
311#define ES_REG_COUNTM (0xffff<<0)
312#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
313
314#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
315#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
316#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
317#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
318#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
319#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
320#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
321#define ES_REG_FCURR_COUNTM (0xffff<<16)
322#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
323#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
324#define ES_REG_FSIZEM (0xffff<<0)
325#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
326#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
327#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
328
329#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
330#define ES_REG_UF_VALID (1<<8)
331#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
332#define ES_REG_UF_BYTEM (0xff<<0)
333#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
334
335
336/*
337 * Pages
338 */
339
340#define ES_PAGE_DAC 0x0c
341#define ES_PAGE_ADC 0x0d
342#define ES_PAGE_UART 0x0e
343#define ES_PAGE_UART1 0x0f
344
345/*
346 * Sample rate converter addresses
347 */
348
349#define ES_SMPREG_DAC1 0x70
350#define ES_SMPREG_DAC2 0x74
351#define ES_SMPREG_ADC 0x78
352#define ES_SMPREG_VOL_ADC 0x6c
353#define ES_SMPREG_VOL_DAC1 0x7c
354#define ES_SMPREG_VOL_DAC2 0x7e
355#define ES_SMPREG_TRUNC_N 0x00
356#define ES_SMPREG_INT_REGS 0x01
357#define ES_SMPREG_ACCUM_FRAC 0x02
358#define ES_SMPREG_VFREQ_FRAC 0x03
359
360/*
361 * Some contants
362 */
363
364#define ES_1370_SRCLOCK 1411200
365#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
366
367/*
368 * Open modes
369 */
370
371#define ES_MODE_PLAY1 0x0001
372#define ES_MODE_PLAY2 0x0002
373#define ES_MODE_CAPTURE 0x0004
374
375#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
376#define ES_MODE_INPUT 0x0002 /* for MIDI */
377
378/*
379
380 */
381
eb3414b4 382struct ensoniq {
1da177e4 383 spinlock_t reg_lock;
62932df8 384 struct mutex src_mutex;
1da177e4
LT		 385
386 int irq;
387
388 unsigned long playback1size;
389 unsigned long playback2size;
390 unsigned long capture3size;
391
392 unsigned long port;
393 unsigned int mode;
394 unsigned int uartm; /* UART mode */
395
396 unsigned int ctrl; /* control register */
397 unsigned int sctrl; /* serial control register */
398 unsigned int cssr; /* control status register */
399 unsigned int uartc; /* uart control register */
400 unsigned int rev; /* chip revision */
401
402 union {
403#ifdef CHIP1371
404 struct {
eb3414b4 405 struct snd_ac97 *ac97;
1da177e4
LT		 406 } es1371;
407#else
408 struct {
409 int pclkdiv_lock;
eb3414b4 410 struct snd_ak4531 *ak4531;
1da177e4
LT		 411 } es1370;
412#endif
413 } u;
414
415 struct pci_dev *pci;
eb3414b4
TI		 416 struct snd_card *card;
417 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
418 struct snd_pcm *pcm2; /* DAC2 PCM */
419 struct snd_pcm_substream *playback1_substream;
420 struct snd_pcm_substream *playback2_substream;
421 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 422 unsigned int p1_dma_size;
423 unsigned int p2_dma_size;
424 unsigned int c_dma_size;
425 unsigned int p1_period_size;
426 unsigned int p2_period_size;
427 unsigned int c_period_size;
eb3414b4
TI		 428 struct snd_rawmidi *rmidi;
429 struct snd_rawmidi_substream *midi_input;
430 struct snd_rawmidi_substream *midi_output;
1da177e4
LT		 431
432 unsigned int spdif;
433 unsigned int spdif_default;
434 unsigned int spdif_stream;
435
436#ifdef CHIP1370
437 struct snd_dma_buffer dma_bug;
438#endif
439
440#ifdef SUPPORT_JOYSTICK
441 struct gameport *gameport;
442#endif
443};
444
7d12e780 445static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
1da177e4 446
cebe41d4 447static DEFINE_PCI_DEVICE_TABLE(snd_audiopci_ids) = {
1da177e4 448#ifdef CHIP1370
28d27aae 449 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
1da177e4
LT		 450#endif
451#ifdef CHIP1371
28d27aae
JP		 452 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
453 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
0d7392e5 454 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
1da177e4
LT		 455#endif
456 { 0, }
457};
458
459MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
460
461/*
462 * constants
463 */
464
465#define POLL_COUNT 0xa000
466
467#ifdef CHIP1370
468static unsigned int snd_es1370_fixed_rates[] =
469 {5512, 11025, 22050, 44100};
eb3414b4 470static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
1da177e4
LT		 471 .count = 4,
472 .list = snd_es1370_fixed_rates,
473 .mask = 0,
474};
eb3414b4 475static struct snd_ratnum es1370_clock = {
1da177e4
LT		 476 .num = ES_1370_SRCLOCK,
477 .den_min = 29,
478 .den_max = 353,
479 .den_step = 1,
480};
eb3414b4 481static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
1da177e4
LT		 482 .nrats = 1,
483 .rats = &es1370_clock,
484};
485#else
eb3414b4 486static struct snd_ratden es1371_dac_clock = {
1da177e4
LT		 487 .num_min = 3000 * (1 << 15),
488 .num_max = 48000 * (1 << 15),
489 .num_step = 3000,
490 .den = 1 << 15,
491};
eb3414b4 492static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
1da177e4
LT		 493 .nrats = 1,
494 .rats = &es1371_dac_clock,
495};
eb3414b4 496static struct snd_ratnum es1371_adc_clock = {
1da177e4
LT		 497 .num = 48000 << 15,
498 .den_min = 32768,
499 .den_max = 393216,
500 .den_step = 1,
501};
eb3414b4 502static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
1da177e4
LT		 503 .nrats = 1,
504 .rats = &es1371_adc_clock,
505};
506#endif
507static const unsigned int snd_ensoniq_sample_shift[] =
508 {0, 1, 1, 2};
509
510/*
511 * common I/O routines
512 */
513
514#ifdef CHIP1371
515
eb3414b4 516static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
1da177e4
LT		 517{
518 unsigned int t, r = 0;
519
520 for (t = 0; t < POLL_COUNT; t++) {
521 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
522 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
523 return r;
524 cond_resched();
525 }
810fd3f3 526 snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n",
eb3414b4 527 ES_REG(ensoniq, 1371_SMPRATE), r);
1da177e4
LT		 528 return 0;
529}
530
eb3414b4 531static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
1da177e4
LT		 532{
533 unsigned int temp, i, orig, r;
534
535 /* wait for ready */
536 temp = orig = snd_es1371_wait_src_ready(ensoniq);
537
538 /* expose the SRC state bits */
539 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
540 ES_1371_DIS_P2 | ES_1371_DIS_R1);
541 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
542 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
543
544 /* now, wait for busy and the correct time to read */
545 temp = snd_es1371_wait_src_ready(ensoniq);
546
547 if ((temp & 0x00870000) != 0x00010000) {
548 /* wait for the right state */
549 for (i = 0; i < POLL_COUNT; i++) {
550 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
551 if ((temp & 0x00870000) == 0x00010000)
552 break;
553 }
554 }
555
556 /* hide the state bits */
557 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
558 ES_1371_DIS_P2 | ES_1371_DIS_R1);
559 r |= ES_1371_SRC_RAM_ADDRO(reg);
560 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
561
562 return temp;
563}
564
eb3414b4 565static void snd_es1371_src_write(struct ensoniq * ensoniq,
1da177e4
LT		 566 unsigned short reg, unsigned short data)
567{
568 unsigned int r;
569
570 r = snd_es1371_wait_src_ready(ensoniq) &
571 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
572 ES_1371_DIS_P2 | ES_1371_DIS_R1);
573 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
574 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
575}
576
577#endif /* CHIP1371 */
578
579#ifdef CHIP1370
580
eb3414b4 581static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
1da177e4
LT		 582 unsigned short reg, unsigned short val)
583{
eb3414b4 584 struct ensoniq *ensoniq = ak4531->private_data;
1da177e4
LT		 585 unsigned long end_time = jiffies + HZ / 10;
586
587#if 0
ee419653
TI		 588 printk(KERN_DEBUG
589 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
eb3414b4 590 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
1da177e4
LT		 591#endif
592 do {
593 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
594 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
595 return;
596 }
8433a509 597 schedule_timeout_uninterruptible(1);
1da177e4 598 } while (time_after(end_time, jiffies));
eb3414b4
TI		 599 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
600 inl(ES_REG(ensoniq, STATUS)));
1da177e4
LT		 601}
602
603#endif /* CHIP1370 */
604
605#ifdef CHIP1371
606
6ebb8a4a
CL		 607static inline bool is_ev1938(struct ensoniq *ensoniq)
608{
609 return ensoniq->pci->device == 0x8938;
610}
611
eb3414b4 612static void snd_es1371_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 613 unsigned short reg, unsigned short val)
614{
eb3414b4 615 struct ensoniq *ensoniq = ac97->private_data;
6ebb8a4a 616 unsigned int t, x, flag;
1da177e4 617
6ebb8a4a 618 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
62932df8 619 mutex_lock(&ensoniq->src_mutex);
1da177e4
LT		 620 for (t = 0; t < POLL_COUNT; t++) {
621 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
622 /* save the current state for latter */
623 x = snd_es1371_wait_src_ready(ensoniq);
624 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
625 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
626 ES_REG(ensoniq, 1371_SMPRATE));
627 /* wait for not busy (state 0) first to avoid
628 transition states */
629 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 630 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
631 0x00000000)
1da177e4
LT		 632 break;
633 }
634 /* wait for a SAFE time to write addr/data and then do it, dammit */
635 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 636 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
637 0x00010000)
1da177e4
LT		 638 break;
639 }
6ebb8a4a
CL		 640 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
641 ES_REG(ensoniq, 1371_CODEC));
1da177e4
LT		 642 /* restore SRC reg */
643 snd_es1371_wait_src_ready(ensoniq);
644 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
62932df8 645 mutex_unlock(&ensoniq->src_mutex);
1da177e4
LT		 646 return;
647 }
648 }
62932df8 649 mutex_unlock(&ensoniq->src_mutex);
eb3414b4
TI		 650 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
651 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 652}
653
eb3414b4 654static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 655 unsigned short reg)
656{
eb3414b4 657 struct ensoniq *ensoniq = ac97->private_data;
6ebb8a4a 658 unsigned int t, x, flag, fail = 0;
1da177e4 659
6ebb8a4a 660 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
1da177e4 661 __again:
62932df8 662 mutex_lock(&ensoniq->src_mutex);
1da177e4
LT		 663 for (t = 0; t < POLL_COUNT; t++) {
664 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
665 /* save the current state for latter */
666 x = snd_es1371_wait_src_ready(ensoniq);
667 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
668 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
669 ES_REG(ensoniq, 1371_SMPRATE));
670 /* wait for not busy (state 0) first to avoid
671 transition states */
672 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 673 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
674 0x00000000)
1da177e4
LT		 675 break;
676 }
677 /* wait for a SAFE time to write addr/data and then do it, dammit */
678 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 679 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
680 0x00010000)
1da177e4
LT		 681 break;
682 }
6ebb8a4a
CL		 683 outl(ES_1371_CODEC_READS(reg) | flag,
684 ES_REG(ensoniq, 1371_CODEC));
1da177e4
LT		 685 /* restore SRC reg */
686 snd_es1371_wait_src_ready(ensoniq);
687 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
688 /* wait for WIP again */
689 for (t = 0; t < POLL_COUNT; t++) {
690 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
691 break;
692 }
693 /* now wait for the stinkin' data (RDY) */
694 for (t = 0; t < POLL_COUNT; t++) {
695 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
6ebb8a4a
CL		 696 if (is_ev1938(ensoniq)) {
697 for (t = 0; t < 100; t++)
698 inl(ES_REG(ensoniq, CONTROL));
699 x = inl(ES_REG(ensoniq, 1371_CODEC));
700 }
62932df8 701 mutex_unlock(&ensoniq->src_mutex);
1da177e4
LT		 702 return ES_1371_CODEC_READ(x);
703 }
704 }
62932df8 705 mutex_unlock(&ensoniq->src_mutex);
1da177e4 706 if (++fail > 10) {
eb3414b4
TI		 707 snd_printk(KERN_ERR "codec read timeout (final) "
708 "at 0x%lx, reg = 0x%x [0x%x]\n",
709 ES_REG(ensoniq, 1371_CODEC), reg,
710 inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 711 return 0;
712 }
713 goto __again;
714 }
715 }
62932df8 716 mutex_unlock(&ensoniq->src_mutex);
eb3414b4
TI		 717 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
718 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 719 return 0;
720}
721
eb3414b4 722static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
072c0119
JK		 723{
724 msleep(750);
725 snd_es1371_codec_read(ac97, AC97_RESET);
726 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
727 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
728 msleep(50);
729}
730
eb3414b4 731static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
1da177e4
LT		 732{
733 unsigned int n, truncm, freq, result;
734
62932df8 735 mutex_lock(&ensoniq->src_mutex);
1da177e4
LT		 736 n = rate / 3000;
737 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
738 n--;
739 truncm = (21 * n - 1) | 1;
740 freq = ((48000UL << 15) / rate) * n;
741 result = (48000UL << 15) / (freq / n);
742 if (rate >= 24000) {
743 if (truncm > 239)
744 truncm = 239;
745 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
746 (((239 - truncm) >> 1) << 9) | (n << 4));
747 } else {
748 if (truncm > 119)
749 truncm = 119;
750 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
751 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
752 }
753 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
eb3414b4
TI		 754 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
755 ES_SMPREG_INT_REGS) & 0x00ff) |
756 ((freq >> 5) & 0xfc00));
1da177e4
LT		 757 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
758 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
759 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
62932df8 760 mutex_unlock(&ensoniq->src_mutex);
1da177e4
LT		 761}
762
eb3414b4 763static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
1da177e4
LT		 764{
765 unsigned int freq, r;
766
62932df8 767 mutex_lock(&ensoniq->src_mutex);
1da177e4 768 freq = ((rate << 15) + 1500) / 3000;
eb3414b4
TI		 769 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
770 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
771 ES_1371_DIS_P1;
1da177e4
LT		 772 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
773 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
eb3414b4
TI		 774 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
775 ES_SMPREG_INT_REGS) & 0x00ff) |
1da177e4
LT		 776 ((freq >> 5) & 0xfc00));
777 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
eb3414b4
TI		 778 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
779 ES_1371_DIS_P2 | ES_1371_DIS_R1));
1da177e4 780 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
62932df8 781 mutex_unlock(&ensoniq->src_mutex);
1da177e4
LT		 782}
783
eb3414b4 784static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
1da177e4
LT		 785{
786 unsigned int freq, r;
787
62932df8 788 mutex_lock(&ensoniq->src_mutex);
1da177e4 789 freq = ((rate << 15) + 1500) / 3000;
eb3414b4
TI		 790 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
791 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
792 ES_1371_DIS_P2;
1da177e4
LT		 793 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
794 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
eb3414b4
TI		 795 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
796 ES_SMPREG_INT_REGS) & 0x00ff) |
1da177e4 797 ((freq >> 5) & 0xfc00));
eb3414b4
TI		 798 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
799 freq & 0x7fff);
800 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
801 ES_1371_DIS_P1 | ES_1371_DIS_R1));
1da177e4 802 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
62932df8 803 mutex_unlock(&ensoniq->src_mutex);
1da177e4
LT		 804}
805
806#endif /* CHIP1371 */
807
eb3414b4 808static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 809{
eb3414b4 810 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 811 switch (cmd) {
812 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
814 {
815 unsigned int what = 0;
eb3414b4 816 struct snd_pcm_substream *s;
ef991b95 817 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 818 if (s == ensoniq->playback1_substream) {
819 what |= ES_P1_PAUSE;
820 snd_pcm_trigger_done(s, substream);
821 } else if (s == ensoniq->playback2_substream) {
822 what |= ES_P2_PAUSE;
823 snd_pcm_trigger_done(s, substream);
824 } else if (s == ensoniq->capture_substream)
825 return -EINVAL;
826 }
827 spin_lock(&ensoniq->reg_lock);
828 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
829 ensoniq->sctrl |= what;
830 else
831 ensoniq->sctrl &= ~what;
832 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
833 spin_unlock(&ensoniq->reg_lock);
834 break;
835 }
836 case SNDRV_PCM_TRIGGER_START:
837 case SNDRV_PCM_TRIGGER_STOP:
838 {
839 unsigned int what = 0;
eb3414b4 840 struct snd_pcm_substream *s;
ef991b95 841 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 842 if (s == ensoniq->playback1_substream) {
843 what |= ES_DAC1_EN;
844 snd_pcm_trigger_done(s, substream);
845 } else if (s == ensoniq->playback2_substream) {
846 what |= ES_DAC2_EN;
847 snd_pcm_trigger_done(s, substream);
848 } else if (s == ensoniq->capture_substream) {
849 what |= ES_ADC_EN;
850 snd_pcm_trigger_done(s, substream);
851 }
852 }
853 spin_lock(&ensoniq->reg_lock);
854 if (cmd == SNDRV_PCM_TRIGGER_START)
855 ensoniq->ctrl |= what;
856 else
857 ensoniq->ctrl &= ~what;
858 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
859 spin_unlock(&ensoniq->reg_lock);
860 break;
861 }
862 default:
863 return -EINVAL;
864 }
865 return 0;
866}
867
868/*
869 * PCM part
870 */
871
eb3414b4
TI		 872static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
873 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 874{
875 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
876}
877
eb3414b4 878static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 879{
880 return snd_pcm_lib_free_pages(substream);
881}
882
eb3414b4 883static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
1da177e4 884{
eb3414b4
TI		 885 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
886 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 887 unsigned int mode = 0;
888
889 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
890 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
891 if (snd_pcm_format_width(runtime->format) == 16)
892 mode |= 0x02;
893 if (runtime->channels > 1)
894 mode |= 0x01;
895 spin_lock_irq(&ensoniq->reg_lock);
896 ensoniq->ctrl &= ~ES_DAC1_EN;
897#ifdef CHIP1371
898 /* 48k doesn't need SRC (it breaks AC3-passthru) */
899 if (runtime->rate == 48000)
900 ensoniq->ctrl |= ES_1373_BYPASS_P1;
901 else
902 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
903#endif
904 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
905 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
906 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
907 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
908 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
909 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
910 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
eb3414b4
TI		 911 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
912 ES_REG(ensoniq, DAC1_COUNT));
1da177e4
LT		 913#ifdef CHIP1370
914 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
915 switch (runtime->rate) {
916 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
917 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
918 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
919 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
920 default: snd_BUG();
921 }
922#endif
923 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
924 spin_unlock_irq(&ensoniq->reg_lock);
925#ifndef CHIP1370
926 snd_es1371_dac1_rate(ensoniq, runtime->rate);
927#endif
928 return 0;
929}
930
eb3414b4 931static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
1da177e4 932{
eb3414b4
TI		 933 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
934 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 935 unsigned int mode = 0;
936
937 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
938 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
939 if (snd_pcm_format_width(runtime->format) == 16)
940 mode |= 0x02;
941 if (runtime->channels > 1)
942 mode |= 0x01;
943 spin_lock_irq(&ensoniq->reg_lock);
944 ensoniq->ctrl &= ~ES_DAC2_EN;
945 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
946 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
947 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
948 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
949 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
950 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
951 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
952 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
953 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
eb3414b4
TI		 954 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
955 ES_REG(ensoniq, DAC2_COUNT));
1da177e4
LT		 956#ifdef CHIP1370
957 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
958 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
959 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
960 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
961 }
962#endif
963 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
964 spin_unlock_irq(&ensoniq->reg_lock);
965#ifndef CHIP1370
966 snd_es1371_dac2_rate(ensoniq, runtime->rate);
967#endif
968 return 0;
969}
970
eb3414b4 971static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 972{
eb3414b4
TI		 973 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
974 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 975 unsigned int mode = 0;
976
977 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
978 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
979 if (snd_pcm_format_width(runtime->format) == 16)
980 mode |= 0x02;
981 if (runtime->channels > 1)
982 mode |= 0x01;
983 spin_lock_irq(&ensoniq->reg_lock);
984 ensoniq->ctrl &= ~ES_ADC_EN;
985 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
986 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
987 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
988 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
989 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
990 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
991 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
eb3414b4
TI		 992 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
993 ES_REG(ensoniq, ADC_COUNT));
1da177e4
LT		 994#ifdef CHIP1370
995 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
996 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
997 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
998 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
999 }
1000#endif
1001 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1002 spin_unlock_irq(&ensoniq->reg_lock);
1003#ifndef CHIP1370
1004 snd_es1371_adc_rate(ensoniq, runtime->rate);
1005#endif
1006 return 0;
1007}
1008
eb3414b4 1009static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1da177e4 1010{
eb3414b4 1011 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1012 size_t ptr;
1013
1014 spin_lock(&ensoniq->reg_lock);
1015 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1016 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1017 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1018 ptr = bytes_to_frames(substream->runtime, ptr);
1019 } else {
1020 ptr = 0;
1021 }
1022 spin_unlock(&ensoniq->reg_lock);
1023 return ptr;
1024}
1025
eb3414b4 1026static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1da177e4 1027{
eb3414b4 1028 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1029 size_t ptr;
1030
1031 spin_lock(&ensoniq->reg_lock);
1032 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1033 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1034 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1035 ptr = bytes_to_frames(substream->runtime, ptr);
1036 } else {
1037 ptr = 0;
1038 }
1039 spin_unlock(&ensoniq->reg_lock);
1040 return ptr;
1041}
1042
eb3414b4 1043static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1044{
eb3414b4 1045 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1046 size_t ptr;
1047
1048 spin_lock(&ensoniq->reg_lock);
1049 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1050 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1051 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1052 ptr = bytes_to_frames(substream->runtime, ptr);
1053 } else {
1054 ptr = 0;
1055 }
1056 spin_unlock(&ensoniq->reg_lock);
1057 return ptr;
1058}
1059
eb3414b4 1060static struct snd_pcm_hardware snd_ensoniq_playback1 =
1da177e4
LT		 1061{
1062 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1063 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1064 SNDRV_PCM_INFO_MMAP_VALID |
1065 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1066 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1067 .rates =
1068#ifndef CHIP1370
1069 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1070#else
1071 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1072 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1073 SNDRV_PCM_RATE_44100),
1074#endif
1075 .rate_min = 4000,
1076 .rate_max = 48000,
1077 .channels_min = 1,
1078 .channels_max = 2,
1079 .buffer_bytes_max = (128*1024),
1080 .period_bytes_min = 64,
1081 .period_bytes_max = (128*1024),
1082 .periods_min = 1,
1083 .periods_max = 1024,
1084 .fifo_size = 0,
1085};
1086
eb3414b4 1087static struct snd_pcm_hardware snd_ensoniq_playback2 =
1da177e4
LT		 1088{
1089 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1090 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1091 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1092 SNDRV_PCM_INFO_SYNC_START),
1093 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1094 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1095 .rate_min = 4000,
1096 .rate_max = 48000,
1097 .channels_min = 1,
1098 .channels_max = 2,
1099 .buffer_bytes_max = (128*1024),
1100 .period_bytes_min = 64,
1101 .period_bytes_max = (128*1024),
1102 .periods_min = 1,
1103 .periods_max = 1024,
1104 .fifo_size = 0,
1105};
1106
eb3414b4 1107static struct snd_pcm_hardware snd_ensoniq_capture =
1da177e4
LT		 1108{
1109 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1110 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1111 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1112 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1113 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1114 .rate_min = 4000,
1115 .rate_max = 48000,
1116 .channels_min = 1,
1117 .channels_max = 2,
1118 .buffer_bytes_max = (128*1024),
1119 .period_bytes_min = 64,
1120 .period_bytes_max = (128*1024),
1121 .periods_min = 1,
1122 .periods_max = 1024,
1123 .fifo_size = 0,
1124};
1125
eb3414b4 1126static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1da177e4 1127{
eb3414b4
TI		 1128 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1129 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1130
1131 ensoniq->mode |= ES_MODE_PLAY1;
1132 ensoniq->playback1_substream = substream;
1133 runtime->hw = snd_ensoniq_playback1;
1134 snd_pcm_set_sync(substream);
1135 spin_lock_irq(&ensoniq->reg_lock);
1136 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1137 ensoniq->spdif_stream = ensoniq->spdif_default;
1138 spin_unlock_irq(&ensoniq->reg_lock);
1139#ifdef CHIP1370
1140 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1141 &snd_es1370_hw_constraints_rates);
1142#else
1143 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1144 &snd_es1371_hw_constraints_dac_clock);
1145#endif
1146 return 0;
1147}
1148
eb3414b4 1149static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1da177e4 1150{
eb3414b4
TI		 1151 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1152 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1153
1154 ensoniq->mode |= ES_MODE_PLAY2;
1155 ensoniq->playback2_substream = substream;
1156 runtime->hw = snd_ensoniq_playback2;
1157 snd_pcm_set_sync(substream);
1158 spin_lock_irq(&ensoniq->reg_lock);
1159 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1160 ensoniq->spdif_stream = ensoniq->spdif_default;
1161 spin_unlock_irq(&ensoniq->reg_lock);
1162#ifdef CHIP1370
1163 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1164 &snd_es1370_hw_constraints_clock);
1165#else
1166 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1167 &snd_es1371_hw_constraints_dac_clock);
1168#endif
1169 return 0;
1170}
1171
eb3414b4 1172static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1da177e4 1173{
eb3414b4
TI		 1174 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1175 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1176
1177 ensoniq->mode |= ES_MODE_CAPTURE;
1178 ensoniq->capture_substream = substream;
1179 runtime->hw = snd_ensoniq_capture;
1180 snd_pcm_set_sync(substream);
1181#ifdef CHIP1370
1182 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1183 &snd_es1370_hw_constraints_clock);
1184#else
1185 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1186 &snd_es1371_hw_constraints_adc_clock);
1187#endif
1188 return 0;
1189}
1190
eb3414b4 1191static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1da177e4 1192{
eb3414b4 1193 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1194
1195 ensoniq->playback1_substream = NULL;
1196 ensoniq->mode &= ~ES_MODE_PLAY1;
1197 return 0;
1198}
1199
eb3414b4 1200static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1da177e4 1201{
eb3414b4 1202 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1203
1204 ensoniq->playback2_substream = NULL;
1205 spin_lock_irq(&ensoniq->reg_lock);
1206#ifdef CHIP1370
1207 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1208#endif
1209 ensoniq->mode &= ~ES_MODE_PLAY2;
1210 spin_unlock_irq(&ensoniq->reg_lock);
1211 return 0;
1212}
1213
eb3414b4 1214static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1da177e4 1215{
eb3414b4 1216 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1217
1218 ensoniq->capture_substream = NULL;
1219 spin_lock_irq(&ensoniq->reg_lock);
1220#ifdef CHIP1370
1221 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1222#endif
1223 ensoniq->mode &= ~ES_MODE_CAPTURE;
1224 spin_unlock_irq(&ensoniq->reg_lock);
1225 return 0;
1226}
1227
eb3414b4 1228static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1da177e4
LT		 1229 .open = snd_ensoniq_playback1_open,
1230 .close = snd_ensoniq_playback1_close,
1231 .ioctl = snd_pcm_lib_ioctl,
1232 .hw_params = snd_ensoniq_hw_params,
1233 .hw_free = snd_ensoniq_hw_free,
1234 .prepare = snd_ensoniq_playback1_prepare,
1235 .trigger = snd_ensoniq_trigger,
1236 .pointer = snd_ensoniq_playback1_pointer,
1237};
1238
eb3414b4 1239static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1da177e4
LT		 1240 .open = snd_ensoniq_playback2_open,
1241 .close = snd_ensoniq_playback2_close,
1242 .ioctl = snd_pcm_lib_ioctl,
1243 .hw_params = snd_ensoniq_hw_params,
1244 .hw_free = snd_ensoniq_hw_free,
1245 .prepare = snd_ensoniq_playback2_prepare,
1246 .trigger = snd_ensoniq_trigger,
1247 .pointer = snd_ensoniq_playback2_pointer,
1248};
1249
eb3414b4 1250static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1da177e4
LT		 1251 .open = snd_ensoniq_capture_open,
1252 .close = snd_ensoniq_capture_close,
1253 .ioctl = snd_pcm_lib_ioctl,
1254 .hw_params = snd_ensoniq_hw_params,
1255 .hw_free = snd_ensoniq_hw_free,
1256 .prepare = snd_ensoniq_capture_prepare,
1257 .trigger = snd_ensoniq_trigger,
1258 .pointer = snd_ensoniq_capture_pointer,
1259};
1260
eb3414b4
TI		 1261static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1262 struct snd_pcm ** rpcm)
1da177e4 1263{
eb3414b4 1264 struct snd_pcm *pcm;
1da177e4
LT		 1265 int err;
1266
1267 if (rpcm)
1268 *rpcm = NULL;
1269#ifdef CHIP1370
1270 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1271#else
1272 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1273#endif
1274 if (err < 0)
1275 return err;
1276
1277#ifdef CHIP1370
1278 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1279#else
1280 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1281#endif
1282 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1283
1284 pcm->private_data = ensoniq;
1da177e4
LT		 1285 pcm->info_flags = 0;
1286#ifdef CHIP1370
1287 strcpy(pcm->name, "ES1370 DAC2/ADC");
1288#else
1289 strcpy(pcm->name, "ES1371 DAC2/ADC");
1290#endif
1291 ensoniq->pcm1 = pcm;
1292
1293 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1294 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1295
1296 if (rpcm)
1297 *rpcm = pcm;
1298 return 0;
1299}
1300
eb3414b4
TI		 1301static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1302 struct snd_pcm ** rpcm)
1da177e4 1303{
eb3414b4 1304 struct snd_pcm *pcm;
1da177e4
LT		 1305 int err;
1306
1307 if (rpcm)
1308 *rpcm = NULL;
1309#ifdef CHIP1370
1310 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1311#else
1312 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1313#endif
1314 if (err < 0)
1315 return err;
1316
1317#ifdef CHIP1370
1318 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1319#else
1320 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1321#endif
1322 pcm->private_data = ensoniq;
1da177e4
LT		 1323 pcm->info_flags = 0;
1324#ifdef CHIP1370
1325 strcpy(pcm->name, "ES1370 DAC1");
1326#else
1327 strcpy(pcm->name, "ES1371 DAC1");
1328#endif
1329 ensoniq->pcm2 = pcm;
1330
1331 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1332 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1333
1334 if (rpcm)
1335 *rpcm = pcm;
1336 return 0;
1337}
1338
1339/*
1340 * Mixer section
1341 */
1342
1343/*
1344 * ENS1371 mixer (including SPDIF interface)
1345 */
1346#ifdef CHIP1371
eb3414b4
TI		 1347static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1348 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1349{
1350 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1351 uinfo->count = 1;
1352 return 0;
1353}
1354
eb3414b4
TI		 1355static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1356 struct snd_ctl_elem_value *ucontrol)
1da177e4 1357{
eb3414b4 1358 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1359 spin_lock_irq(&ensoniq->reg_lock);
1360 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1361 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1362 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1363 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1364 spin_unlock_irq(&ensoniq->reg_lock);
1365 return 0;
1366}
1367
eb3414b4
TI		 1368static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1369 struct snd_ctl_elem_value *ucontrol)
1da177e4 1370{
eb3414b4 1371 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1372 unsigned int val;
1373 int change;
1374
1375 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1376 ((u32)ucontrol->value.iec958.status[1] << 8) |
1377 ((u32)ucontrol->value.iec958.status[2] << 16) |
1378 ((u32)ucontrol->value.iec958.status[3] << 24);
1379 spin_lock_irq(&ensoniq->reg_lock);
1380 change = ensoniq->spdif_default != val;
1381 ensoniq->spdif_default = val;
eb3414b4
TI		 1382 if (change && ensoniq->playback1_substream == NULL &&
1383 ensoniq->playback2_substream == NULL)
1da177e4
LT		 1384 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1385 spin_unlock_irq(&ensoniq->reg_lock);
1386 return change;
1387}
1388
eb3414b4
TI		 1389static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1390 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1391{
1392 ucontrol->value.iec958.status[0] = 0xff;
1393 ucontrol->value.iec958.status[1] = 0xff;
1394 ucontrol->value.iec958.status[2] = 0xff;
1395 ucontrol->value.iec958.status[3] = 0xff;
1396 return 0;
1397}
1398
eb3414b4
TI		 1399static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1400 struct snd_ctl_elem_value *ucontrol)
1da177e4 1401{
eb3414b4 1402 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1403 spin_lock_irq(&ensoniq->reg_lock);
1404 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1405 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1406 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1407 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1408 spin_unlock_irq(&ensoniq->reg_lock);
1409 return 0;
1410}
1411
eb3414b4
TI		 1412static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1413 struct snd_ctl_elem_value *ucontrol)
1da177e4 1414{
eb3414b4 1415 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1416 unsigned int val;
1417 int change;
1418
1419 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1420 ((u32)ucontrol->value.iec958.status[1] << 8) |
1421 ((u32)ucontrol->value.iec958.status[2] << 16) |
1422 ((u32)ucontrol->value.iec958.status[3] << 24);
1423 spin_lock_irq(&ensoniq->reg_lock);
1424 change = ensoniq->spdif_stream != val;
1425 ensoniq->spdif_stream = val;
eb3414b4
TI		 1426 if (change && (ensoniq->playback1_substream != NULL ||
1427 ensoniq->playback2_substream != NULL))
1da177e4
LT		 1428 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1429 spin_unlock_irq(&ensoniq->reg_lock);
1430 return change;
1431}
1432
1433#define ES1371_SPDIF(xname) \
1434{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1435 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1436
a5ce8890 1437#define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1da177e4 1438
eb3414b4
TI		 1439static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1440 struct snd_ctl_elem_value *ucontrol)
1da177e4 1441{
eb3414b4 1442 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1443
1444 spin_lock_irq(&ensoniq->reg_lock);
1445 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1446 spin_unlock_irq(&ensoniq->reg_lock);
1447 return 0;
1448}
1449
eb3414b4
TI		 1450static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1451 struct snd_ctl_elem_value *ucontrol)
1da177e4 1452{
eb3414b4 1453 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1454 unsigned int nval1, nval2;
1455 int change;
1456
1457 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1458 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1459 spin_lock_irq(&ensoniq->reg_lock);
1460 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1461 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1462 ensoniq->ctrl |= nval1;
1463 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1464 ensoniq->cssr |= nval2;
1465 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1466 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1467 spin_unlock_irq(&ensoniq->reg_lock);
1468 return change;
1469}
1470
1471
1472/* spdif controls */
eb3414b4 1473static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
10e8d78a 1474 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1da177e4 1475 {
5549d549 1476 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1477 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1478 .info = snd_ens1373_spdif_info,
1479 .get = snd_ens1373_spdif_default_get,
1480 .put = snd_ens1373_spdif_default_put,
1481 },
1482 {
1483 .access = SNDRV_CTL_ELEM_ACCESS_READ,
5549d549 1484 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1485 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1486 .info = snd_ens1373_spdif_info,
1487 .get = snd_ens1373_spdif_mask_get
1488 },
1489 {
5549d549 1490 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1491 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1492 .info = snd_ens1373_spdif_info,
1493 .get = snd_ens1373_spdif_stream_get,
1494 .put = snd_ens1373_spdif_stream_put
1495 },
1496};
1497
1498
a5ce8890 1499#define snd_es1373_rear_info snd_ctl_boolean_mono_info
1da177e4 1500
eb3414b4
TI		 1501static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1502 struct snd_ctl_elem_value *ucontrol)
1da177e4 1503{
eb3414b4 1504 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1505 int val = 0;
1506
1507 spin_lock_irq(&ensoniq->reg_lock);
eb3414b4
TI		 1508 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1509 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1da177e4
LT		 1510 val = 1;
1511 ucontrol->value.integer.value[0] = val;
1512 spin_unlock_irq(&ensoniq->reg_lock);
1513 return 0;
1514}
1515
eb3414b4
TI		 1516static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1517 struct snd_ctl_elem_value *ucontrol)
1da177e4 1518{
eb3414b4 1519 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1520 unsigned int nval1;
1521 int change;
1522
eb3414b4
TI		 1523 nval1 = ucontrol->value.integer.value[0] ?
1524 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1da177e4 1525 spin_lock_irq(&ensoniq->reg_lock);
eb3414b4
TI		 1526 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1527 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1da177e4
LT		 1528 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1529 ensoniq->cssr |= nval1;
1530 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1531 spin_unlock_irq(&ensoniq->reg_lock);
1532 return change;
1533}
1534
eb3414b4 1535static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1da177e4
LT		 1536{
1537 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1538 .name = "AC97 2ch->4ch Copy Switch",
1539 .info = snd_es1373_rear_info,
1540 .get = snd_es1373_rear_get,
1541 .put = snd_es1373_rear_put,
1542};
1543
a5ce8890 1544#define snd_es1373_line_info snd_ctl_boolean_mono_info
1da177e4 1545
eb3414b4
TI		 1546static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1547 struct snd_ctl_elem_value *ucontrol)
1da177e4 1548{
eb3414b4 1549 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1550 int val = 0;
1551
1552 spin_lock_irq(&ensoniq->reg_lock);
1553 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1554 val = 1;
1555 ucontrol->value.integer.value[0] = val;
1556 spin_unlock_irq(&ensoniq->reg_lock);
1557 return 0;
1558}
1559
eb3414b4
TI		 1560static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol)
1da177e4 1562{
eb3414b4 1563 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1564 int changed;
1565 unsigned int ctrl;
1566
1567 spin_lock_irq(&ensoniq->reg_lock);
1568 ctrl = ensoniq->ctrl;
1569 if (ucontrol->value.integer.value[0])
1570 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1571 else
1572 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1573 changed = (ctrl != ensoniq->ctrl);
1574 if (changed)
1575 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1576 spin_unlock_irq(&ensoniq->reg_lock);
1577 return changed;
1578}
1579
eb3414b4 1580static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1da177e4
LT		 1581{
1582 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1583 .name = "Line In->Rear Out Switch",
1584 .info = snd_es1373_line_info,
1585 .get = snd_es1373_line_get,
1586 .put = snd_es1373_line_put,
1587};
1588
eb3414b4 1589static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1590{
eb3414b4 1591 struct ensoniq *ensoniq = ac97->private_data;
1da177e4
LT		 1592 ensoniq->u.es1371.ac97 = NULL;
1593}
1594
5da8fa25 1595struct es1371_quirk {
1da177e4
LT		 1596 unsigned short vid; /* vendor ID */
1597 unsigned short did; /* device ID */
1598 unsigned char rev; /* revision */
5da8fa25
TI		 1599};
1600
076c0e4f
RD		 1601static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1602 struct es1371_quirk *list)
5da8fa25
TI		 1603{
1604 while (list->vid != (unsigned short)PCI_ANY_ID) {
1605 if (ensoniq->pci->vendor == list->vid &&
1606 ensoniq->pci->device == list->did &&
1607 ensoniq->rev == list->rev)
1608 return 1;
1609 list++;
1610 }
1611 return 0;
1612}
1613
1614static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1da177e4
LT		 1615 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1616 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1617 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1618 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1619 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1620 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1621};
1622
5da8fa25
TI		 1623static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1624 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1625 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1626 { } /* end */
1627};
1628
1629static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1630 int has_spdif, int has_line)
1da177e4 1631{
eb3414b4
TI		 1632 struct snd_card *card = ensoniq->card;
1633 struct snd_ac97_bus *pbus;
1634 struct snd_ac97_template ac97;
5da8fa25 1635 int err;
eb3414b4 1636 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1637 .write = snd_es1371_codec_write,
1638 .read = snd_es1371_codec_read,
072c0119 1639 .wait = snd_es1371_codec_wait,
1da177e4
LT		 1640 };
1641
1642 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1643 return err;
1644
1645 memset(&ac97, 0, sizeof(ac97));
1646 ac97.private_data = ensoniq;
1647 ac97.private_free = snd_ensoniq_mixer_free_ac97;
462dba28 1648 ac97.pci = ensoniq->pci;
1da177e4
LT		 1649 ac97.scaps = AC97_SCAP_AUDIO;
1650 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1651 return err;
5da8fa25
TI		 1652 if (has_spdif > 0 ||
1653 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1654 struct snd_kcontrol *kctl;
405b0a37 1655 int i, is_spdif = 0;
5da8fa25
TI		 1656
1657 ensoniq->spdif_default = ensoniq->spdif_stream =
1658 SNDRV_PCM_DEFAULT_CON_SPDIF;
1659 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1660
1661 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
405b0a37 1662 is_spdif++;
5da8fa25
TI		 1663
1664 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1665 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1666 if (!kctl)
1667 return -ENOMEM;
405b0a37 1668 kctl->id.index = is_spdif;
5da8fa25
TI		 1669 err = snd_ctl_add(card, kctl);
1670 if (err < 0)
1671 return err;
1da177e4 1672 }
5da8fa25 1673 }
1da177e4
LT		 1674 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1675 /* mirror rear to front speakers */
1676 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1677 ensoniq->cssr |= ES_1373_REAR_BIT26;
1678 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1679 if (err < 0)
1680 return err;
1681 }
5da8fa25
TI		 1682 if (has_line > 0 ||
1683 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1684 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1685 ensoniq));
1da177e4
LT		 1686 if (err < 0)
1687 return err;
1688 }
1689
1690 return 0;
1691}
1692
1693#endif /* CHIP1371 */
1694
1695/* generic control callbacks for ens1370 */
1696#ifdef CHIP1370
1697#define ENSONIQ_CONTROL(xname, mask) \
1698{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1699 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1700 .private_value = mask }
1701
a5ce8890 1702#define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1da177e4 1703
eb3414b4
TI		 1704static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1705 struct snd_ctl_elem_value *ucontrol)
1da177e4 1706{
eb3414b4 1707 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1708 int mask = kcontrol->private_value;
1709
1710 spin_lock_irq(&ensoniq->reg_lock);
1711 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1712 spin_unlock_irq(&ensoniq->reg_lock);
1713 return 0;
1714}
1715
eb3414b4
TI		 1716static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1717 struct snd_ctl_elem_value *ucontrol)
1da177e4 1718{
eb3414b4 1719 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1720 int mask = kcontrol->private_value;
1721 unsigned int nval;
1722 int change;
1723
1724 nval = ucontrol->value.integer.value[0] ? mask : 0;
1725 spin_lock_irq(&ensoniq->reg_lock);
1726 change = (ensoniq->ctrl & mask) != nval;
1727 ensoniq->ctrl &= ~mask;
1728 ensoniq->ctrl |= nval;
1729 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1730 spin_unlock_irq(&ensoniq->reg_lock);
1731 return change;
1732}
1733
1734/*
1735 * ENS1370 mixer
1736 */
1737
eb3414b4 1738static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1da177e4
LT		 1739ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1740ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1741};
1742
1743#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1744
eb3414b4 1745static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1da177e4 1746{
eb3414b4 1747 struct ensoniq *ensoniq = ak4531->private_data;
1da177e4
LT		 1748 ensoniq->u.es1370.ak4531 = NULL;
1749}
1750
eb3414b4 1751static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1da177e4 1752{
eb3414b4
TI		 1753 struct snd_card *card = ensoniq->card;
1754 struct snd_ak4531 ak4531;
1da177e4
LT		 1755 unsigned int idx;
1756 int err;
1757
1758 /* try reset AK4531 */
1759 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1760 inw(ES_REG(ensoniq, 1370_CODEC));
1761 udelay(100);
1762 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1763 inw(ES_REG(ensoniq, 1370_CODEC));
1764 udelay(100);
1765
1766 memset(&ak4531, 0, sizeof(ak4531));
1767 ak4531.write = snd_es1370_codec_write;
1768 ak4531.private_data = ensoniq;
1769 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1770 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1771 return err;
1772 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1773 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1774 if (err < 0)
1775 return err;
1776 }
1777 return 0;
1778}
1779
1780#endif /* CHIP1370 */
1781
1782#ifdef SUPPORT_JOYSTICK
1783
1784#ifdef CHIP1371
1785static int __devinit snd_ensoniq_get_joystick_port(int dev)
1786{
1787 switch (joystick_port[dev]) {
1788 case 0: /* disabled */
1789 case 1: /* auto-detect */
1790 case 0x200:
1791 case 0x208:
1792 case 0x210:
1793 case 0x218:
1794 return joystick_port[dev];
1795
1796 default:
1797 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1798 return 0;
1799 }
1800}
1801#else
1802static inline int snd_ensoniq_get_joystick_port(int dev)
1803{
1804 return joystick[dev] ? 0x200 : 0;
1805}
1806#endif
1807
eb3414b4 1808static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1da177e4
LT		 1809{
1810 struct gameport *gp;
1811 int io_port;
1812
1813 io_port = snd_ensoniq_get_joystick_port(dev);
1814
1815 switch (io_port) {
1816 case 0:
1817 return -ENOSYS;
1818
1819 case 1: /* auto_detect */
1820 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1821 if (request_region(io_port, 8, "ens137x: gameport"))
1822 break;
1823 if (io_port > 0x218) {
1824 printk(KERN_WARNING "ens137x: no gameport ports available\n");
1825 return -EBUSY;
1826 }
1827 break;
1828
1829 default:
1830 if (!request_region(io_port, 8, "ens137x: gameport")) {
eb3414b4
TI		 1831 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1832 io_port);
1da177e4
LT		 1833 return -EBUSY;
1834 }
1835 break;
1836 }
1837
1838 ensoniq->gameport = gp = gameport_allocate_port();
1839 if (!gp) {
1840 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1841 release_region(io_port, 8);
1842 return -ENOMEM;
1843 }
1844
1845 gameport_set_name(gp, "ES137x");
1846 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1847 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1848 gp->io = io_port;
1849
1850 ensoniq->ctrl |= ES_JYSTK_EN;
1851#ifdef CHIP1371
1852 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1853 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1854#endif
1855 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1856
1857 gameport_register_port(ensoniq->gameport);
1858
1859 return 0;
1860}
1861
eb3414b4 1862static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1da177e4
LT		 1863{
1864 if (ensoniq->gameport) {
1865 int port = ensoniq->gameport->io;
1866
1867 gameport_unregister_port(ensoniq->gameport);
1868 ensoniq->gameport = NULL;
1869 ensoniq->ctrl &= ~ES_JYSTK_EN;
1870 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1871 release_region(port, 8);
1872 }
1873}
1874#else
eb3414b4
TI		 1875static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1876static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1da177e4
LT		 1877#endif /* SUPPORT_JOYSTICK */
1878
1879/*
1880
1881 */
1882
eb3414b4
TI		 1883static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1884 struct snd_info_buffer *buffer)
1da177e4 1885{
eb3414b4 1886 struct ensoniq *ensoniq = entry->private_data;
1da177e4
LT		 1887
1888#ifdef CHIP1370
1889 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1890#else
1891 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1892#endif
eb3414b4
TI		 1893 snd_iprintf(buffer, "Joystick enable : %s\n",
1894 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1da177e4 1895#ifdef CHIP1370
eb3414b4
TI		 1896 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1897 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1898 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1899 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1da177e4 1900#else
eb3414b4
TI		 1901 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1902 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1da177e4
LT		 1903#endif
1904}
1905
eb3414b4 1906static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1da177e4 1907{
eb3414b4 1908 struct snd_info_entry *entry;
1da177e4
LT		 1909
1910 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
bf850204 1911 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1da177e4
LT		 1912}
1913
1914/*
1915
1916 */
1917
eb3414b4 1918static int snd_ensoniq_free(struct ensoniq *ensoniq)
1da177e4
LT		 1919{
1920 snd_ensoniq_free_gameport(ensoniq);
1921 if (ensoniq->irq < 0)
1922 goto __hw_end;
1923#ifdef CHIP1370
1924 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1925 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1926#else
1927 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1928 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1929#endif
f000fd80
JG		 1930 if (ensoniq->irq >= 0)
1931 synchronize_irq(ensoniq->irq);
1da177e4
LT		 1932 pci_set_power_state(ensoniq->pci, 3);
1933 __hw_end:
1934#ifdef CHIP1370
1935 if (ensoniq->dma_bug.area)
1936 snd_dma_free_pages(&ensoniq->dma_bug);
1937#endif
1938 if (ensoniq->irq >= 0)
eb3414b4 1939 free_irq(ensoniq->irq, ensoniq);
1da177e4
LT		 1940 pci_release_regions(ensoniq->pci);
1941 pci_disable_device(ensoniq->pci);
1942 kfree(ensoniq);
1943 return 0;
1944}
1945
eb3414b4 1946static int snd_ensoniq_dev_free(struct snd_device *device)
1da177e4 1947{
eb3414b4 1948 struct ensoniq *ensoniq = device->device_data;
1da177e4
LT		 1949 return snd_ensoniq_free(ensoniq);
1950}
1951
1952#ifdef CHIP1371
5da8fa25
TI		 1953static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1954 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1955 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1956 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1957 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1958 { } /* end */
1da177e4 1959};
5da8fa25
TI		 1960
1961static struct es1371_quirk es1371_ac97_reset_hack[] = {
1da177e4
LT		 1962 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1963 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1964 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1965 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1966 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1967 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1968};
1969#endif
1970
eb3414b4 1971static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
f31a31b9
KB		 1972{
1973#ifdef CHIP1371
1974 int idx;
f31a31b9 1975#endif
eb3414b4
TI		 1976 /* this code was part of snd_ensoniq_create before intruduction
1977 * of suspend/resume
1978 */
f31a31b9
KB		 1979#ifdef CHIP1370
1980 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1981 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1982 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1983 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1984 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1985#else
1986 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1987 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1988 outl(0, ES_REG(ensoniq, 1371_LEGACY));
5da8fa25
TI		 1989 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1990 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1991 /* need to delay around 20ms(bleech) to give
1992 some CODECs enough time to wakeup */
1993 msleep(20);
1994 }
f31a31b9
KB		 1995 /* AC'97 warm reset to start the bitclk */
1996 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1997 inl(ES_REG(ensoniq, CONTROL));
1998 udelay(20);
1999 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2000 /* Init the sample rate converter */
2001 snd_es1371_wait_src_ready(ensoniq);
2002 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2003 for (idx = 0; idx < 0x80; idx++)
2004 snd_es1371_src_write(ensoniq, idx, 0);
2005 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2006 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2007 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2008 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2009 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2010 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2011 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2012 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2013 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2014 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2015 snd_es1371_adc_rate(ensoniq, 22050);
2016 snd_es1371_dac1_rate(ensoniq, 22050);
2017 snd_es1371_dac2_rate(ensoniq, 22050);
2018 /* WARNING:
2019 * enabling the sample rate converter without properly programming
2020 * its parameters causes the chip to lock up (the SRC busy bit will
2021 * be stuck high, and I've found no way to rectify this other than
2022 * power cycle) - Thomas Sailer
2023 */
2024 snd_es1371_wait_src_ready(ensoniq);
2025 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2026 /* try reset codec directly */
2027 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2028#endif
2029 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2030 outb(0x00, ES_REG(ensoniq, UART_RES));
2031 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2032 synchronize_irq(ensoniq->irq);
2033}
2034
2035#ifdef CONFIG_PM
68cb2b55 2036static int snd_ensoniq_suspend(struct device *dev)
f31a31b9 2037{
68cb2b55
TI		 2038 struct pci_dev *pci = to_pci_dev(dev);
2039 struct snd_card *card = dev_get_drvdata(dev);
fe8be107 2040 struct ensoniq *ensoniq = card->private_data;
f31a31b9 2041
fe8be107
TI		 2042 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2043
f31a31b9
KB		 2044 snd_pcm_suspend_all(ensoniq->pcm1);
2045 snd_pcm_suspend_all(ensoniq->pcm2);
2046
2047#ifdef CHIP1371
fe8be107 2048 snd_ac97_suspend(ensoniq->u.es1371.ac97);
f31a31b9 2049#else
15f500a6
TI		 2050 /* try to reset AK4531 */
2051 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2052 inw(ES_REG(ensoniq, 1370_CODEC));
2053 udelay(100);
2054 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2055 inw(ES_REG(ensoniq, 1370_CODEC));
2056 udelay(100);
fe8be107 2057 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
f31a31b9 2058#endif
30b35399 2059
fe8be107
TI		 2060 pci_disable_device(pci);
2061 pci_save_state(pci);
68cb2b55 2062 pci_set_power_state(pci, PCI_D3hot);
f31a31b9
KB		 2063 return 0;
2064}
2065
68cb2b55 2066static int snd_ensoniq_resume(struct device *dev)
f31a31b9 2067{
68cb2b55
TI		 2068 struct pci_dev *pci = to_pci_dev(dev);
2069 struct snd_card *card = dev_get_drvdata(dev);
fe8be107 2070 struct ensoniq *ensoniq = card->private_data;
f31a31b9 2071
fe8be107 2072 pci_set_power_state(pci, PCI_D0);
30b35399
TI		 2073 pci_restore_state(pci);
2074 if (pci_enable_device(pci) < 0) {
2075 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2076 "disabling device\n");
2077 snd_card_disconnect(card);
2078 return -EIO;
2079 }
fe8be107 2080 pci_set_master(pci);
f31a31b9
KB		 2081
2082 snd_ensoniq_chip_init(ensoniq);
2083
2084#ifdef CHIP1371
fe8be107 2085 snd_ac97_resume(ensoniq->u.es1371.ac97);
f31a31b9 2086#else
fe8be107 2087 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
f31a31b9 2088#endif
fe8be107 2089 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
f31a31b9
KB		 2090 return 0;
2091}
f31a31b9 2092
68cb2b55
TI		 2093static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2094#define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
2095#else
2096#define SND_ENSONIQ_PM_OPS NULL
2097#endif /* CONFIG_PM */
f31a31b9 2098
eb3414b4 2099static int __devinit snd_ensoniq_create(struct snd_card *card,
1da177e4 2100 struct pci_dev *pci,
eb3414b4 2101 struct ensoniq ** rensoniq)
1da177e4 2102{
eb3414b4 2103 struct ensoniq *ensoniq;
1da177e4 2104 int err;
eb3414b4 2105 static struct snd_device_ops ops = {
1da177e4
LT		 2106 .dev_free = snd_ensoniq_dev_free,
2107 };
2108
2109 *rensoniq = NULL;
2110 if ((err = pci_enable_device(pci)) < 0)
2111 return err;
e560d8d8 2112 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
1da177e4
LT		 2113 if (ensoniq == NULL) {
2114 pci_disable_device(pci);
2115 return -ENOMEM;
2116 }
2117 spin_lock_init(&ensoniq->reg_lock);
62932df8 2118 mutex_init(&ensoniq->src_mutex);
1da177e4
LT		 2119 ensoniq->card = card;
2120 ensoniq->pci = pci;
2121 ensoniq->irq = -1;
2122 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2123 kfree(ensoniq);
2124 pci_disable_device(pci);
2125 return err;
2126 }
2127 ensoniq->port = pci_resource_start(pci, 0);
437a5a46 2128 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
934c2b6d 2129 KBUILD_MODNAME, ensoniq)) {
99b359ba 2130 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2131 snd_ensoniq_free(ensoniq);
2132 return -EBUSY;
2133 }
2134 ensoniq->irq = pci->irq;
2135#ifdef CHIP1370
2136 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2137 16, &ensoniq->dma_bug) < 0) {
99b359ba 2138 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
1da177e4
LT		 2139 snd_ensoniq_free(ensoniq);
2140 return -EBUSY;
2141 }
2142#endif
2143 pci_set_master(pci);
44c10138 2144 ensoniq->rev = pci->revision;
1da177e4
LT		 2145#ifdef CHIP1370
2146#if 0
eb3414b4
TI		 2147 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2148 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1da177e4
LT		 2149#else /* get microphone working */
2150 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2151#endif
2152 ensoniq->sctrl = 0;
1da177e4
LT		 2153#else
2154 ensoniq->ctrl = 0;
2155 ensoniq->sctrl = 0;
2156 ensoniq->cssr = 0;
5da8fa25
TI		 2157 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2158 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2159
2160 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2161 ensoniq->cssr |= ES_1371_ST_AC97_RST;
1da177e4 2162#endif
f31a31b9
KB		 2163
2164 snd_ensoniq_chip_init(ensoniq);
1da177e4
LT		 2165
2166 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2167 snd_ensoniq_free(ensoniq);
2168 return err;
2169 }
2170
2171 snd_ensoniq_proc_init(ensoniq);
2172
2173 snd_card_set_dev(card, &pci->dev);
2174
2175 *rensoniq = ensoniq;
2176 return 0;
2177}
2178
2179/*
2180 * MIDI section
2181 */
2182
eb3414b4 2183static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
1da177e4 2184{
eb3414b4 2185 struct snd_rawmidi *rmidi = ensoniq->rmidi;
1da177e4
LT		 2186 unsigned char status, mask, byte;
2187
2188 if (rmidi == NULL)
2189 return;
2190 /* do Rx at first */
2191 spin_lock(&ensoniq->reg_lock);
2192 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2193 while (mask) {
2194 status = inb(ES_REG(ensoniq, UART_STATUS));
2195 if ((status & mask) == 0)
2196 break;
2197 byte = inb(ES_REG(ensoniq, UART_DATA));
2198 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2199 }
2200 spin_unlock(&ensoniq->reg_lock);
2201
2202 /* do Tx at second */
2203 spin_lock(&ensoniq->reg_lock);
2204 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2205 while (mask) {
2206 status = inb(ES_REG(ensoniq, UART_STATUS));
2207 if ((status & mask) == 0)
2208 break;
2209 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2210 ensoniq->uartc &= ~ES_TXINTENM;
2211 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2212 mask &= ~ES_TXRDY;
2213 } else {
2214 outb(byte, ES_REG(ensoniq, UART_DATA));
2215 }
2216 }
2217 spin_unlock(&ensoniq->reg_lock);
2218}
2219
eb3414b4 2220static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 2221{
eb3414b4 2222 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2223
2224 spin_lock_irq(&ensoniq->reg_lock);
2225 ensoniq->uartm |= ES_MODE_INPUT;
2226 ensoniq->midi_input = substream;
2227 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2228 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2229 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2230 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2231 }
2232 spin_unlock_irq(&ensoniq->reg_lock);
2233 return 0;
2234}
2235
eb3414b4 2236static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 2237{
eb3414b4 2238 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2239
2240 spin_lock_irq(&ensoniq->reg_lock);
2241 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2242 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2243 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2244 } else {
2245 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2246 }
2247 ensoniq->midi_input = NULL;
2248 ensoniq->uartm &= ~ES_MODE_INPUT;
2249 spin_unlock_irq(&ensoniq->reg_lock);
2250 return 0;
2251}
2252
eb3414b4 2253static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 2254{
eb3414b4 2255 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2256
2257 spin_lock_irq(&ensoniq->reg_lock);
2258 ensoniq->uartm |= ES_MODE_OUTPUT;
2259 ensoniq->midi_output = substream;
2260 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2261 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2262 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2263 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2264 }
2265 spin_unlock_irq(&ensoniq->reg_lock);
2266 return 0;
2267}
2268
eb3414b4 2269static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 2270{
eb3414b4 2271 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2272
2273 spin_lock_irq(&ensoniq->reg_lock);
2274 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2275 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2276 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2277 } else {
2278 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2279 }
2280 ensoniq->midi_output = NULL;
2281 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2282 spin_unlock_irq(&ensoniq->reg_lock);
2283 return 0;
2284}
2285
eb3414b4 2286static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2287{
2288 unsigned long flags;
eb3414b4 2289 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2290 int idx;
2291
2292 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2293 if (up) {
2294 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2295 /* empty input FIFO */
2296 for (idx = 0; idx < 32; idx++)
2297 inb(ES_REG(ensoniq, UART_DATA));
2298 ensoniq->uartc |= ES_RXINTEN;
2299 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2300 }
2301 } else {
2302 if (ensoniq->uartc & ES_RXINTEN) {
2303 ensoniq->uartc &= ~ES_RXINTEN;
2304 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2305 }
2306 }
2307 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2308}
2309
eb3414b4 2310static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2311{
2312 unsigned long flags;
eb3414b4 2313 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2314 unsigned char byte;
2315
2316 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2317 if (up) {
2318 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2319 ensoniq->uartc |= ES_TXINTENO(1);
2320 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2321 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2322 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2323 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2324 ensoniq->uartc &= ~ES_TXINTENM;
2325 } else {
2326 outb(byte, ES_REG(ensoniq, UART_DATA));
2327 }
2328 }
2329 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2330 }
2331 } else {
2332 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2333 ensoniq->uartc &= ~ES_TXINTENM;
2334 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2335 }
2336 }
2337 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2338}
2339
eb3414b4 2340static struct snd_rawmidi_ops snd_ensoniq_midi_output =
1da177e4
LT		 2341{
2342 .open = snd_ensoniq_midi_output_open,
2343 .close = snd_ensoniq_midi_output_close,
2344 .trigger = snd_ensoniq_midi_output_trigger,
2345};
2346
eb3414b4 2347static struct snd_rawmidi_ops snd_ensoniq_midi_input =
1da177e4
LT		 2348{
2349 .open = snd_ensoniq_midi_input_open,
2350 .close = snd_ensoniq_midi_input_close,
2351 .trigger = snd_ensoniq_midi_input_trigger,
2352};
2353
eb3414b4
TI		 2354static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2355 struct snd_rawmidi **rrawmidi)
1da177e4 2356{
eb3414b4 2357 struct snd_rawmidi *rmidi;
1da177e4
LT		 2358 int err;
2359
2360 if (rrawmidi)
2361 *rrawmidi = NULL;
2362 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2363 return err;
2364#ifdef CHIP1370
2365 strcpy(rmidi->name, "ES1370");
2366#else
2367 strcpy(rmidi->name, "ES1371");
2368#endif
2369 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2370 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
eb3414b4
TI		 2371 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2372 SNDRV_RAWMIDI_INFO_DUPLEX;
1da177e4
LT		 2373 rmidi->private_data = ensoniq;
2374 ensoniq->rmidi = rmidi;
2375 if (rrawmidi)
2376 *rrawmidi = rmidi;
2377 return 0;
2378}
2379
2380/*
2381 * Interrupt handler
2382 */
2383
7d12e780 2384static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
1da177e4 2385{
eb3414b4 2386 struct ensoniq *ensoniq = dev_id;
1da177e4
LT		 2387 unsigned int status, sctrl;
2388
2389 if (ensoniq == NULL)
2390 return IRQ_NONE;
2391
2392 status = inl(ES_REG(ensoniq, STATUS));
2393 if (!(status & ES_INTR))
2394 return IRQ_NONE;
2395
2396 spin_lock(&ensoniq->reg_lock);
2397 sctrl = ensoniq->sctrl;
2398 if (status & ES_DAC1)
2399 sctrl &= ~ES_P1_INT_EN;
2400 if (status & ES_DAC2)
2401 sctrl &= ~ES_P2_INT_EN;
2402 if (status & ES_ADC)
2403 sctrl &= ~ES_R1_INT_EN;
2404 outl(sctrl, ES_REG(ensoniq, SERIAL));
2405 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2406 spin_unlock(&ensoniq->reg_lock);
2407
2408 if (status & ES_UART)
2409 snd_ensoniq_midi_interrupt(ensoniq);
2410 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2411 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2412 if ((status & ES_ADC) && ensoniq->capture_substream)
2413 snd_pcm_period_elapsed(ensoniq->capture_substream);
2414 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2415 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2416 return IRQ_HANDLED;
2417}
2418
2419static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2420 const struct pci_device_id *pci_id)
2421{
2422 static int dev;
eb3414b4
TI		 2423 struct snd_card *card;
2424 struct ensoniq *ensoniq;
1da177e4
LT		 2425 int err, pcm_devs[2];
2426
2427 if (dev >= SNDRV_CARDS)
2428 return -ENODEV;
2429 if (!enable[dev]) {
2430 dev++;
2431 return -ENOENT;
2432 }
2433
e58de7ba
TI		 2434 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2435 if (err < 0)
2436 return err;
1da177e4
LT		 2437
2438 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2439 snd_card_free(card);
2440 return err;
2441 }
fe8be107 2442 card->private_data = ensoniq;
1da177e4
LT		 2443
2444 pcm_devs[0] = 0; pcm_devs[1] = 1;
2445#ifdef CHIP1370
2446 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2447 snd_card_free(card);
2448 return err;
2449 }
2450#endif
2451#ifdef CHIP1371
015b6a19 2452 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
1da177e4
LT		 2453 snd_card_free(card);
2454 return err;
2455 }
2456#endif
2457 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2458 snd_card_free(card);
2459 return err;
2460 }
2461 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2462 snd_card_free(card);
2463 return err;
2464 }
2465 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2466 snd_card_free(card);
2467 return err;
2468 }
2469
2470 snd_ensoniq_create_gameport(ensoniq, dev);
2471
2472 strcpy(card->driver, DRIVER_NAME);
2473
2474 strcpy(card->shortname, "Ensoniq AudioPCI");
2475 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2476 card->shortname,
2477 card->driver,
2478 ensoniq->port,
2479 ensoniq->irq);
2480
2481 if ((err = snd_card_register(card)) < 0) {
2482 snd_card_free(card);
2483 return err;
2484 }
2485
2486 pci_set_drvdata(pci, card);
2487 dev++;
2488 return 0;
2489}
2490
2491static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2492{
2493 snd_card_free(pci_get_drvdata(pci));
2494 pci_set_drvdata(pci, NULL);
2495}
2496
e9f66d9b 2497static struct pci_driver ens137x_driver = {
3733e424 2498 .name = KBUILD_MODNAME,
1da177e4
LT		 2499 .id_table = snd_audiopci_ids,
2500 .probe = snd_audiopci_probe,
2501 .remove = __devexit_p(snd_audiopci_remove),
68cb2b55
TI		 2502 .driver = {
2503 .pm = SND_ENSONIQ_PM_OPS,
2504 },
1da177e4
LT		 2505};
2506
e9f66d9b 2507module_pci_driver(ens137x_driver);
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