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a2fbb9ea ET |
1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. |
2 | * | |
3359fced | 3 | * Copyright (c) 2007-2010 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
523224a3 DK |
10 | #ifndef BNX2X_FW_DEFS_H |
11 | #define BNX2X_FW_DEFS_H | |
12 | ||
13 | #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[142].base) | |
14 | #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ | |
15 | (IRO[141].base + ((assertListEntry) * IRO[141].m1)) | |
16 | #define CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ | |
17 | (IRO[144].base + ((pfId) * IRO[144].m1)) | |
18 | #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ | |
19 | (IRO[149].base + (((pfId)>>1) * IRO[149].m1) + (((pfId)&1) * \ | |
20 | IRO[149].m2)) | |
21 | #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ | |
22 | (IRO[150].base + (((pfId)>>1) * IRO[150].m1) + (((pfId)&1) * \ | |
23 | IRO[150].m2)) | |
24 | #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ | |
25 | (IRO[156].base + ((funcId) * IRO[156].m1)) | |
26 | #define CSTORM_FUNC_EN_OFFSET(funcId) \ | |
27 | (IRO[146].base + ((funcId) * IRO[146].m1)) | |
28 | #define CSTORM_FUNCTION_MODE_OFFSET (IRO[153].base) | |
29 | #define CSTORM_IGU_MODE_OFFSET (IRO[154].base) | |
30 | #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ | |
31 | (IRO[311].base + ((pfId) * IRO[311].m1)) | |
32 | #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ | |
33 | (IRO[312].base + ((pfId) * IRO[312].m1)) | |
34 | #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ | |
35 | (IRO[304].base + ((pfId) * IRO[304].m1) + ((iscsiEqId) * \ | |
36 | IRO[304].m2)) | |
37 | #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ | |
38 | (IRO[306].base + ((pfId) * IRO[306].m1) + ((iscsiEqId) * \ | |
39 | IRO[306].m2)) | |
40 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ | |
41 | (IRO[305].base + ((pfId) * IRO[305].m1) + ((iscsiEqId) * \ | |
42 | IRO[305].m2)) | |
43 | #define \ | |
44 | CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ | |
45 | (IRO[307].base + ((pfId) * IRO[307].m1) + ((iscsiEqId) * \ | |
46 | IRO[307].m2)) | |
47 | #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ | |
48 | (IRO[303].base + ((pfId) * IRO[303].m1) + ((iscsiEqId) * \ | |
49 | IRO[303].m2)) | |
50 | #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ | |
51 | (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * \ | |
52 | IRO[309].m2)) | |
53 | #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ | |
54 | (IRO[308].base + ((pfId) * IRO[308].m1) + ((iscsiEqId) * \ | |
55 | IRO[308].m2)) | |
56 | #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ | |
57 | (IRO[310].base + ((pfId) * IRO[310].m1)) | |
58 | #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | |
59 | (IRO[302].base + ((pfId) * IRO[302].m1)) | |
60 | #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | |
61 | (IRO[301].base + ((pfId) * IRO[301].m1)) | |
62 | #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | |
63 | (IRO[300].base + ((pfId) * IRO[300].m1)) | |
64 | #define CSTORM_PATH_ID_OFFSET (IRO[159].base) | |
65 | #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ | |
66 | (IRO[137].base + ((pfId) * IRO[137].m1)) | |
67 | #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ | |
68 | (IRO[136].base + ((pfId) * IRO[136].m1)) | |
69 | #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[136].size) | |
70 | #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ | |
71 | (IRO[138].base + ((pfId) * IRO[138].m1)) | |
72 | #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[138].size) | |
73 | #define CSTORM_STATS_FLAGS_OFFSET(pfId) \ | |
74 | (IRO[143].base + ((pfId) * IRO[143].m1)) | |
75 | #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ | |
76 | (IRO[129].base + ((sbId) * IRO[129].m1)) | |
77 | #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ | |
78 | (IRO[128].base + ((sbId) * IRO[128].m1)) | |
79 | #define CSTORM_STATUS_BLOCK_SIZE (IRO[128].size) | |
80 | #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ | |
81 | (IRO[132].base + ((sbId) * IRO[132].m1)) | |
82 | #define CSTORM_SYNC_BLOCK_SIZE (IRO[132].size) | |
83 | #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \ | |
84 | (IRO[151].base + ((vfId) * IRO[151].m1)) | |
85 | #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \ | |
86 | (IRO[152].base + ((vfId) * IRO[152].m1)) | |
87 | #define CSTORM_VF_TO_PF_OFFSET(funcId) \ | |
88 | (IRO[147].base + ((funcId) * IRO[147].m1)) | |
89 | #define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[199].base) | |
90 | #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ | |
91 | (IRO[198].base + ((pfId) * IRO[198].m1)) | |
92 | #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[99].base) | |
93 | #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ | |
94 | (IRO[98].base + ((assertListEntry) * IRO[98].m1)) | |
95 | #define TSTORM_CLIENT_CONFIG_OFFSET(portId, clientId) \ | |
96 | (IRO[197].base + ((portId) * IRO[197].m1) + ((clientId) * \ | |
97 | IRO[197].m2)) | |
98 | #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[104].base) | |
ca00392c | 99 | #define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \ |
523224a3 DK |
100 | (IRO[105].base) |
101 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ | |
102 | (IRO[96].base + ((pfId) * IRO[96].m1)) | |
103 | #define TSTORM_FUNC_EN_OFFSET(funcId) \ | |
104 | (IRO[101].base + ((funcId) * IRO[101].m1)) | |
105 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ | |
106 | (IRO[195].base + ((pfId) * IRO[195].m1)) | |
107 | #define TSTORM_FUNCTION_MODE_OFFSET (IRO[103].base) | |
108 | #define TSTORM_INDIRECTION_TABLE_OFFSET(pfId) \ | |
109 | (IRO[91].base + ((pfId) * IRO[91].m1)) | |
110 | #define TSTORM_INDIRECTION_TABLE_SIZE (IRO[91].size) | |
111 | #define \ | |
112 | TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfId, iscsiConBufPblEntry) \ | |
113 | (IRO[260].base + ((pfId) * IRO[260].m1) + ((iscsiConBufPblEntry) \ | |
114 | * IRO[260].m2)) | |
115 | #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ | |
116 | (IRO[264].base + ((pfId) * IRO[264].m1)) | |
117 | #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \ | |
118 | (IRO[265].base + ((pfId) * IRO[265].m1)) | |
119 | #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \ | |
120 | (IRO[266].base + ((pfId) * IRO[266].m1)) | |
121 | #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \ | |
122 | (IRO[267].base + ((pfId) * IRO[267].m1)) | |
123 | #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | |
124 | (IRO[263].base + ((pfId) * IRO[263].m1)) | |
125 | #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | |
126 | (IRO[262].base + ((pfId) * IRO[262].m1)) | |
127 | #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | |
128 | (IRO[261].base + ((pfId) * IRO[261].m1)) | |
129 | #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ | |
130 | (IRO[259].base + ((pfId) * IRO[259].m1)) | |
131 | #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ | |
132 | (IRO[269].base + ((pfId) * IRO[269].m1)) | |
133 | #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ | |
134 | (IRO[256].base + ((pfId) * IRO[256].m1)) | |
135 | #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ | |
136 | (IRO[257].base + ((pfId) * IRO[257].m1)) | |
137 | #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ | |
138 | (IRO[258].base + ((pfId) * IRO[258].m1)) | |
139 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ | |
140 | (IRO[196].base + ((pfId) * IRO[196].m1)) | |
141 | #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(portId, tStatCntId) \ | |
142 | (IRO[100].base + ((portId) * IRO[100].m1) + ((tStatCntId) * \ | |
143 | IRO[100].m2)) | |
144 | #define TSTORM_STATS_FLAGS_OFFSET(pfId) \ | |
145 | (IRO[95].base + ((pfId) * IRO[95].m1)) | |
146 | #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ | |
147 | (IRO[211].base + ((pfId) * IRO[211].m1)) | |
148 | #define TSTORM_VF_TO_PF_OFFSET(funcId) \ | |
149 | (IRO[102].base + ((funcId) * IRO[102].m1)) | |
150 | #define USTORM_AGG_DATA_OFFSET (IRO[201].base) | |
151 | #define USTORM_AGG_DATA_SIZE (IRO[201].size) | |
152 | #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[170].base) | |
153 | #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ | |
154 | (IRO[169].base + ((assertListEntry) * IRO[169].m1)) | |
155 | #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ | |
156 | (IRO[178].base + ((portId) * IRO[178].m1)) | |
157 | #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ | |
158 | (IRO[172].base + ((pfId) * IRO[172].m1)) | |
159 | #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ | |
160 | (IRO[313].base + ((pfId) * IRO[313].m1)) | |
161 | #define USTORM_FUNC_EN_OFFSET(funcId) \ | |
162 | (IRO[174].base + ((funcId) * IRO[174].m1)) | |
163 | #define USTORM_FUNCTION_MODE_OFFSET (IRO[177].base) | |
164 | #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ | |
165 | (IRO[277].base + ((pfId) * IRO[277].m1)) | |
166 | #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ | |
167 | (IRO[278].base + ((pfId) * IRO[278].m1)) | |
168 | #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ | |
169 | (IRO[282].base + ((pfId) * IRO[282].m1)) | |
170 | #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ | |
171 | (IRO[279].base + ((pfId) * IRO[279].m1)) | |
172 | #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | |
173 | (IRO[275].base + ((pfId) * IRO[275].m1)) | |
174 | #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | |
175 | (IRO[274].base + ((pfId) * IRO[274].m1)) | |
176 | #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | |
177 | (IRO[273].base + ((pfId) * IRO[273].m1)) | |
178 | #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ | |
179 | (IRO[276].base + ((pfId) * IRO[276].m1)) | |
180 | #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ | |
181 | (IRO[280].base + ((pfId) * IRO[280].m1)) | |
182 | #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ | |
183 | (IRO[281].base + ((pfId) * IRO[281].m1)) | |
184 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ | |
185 | (IRO[176].base + ((pfId) * IRO[176].m1)) | |
186 | #define USTORM_PER_COUNTER_ID_STATS_OFFSET(portId, uStatCntId) \ | |
187 | (IRO[173].base + ((portId) * IRO[173].m1) + ((uStatCntId) * \ | |
188 | IRO[173].m2)) | |
189 | #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ | |
190 | (IRO[204].base + ((portId) * IRO[204].m1) + ((clientId) * \ | |
191 | IRO[204].m2)) | |
192 | #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ | |
193 | (IRO[205].base + ((qzoneId) * IRO[205].m1)) | |
194 | #define USTORM_STATS_FLAGS_OFFSET(pfId) \ | |
195 | (IRO[171].base + ((pfId) * IRO[171].m1)) | |
196 | #define USTORM_TPA_BTR_OFFSET (IRO[202].base) | |
197 | #define USTORM_TPA_BTR_SIZE (IRO[202].size) | |
198 | #define USTORM_VF_TO_PF_OFFSET(funcId) \ | |
199 | (IRO[175].base + ((funcId) * IRO[175].m1)) | |
200 | #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[59].base) | |
201 | #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[58].base) | |
202 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[54].base) | |
203 | #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ | |
204 | (IRO[53].base + ((assertListEntry) * IRO[53].m1)) | |
205 | #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ | |
206 | (IRO[47].base + ((portId) * IRO[47].m1)) | |
207 | #define XSTORM_E1HOV_OFFSET(pfId) \ | |
208 | (IRO[55].base + ((pfId) * IRO[55].m1)) | |
209 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ | |
210 | (IRO[45].base + ((pfId) * IRO[45].m1)) | |
211 | #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ | |
212 | (IRO[49].base + ((pfId) * IRO[49].m1)) | |
213 | #define XSTORM_FUNC_EN_OFFSET(funcId) \ | |
214 | (IRO[51].base + ((funcId) * IRO[51].m1)) | |
215 | #define XSTORM_FUNCTION_MODE_OFFSET (IRO[56].base) | |
216 | #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ | |
217 | (IRO[290].base + ((pfId) * IRO[290].m1)) | |
218 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ | |
219 | (IRO[293].base + ((pfId) * IRO[293].m1)) | |
220 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ | |
221 | (IRO[294].base + ((pfId) * IRO[294].m1)) | |
222 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ | |
223 | (IRO[295].base + ((pfId) * IRO[295].m1)) | |
224 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ | |
225 | (IRO[296].base + ((pfId) * IRO[296].m1)) | |
226 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ | |
227 | (IRO[297].base + ((pfId) * IRO[297].m1)) | |
228 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ | |
229 | (IRO[298].base + ((pfId) * IRO[298].m1)) | |
230 | #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ | |
231 | (IRO[299].base + ((pfId) * IRO[299].m1)) | |
232 | #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | |
233 | (IRO[289].base + ((pfId) * IRO[289].m1)) | |
234 | #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | |
235 | (IRO[288].base + ((pfId) * IRO[288].m1)) | |
236 | #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | |
237 | (IRO[287].base + ((pfId) * IRO[287].m1)) | |
238 | #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ | |
239 | (IRO[292].base + ((pfId) * IRO[292].m1)) | |
240 | #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ | |
241 | (IRO[291].base + ((pfId) * IRO[291].m1)) | |
242 | #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ | |
243 | (IRO[286].base + ((pfId) * IRO[286].m1)) | |
244 | #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ | |
245 | (IRO[285].base + ((pfId) * IRO[285].m1)) | |
246 | #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ | |
247 | (IRO[284].base + ((pfId) * IRO[284].m1)) | |
248 | #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ | |
249 | (IRO[283].base + ((pfId) * IRO[283].m1)) | |
250 | #define XSTORM_PATH_ID_OFFSET (IRO[65].base) | |
251 | #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(portId, xStatCntId) \ | |
252 | (IRO[50].base + ((portId) * IRO[50].m1) + ((xStatCntId) * \ | |
253 | IRO[50].m2)) | |
254 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ | |
255 | (IRO[48].base + ((pfId) * IRO[48].m1)) | |
256 | #define XSTORM_SPQ_DATA_OFFSET(funcId) \ | |
257 | (IRO[32].base + ((funcId) * IRO[32].m1)) | |
258 | #define XSTORM_SPQ_DATA_SIZE (IRO[32].size) | |
259 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ | |
260 | (IRO[30].base + ((funcId) * IRO[30].m1)) | |
261 | #define XSTORM_SPQ_PROD_OFFSET(funcId) \ | |
262 | (IRO[31].base + ((funcId) * IRO[31].m1)) | |
263 | #define XSTORM_STATS_FLAGS_OFFSET(pfId) \ | |
264 | (IRO[43].base + ((pfId) * IRO[43].m1)) | |
265 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ | |
266 | (IRO[206].base + ((portId) * IRO[206].m1)) | |
267 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ | |
268 | (IRO[207].base + ((portId) * IRO[207].m1)) | |
269 | #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ | |
270 | (IRO[209].base + (((pfId)>>1) * IRO[209].m1) + (((pfId)&1) * \ | |
271 | IRO[209].m2)) | |
272 | #define XSTORM_VF_TO_PF_OFFSET(funcId) \ | |
273 | (IRO[52].base + ((funcId) * IRO[52].m1)) | |
a2fbb9ea ET |
274 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 |
275 | ||
34f80b04 EG |
276 | /* RSS hash types */ |
277 | #define DEFAULT_HASH_TYPE 0 | |
278 | #define IPV4_HASH_TYPE 1 | |
279 | #define TCP_IPV4_HASH_TYPE 2 | |
280 | #define IPV6_HASH_TYPE 3 | |
281 | #define TCP_IPV6_HASH_TYPE 4 | |
ca00392c EG |
282 | #define VLAN_PRI_HASH_TYPE 5 |
283 | #define E1HOV_PRI_HASH_TYPE 6 | |
284 | #define DSCP_HASH_TYPE 7 | |
34f80b04 | 285 | |
f5372251 EG |
286 | |
287 | /* Ethernet Ring parameters */ | |
34f80b04 EG |
288 | #define X_ETH_LOCAL_RING_SIZE 13 |
289 | #define FIRST_BD_IN_PKT 0 | |
290 | #define PARSE_BD_INDEX 1 | |
356e2385 | 291 | #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) |
ca00392c EG |
292 | #define U_ETH_NUM_OF_SGES_TO_FETCH 8 |
293 | #define U_ETH_MAX_SGES_FOR_PACKET 3 | |
34f80b04 | 294 | |
523224a3 DK |
295 | /*Tx params*/ |
296 | #define X_ETH_NO_VLAN 0 | |
297 | #define X_ETH_OUTBAND_VLAN 1 | |
298 | #define X_ETH_INBAND_VLAN 2 | |
34f80b04 | 299 | /* Rx ring params */ |
ca00392c EG |
300 | #define U_ETH_LOCAL_BD_RING_SIZE 8 |
301 | #define U_ETH_LOCAL_SGE_RING_SIZE 10 | |
356e2385 | 302 | #define U_ETH_SGL_SIZE 8 |
523224a3 DK |
303 | /* The fw will padd the buffer with this value, so the IP header \ |
304 | will be align to 4 Byte */ | |
305 | #define IP_HEADER_ALIGNMENT_PADDING 2 | |
34f80b04 | 306 | |
34f80b04 EG |
307 | #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ |
308 | (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) | |
309 | ||
ca00392c | 310 | #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) |
34f80b04 EG |
311 | #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) |
312 | #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) | |
313 | ||
ca00392c EG |
314 | #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) |
315 | #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) | |
316 | #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) | |
317 | ||
34f80b04 | 318 | #define U_ETH_UNDEFINED_Q 0xFF |
a2fbb9ea ET |
319 | |
320 | /* values of command IDs in the ramrod message */ | |
523224a3 DK |
321 | #define RAMROD_CMD_ID_ETH_UNUSED 0 |
322 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP 1 | |
323 | #define RAMROD_CMD_ID_ETH_UPDATE 2 | |
324 | #define RAMROD_CMD_ID_ETH_HALT 3 | |
325 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP 4 | |
326 | #define RAMROD_CMD_ID_ETH_ACTIVATE 5 | |
327 | #define RAMROD_CMD_ID_ETH_DEACTIVATE 6 | |
328 | #define RAMROD_CMD_ID_ETH_EMPTY 7 | |
329 | #define RAMROD_CMD_ID_ETH_TERMINATE 8 | |
a2fbb9ea ET |
330 | |
331 | /* command values for set mac command */ | |
34f80b04 EG |
332 | #define T_ETH_MAC_COMMAND_SET 0 |
333 | #define T_ETH_MAC_COMMAND_INVALIDATE 1 | |
334 | ||
335 | #define T_ETH_INDIRECTION_TABLE_SIZE 128 | |
a2fbb9ea | 336 | |
34f80b04 EG |
337 | /*The CRC32 seed, that is used for the hash(reduction) multicast address */ |
338 | #define T_ETH_CRC32_HASH_SEED 0x00000000 | |
a2fbb9ea ET |
339 | |
340 | /* Maximal L2 clients supported */ | |
ca00392c | 341 | #define ETH_MAX_RX_CLIENTS_E1 18 |
523224a3 DK |
342 | #define ETH_MAX_RX_CLIENTS_E1H 28 |
343 | ||
344 | #define MAX_STAT_COUNTER_ID ETH_MAX_RX_CLIENTS_E1H | |
34f80b04 EG |
345 | |
346 | /* Maximal aggregation queues supported */ | |
356e2385 EG |
347 | #define ETH_MAX_AGGREGATION_QUEUES_E1 32 |
348 | #define ETH_MAX_AGGREGATION_QUEUES_E1H 64 | |
34f80b04 | 349 | |
555f6c78 EG |
350 | /* ETH RSS modes */ |
351 | #define ETH_RSS_MODE_DISABLED 0 | |
352 | #define ETH_RSS_MODE_REGULAR 1 | |
ca00392c EG |
353 | #define ETH_RSS_MODE_VLAN_PRI 2 |
354 | #define ETH_RSS_MODE_E1HOV_PRI 3 | |
355 | #define ETH_RSS_MODE_IP_DSCP 4 | |
523224a3 DK |
356 | #define ETH_RSS_MODE_E2_INTEG 5 |
357 | ||
358 | ||
359 | /* ETH vlan filtering modes */ | |
360 | #define ETH_VLAN_FILTER_ANY_VLAN 0 /* Don't filter by vlan */ | |
361 | #define ETH_VLAN_FILTER_SPECIFIC_VLAN \ | |
362 | 1 /* Only the vlan_id is allowed */ | |
363 | #define ETH_VLAN_FILTER_CLASSIFY \ | |
364 | 2 /* vlan will be added to CAM for classification */ | |
365 | ||
366 | /* Fast path CQE selection */ | |
367 | #define ETH_FP_CQE_REGULAR 0 | |
368 | #define ETH_FP_CQE_SGL 1 | |
369 | #define ETH_FP_CQE_RAW 2 | |
555f6c78 | 370 | |
a2fbb9ea ET |
371 | |
372 | /** | |
f5372251 | 373 | * This file defines HSI constants common to all microcode flows |
a2fbb9ea ET |
374 | */ |
375 | ||
376 | /* Connection types */ | |
34f80b04 EG |
377 | #define ETH_CONNECTION_TYPE 0 |
378 | #define TOE_CONNECTION_TYPE 1 | |
379 | #define RDMA_CONNECTION_TYPE 2 | |
380 | #define ISCSI_CONNECTION_TYPE 3 | |
381 | #define FCOE_CONNECTION_TYPE 4 | |
382 | #define RESERVED_CONNECTION_TYPE_0 5 | |
383 | #define RESERVED_CONNECTION_TYPE_1 6 | |
384 | #define RESERVED_CONNECTION_TYPE_2 7 | |
523224a3 | 385 | #define NONE_CONNECTION_TYPE 8 |
34f80b04 | 386 | |
a2fbb9ea | 387 | |
34f80b04 | 388 | #define PROTOCOL_STATE_BIT_OFFSET 6 |
a2fbb9ea | 389 | |
34f80b04 EG |
390 | #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) |
391 | #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
392 | #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
a2fbb9ea | 393 | |
523224a3 DK |
394 | /* values of command IDs in the ramrod message */ |
395 | #define RAMROD_CMD_ID_COMMON_FUNCTION_START 1 | |
396 | #define RAMROD_CMD_ID_COMMON_FUNCTION_STOP 2 | |
397 | #define RAMROD_CMD_ID_COMMON_CFC_DEL 3 | |
398 | #define RAMROD_CMD_ID_COMMON_CFC_DEL_WB 4 | |
399 | #define RAMROD_CMD_ID_COMMON_SET_MAC 5 | |
400 | #define RAMROD_CMD_ID_COMMON_STAT_QUERY 6 | |
401 | #define RAMROD_CMD_ID_COMMON_STOP_TRAFFIC 7 | |
402 | #define RAMROD_CMD_ID_COMMON_START_TRAFFIC 8 | |
403 | ||
a2fbb9ea | 404 | /* microcode fixed page page size 4K (chains and ring segments) */ |
356e2385 | 405 | #define MC_PAGE_SIZE 4096 |
a2fbb9ea | 406 | |
a2fbb9ea | 407 | |
34f80b04 | 408 | /* Host coalescing constants */ |
3359fced VZ |
409 | #define HC_IGU_BC_MODE 0 |
410 | #define HC_IGU_NBC_MODE 1 | |
523224a3 DK |
411 | /* Host coalescing constants. E1 includes E1H as well */ |
412 | ||
413 | /* Number of indices per slow-path SB */ | |
414 | #define HC_SP_SB_MAX_INDICES 16 | |
415 | ||
416 | /* Number of indices per SB */ | |
417 | #define HC_SB_MAX_INDICES_E1X 8 | |
418 | #define HC_SB_MAX_INDICES_E2 8 | |
419 | ||
420 | #define HC_SB_MAX_SB_E1X 32 | |
421 | #define HC_SB_MAX_SB_E2 136 | |
422 | ||
423 | #define HC_SP_SB_ID 0xde | |
3359fced VZ |
424 | |
425 | #define HC_REGULAR_SEGMENT 0 | |
426 | #define HC_DEFAULT_SEGMENT 1 | |
523224a3 | 427 | #define HC_SB_MAX_SM 2 |
a2fbb9ea | 428 | |
523224a3 DK |
429 | #define HC_SB_MAX_DYNAMIC_INDICES 4 |
430 | #define HC_FUNCTION_DISABLED 0xff | |
a2fbb9ea | 431 | /* used by the driver to get the SB offset */ |
34f80b04 EG |
432 | #define USTORM_ID 0 |
433 | #define CSTORM_ID 1 | |
434 | #define XSTORM_ID 2 | |
435 | #define TSTORM_ID 3 | |
436 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
437 | |
438 | /* max number of slow path commands per port */ | |
356e2385 | 439 | #define MAX_RAMRODS_PER_PORT 8 |
a2fbb9ea ET |
440 | |
441 | /* values for RX ETH CQE type field */ | |
356e2385 EG |
442 | #define RX_ETH_CQE_TYPE_ETH_FASTPATH 0 |
443 | #define RX_ETH_CQE_TYPE_ETH_RAMROD 1 | |
34f80b04 EG |
444 | |
445 | ||
446 | /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | |
34f80b04 EG |
447 | |
448 | #define TIMERS_TICK_SIZE_CHIP (1e-3) | |
34f80b04 EG |
449 | |
450 | #define TSEMI_CLK1_RESUL_CHIP (1e-3) | |
34f80b04 EG |
451 | |
452 | #define XSEMI_CLK1_RESUL_CHIP (1e-3) | |
34f80b04 EG |
453 | |
454 | #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6)) | |
34f80b04 EG |
455 | |
456 | /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | |
523224a3 | 457 | |
a2fbb9ea ET |
458 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 |
459 | #define XSTORM_IP_ID_ROLL_ALL 0 | |
460 | ||
356e2385 | 461 | #define FW_LOG_LIST_SIZE 50 |
34f80b04 EG |
462 | |
463 | #define NUM_OF_PROTOCOLS 4 | |
8d9c5f34 EG |
464 | #define NUM_OF_SAFC_BITS 16 |
465 | #define MAX_COS_NUMBER 4 | |
8d9c5f34 | 466 | |
523224a3 DK |
467 | #define FAIRNESS_COS_WRR_MODE 0 |
468 | #define FAIRNESS_COS_ETS_MODE 1 | |
469 | ||
470 | ||
471 | /* Priority Flow Control (PFC) */ | |
472 | #define MAX_PFC_PRIORITIES 8 | |
473 | #define MAX_PFC_TRAFFIC_TYPES 8 | |
474 | ||
475 | /* Available Traffic Types for Link Layer Flow Control */ | |
476 | #define LLFC_TRAFFIC_TYPE_NW 0 | |
477 | #define LLFC_TRAFFIC_TYPE_FCOE 1 | |
478 | #define LLFC_TRAFFIC_TYPE_ISCSI 2 | |
479 | /***************** START OF E2 INTEGRATION \ | |
480 | CODE***************************************/ | |
481 | #define LLFC_TRAFFIC_TYPE_NW_COS1_E2INTEG 3 | |
482 | /***************** END OF E2 INTEGRATION \ | |
483 | CODE***************************************/ | |
484 | #define LLFC_TRAFFIC_TYPE_MAX 4 | |
485 | ||
486 | /* used by array traffic_type_to_priority[] to mark traffic type \ | |
487 | that is not mapped to priority*/ | |
488 | #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF | |
489 | ||
490 | #define LLFC_MODE_NONE 0 | |
491 | #define LLFC_MODE_PFC 1 | |
492 | #define LLFC_MODE_SAFC 2 | |
493 | ||
494 | #define DCB_DISABLED 0 | |
495 | #define DCB_ENABLED 1 | |
a2fbb9ea | 496 | |
34f80b04 EG |
497 | #define UNKNOWN_ADDRESS 0 |
498 | #define UNICAST_ADDRESS 1 | |
499 | #define MULTICAST_ADDRESS 2 | |
500 | #define BROADCAST_ADDRESS 3 | |
a2fbb9ea | 501 | |
34f80b04 | 502 | #define SINGLE_FUNCTION 0 |
523224a3 DK |
503 | #define MULTI_FUNCTION_SD 1 |
504 | #define MULTI_FUNCTION_SI 2 | |
a2fbb9ea | 505 | |
34f80b04 EG |
506 | #define IP_V4 0 |
507 | #define IP_V6 1 | |
a2fbb9ea | 508 | |
523224a3 DK |
509 | |
510 | #define C_ERES_PER_PAGE \ | |
511 | (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem))) | |
512 | #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1) | |
513 | ||
514 | #define EVENT_RING_OPCODE_VF_PF_CHANNEL 0 | |
515 | #define EVENT_RING_OPCODE_FUNCTION_START 1 | |
516 | #define EVENT_RING_OPCODE_FUNCTION_STOP 2 | |
517 | #define EVENT_RING_OPCODE_CFC_DEL 3 | |
518 | #define EVENT_RING_OPCODE_CFC_DEL_WB 4 | |
519 | #define EVENT_RING_OPCODE_SET_MAC 5 | |
520 | #define EVENT_RING_OPCODE_STAT_QUERY 6 | |
521 | #define EVENT_RING_OPCODE_STOP_TRAFFIC 7 | |
522 | #define EVENT_RING_OPCODE_START_TRAFFIC 8 | |
523 | #define EVENT_RING_OPCODE_FORWARD_SETUP 9 | |
524 | ||
525 | #define VF_PF_CHANNEL_STATE_READY 0 | |
526 | #define VF_PF_CHANNEL_STATE_WAITING_FOR_ACK 1 | |
527 | ||
528 | #define VF_PF_CHANNEL_STATE_MAX_NUMBER 2 | |
529 | ||
530 | ||
531 | #endif /* BNX2X_FW_DEFS_H */ |