[linux.git] / drivers / gpio / gpio-tc3589x.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Hanumath Prasad <[email protected]> for ST-Ericsson
 * Author: Rabin Vincent <[email protected]> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_IBE, REG_IEV, REG_IS, REG_IE };

#define CACHE_NR_REGS	4
#define CACHE_NR_BANKS	3

struct tc3589x_gpio {
	struct gpio_chip chip;
	struct tc3589x *tc3589x;
	struct device *dev;
	struct mutex irq_lock;

	int irq_base;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct tc3589x_gpio, chip);
}

static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return ret & mask;
}

static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	unsigned pos = offset % 8;
	u8 data[] = {!!val << pos, 1 << pos};

	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}

static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	tc3589x_gpio_set(chip, offset, val);

	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
}

static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
}

static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);

	return tc3589x_gpio->irq_base + offset;
}

static struct gpio_chip template_chip = {
	.label			= "tc3589x",
	.owner			= THIS_MODULE,
	.direction_input	= tc3589x_gpio_direction_input,
	.get			= tc3589x_gpio_get,
	.direction_output	= tc3589x_gpio_direction_output,
	.set			= tc3589x_gpio_set,
	.to_irq			= tc3589x_gpio_to_irq,
	.can_sleep		= 1,
};

static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tc3589x_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_EDGE_BOTH) {
		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
		return 0;
	}

	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;

	return 0;
}

static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);

	mutex_lock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	static const u8 regmap[] = {
		[REG_IBE]	= TC3589x_GPIOIBE0,
		[REG_IEV]	= TC3589x_GPIOIEV0,
		[REG_IS]	= TC3589x_GPIOIS0,
		[REG_IE]	= TC3589x_GPIOIE0,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < CACHE_NR_BANKS; j++) {
			u8 old = tc3589x_gpio->oldregs[i][j];
			u8 new = tc3589x_gpio->regs[i][j];

			if (new == old)
				continue;

			tc3589x_gpio->oldregs[i][j] = new;
			tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
		}
	}

	mutex_unlock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tc3589x_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tc3589x_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip tc3589x_gpio_irq_chip = {
	.name			= "tc3589x-gpio",
	.irq_bus_lock		= tc3589x_gpio_irq_lock,
	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
	.irq_mask		= tc3589x_gpio_irq_mask,
	.irq_unmask		= tc3589x_gpio_irq_unmask,
	.irq_set_type		= tc3589x_gpio_irq_set_type,
};

static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
	struct tc3589x_gpio *tc3589x_gpio = dev;
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 status[CACHE_NR_BANKS];
	int ret;
	int i;

	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
				 ARRAY_SIZE(status), status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < ARRAY_SIZE(status); i++) {
		unsigned int stat = status[i];
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = i * 8 + bit;

			handle_nested_irq(tc3589x_gpio->irq_base + line);
			stat &= ~(1 << bit);
		}

		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
	}

	return IRQ_HANDLED;
}

static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio)
{
	int base = tc3589x_gpio->irq_base;
	int irq;

	for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
		irq_set_chip_data(irq, tc3589x_gpio);
		irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
					 handle_simple_irq);
		irq_set_nested_thread(irq, 1);
#ifdef CONFIG_ARM
		set_irq_flags(irq, IRQF_VALID);
#else
		irq_set_noprobe(irq);
#endif
	}

	return 0;
}

static void tc3589x_gpio_irq_remove(struct tc3589x_gpio *tc3589x_gpio)
{
	int base = tc3589x_gpio->irq_base;
	int irq;

	for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
#ifdef CONFIG_ARM
		set_irq_flags(irq, 0);
#endif
		irq_set_chip_and_handler(irq, NULL, NULL);
		irq_set_chip_data(irq, NULL);
	}
}

static int __devinit tc3589x_gpio_probe(struct platform_device *pdev)
{
	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	struct tc3589x_gpio_platform_data *pdata;
	struct tc3589x_gpio *tc3589x_gpio;
	int ret;
	int irq;

	pdata = tc3589x->pdata->gpio;
	if (!pdata)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
	if (!tc3589x_gpio)
		return -ENOMEM;

	mutex_init(&tc3589x_gpio->irq_lock);

	tc3589x_gpio->dev = &pdev->dev;
	tc3589x_gpio->tc3589x = tc3589x;

	tc3589x_gpio->chip = template_chip;
	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	tc3589x_gpio->chip.dev = &pdev->dev;
	tc3589x_gpio->chip.base = pdata->gpio_base;

	tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0);

	/* Bring the GPIO module out of reset */
	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
			       TC3589x_RSTCTRL_GPIRST, 0);
	if (ret < 0)
		goto out_free;

	ret = tc3589x_gpio_irq_init(tc3589x_gpio);
	if (ret)
		goto out_free;

	ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
				   "tc3589x-gpio", tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		goto out_removeirq;
	}

	ret = gpiochip_add(&tc3589x_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata->setup)
		pdata->setup(tc3589x, tc3589x_gpio->chip.base);

	platform_set_drvdata(pdev, tc3589x_gpio);

	return 0;

out_freeirq:
	free_irq(irq, tc3589x_gpio);
out_removeirq:
	tc3589x_gpio_irq_remove(tc3589x_gpio);
out_free:
	kfree(tc3589x_gpio);
	return ret;
}

static int __devexit tc3589x_gpio_remove(struct platform_device *pdev)
{
	struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata->remove)
		pdata->remove(tc3589x, tc3589x_gpio->chip.base);

	ret = gpiochip_remove(&tc3589x_gpio->chip);
	if (ret < 0) {
		dev_err(tc3589x_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	free_irq(irq, tc3589x_gpio);
	tc3589x_gpio_irq_remove(tc3589x_gpio);

	platform_set_drvdata(pdev, NULL);
	kfree(tc3589x_gpio);

	return 0;
}

static struct platform_driver tc3589x_gpio_driver = {
	.driver.name	= "tc3589x-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= tc3589x_gpio_probe,
	.remove		= __devexit_p(tc3589x_gpio_remove),
};

static int __init tc3589x_gpio_init(void)
{
	return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);

static void __exit tc3589x_gpio_exit(void)
{
	platform_driver_unregister(&tc3589x_gpio_driver);
}
module_exit(tc3589x_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TC3589x GPIO driver");
MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");
Commit	Line	Data
d88b25be RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Hanumath Prasad <[email protected]> for ST-Ericsson
	6	* Author: Rabin Vincent <[email protected]> for ST-Ericsson
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/slab.h>
	13	#include <linux/gpio.h>
	14	#include <linux/irq.h>
	15	#include <linux/interrupt.h>
c6eda6c5	16	#include <linux/mfd/tc3589x.h>
d88b25be RV	17
	18	/*
	19	* These registers are modified under the irq bus lock and cached to avoid
	20	* unnecessary writes in bus_sync_unlock.
	21	*/
	22	enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
	23
	24	#define CACHE_NR_REGS 4
	25	#define CACHE_NR_BANKS 3
	26
20406ebf	27	struct tc3589x_gpio {
d88b25be	28	struct gpio_chip chip;
20406ebf	29	struct tc3589x *tc3589x;
d88b25be RV	30	struct device *dev;
	31	struct mutex irq_lock;
	32
	33	int irq_base;
	34
	35	/* Caches of interrupt control registers for bus_lock */
	36	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	37	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	38	};
	39
20406ebf	40	static inline struct tc3589x_gpio to_tc3589x_gpio(struct gpio_chip chip)
d88b25be	41	{
20406ebf	42	return container_of(chip, struct tc3589x_gpio, chip);
d88b25be RV	43	}
d88b25be RV	44
20406ebf	45	static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
d88b25be	46	{
20406ebf SI	47	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	48	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	49	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be RV	50	u8 mask = 1 << (offset % 8);
	51	int ret;
	52
20406ebf	53	ret = tc3589x_reg_read(tc3589x, reg);
d88b25be RV	54	if (ret < 0)
	55	return ret;
	56
	57	return ret & mask;
	58	}
	59
20406ebf	60	static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
d88b25be	61	{
20406ebf SI	62	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	63	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	64	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be RV	65	unsigned pos = offset % 8;
	66	u8 data[] = {!!val << pos, 1 << pos};
	67
20406ebf	68	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
d88b25be RV	69	}
d88b25be RV	70
20406ebf	71	static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
d88b25be RV	72	unsigned offset, int val)
d88b25be RV	73	{
20406ebf SI	74	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	75	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	76	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	77	unsigned pos = offset % 8;
d88b25be RV	78
20406ebf	79	tc3589x_gpio_set(chip, offset, val);
d88b25be	80
20406ebf	81	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
d88b25be RV	82	}
d88b25be RV	83
20406ebf	84	static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
d88b25be RV	85	unsigned offset)
d88b25be RV	86	{
20406ebf SI	87	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	88	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	89	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	90	unsigned pos = offset % 8;
d88b25be RV	91
20406ebf	92	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
d88b25be RV	93	}
d88b25be RV	94
20406ebf	95	static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
d88b25be	96	{
20406ebf	97	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
d88b25be	98
20406ebf	99	return tc3589x_gpio->irq_base + offset;
d88b25be RV	100	}
	101
	102	static struct gpio_chip template_chip = {
20406ebf	103	.label = "tc3589x",
d88b25be	104	.owner = THIS_MODULE,
20406ebf SI	105	.direction_input = tc3589x_gpio_direction_input,
	106	.get = tc3589x_gpio_get,
	107	.direction_output = tc3589x_gpio_direction_output,
	108	.set = tc3589x_gpio_set,
	109	.to_irq = tc3589x_gpio_to_irq,
d88b25be RV	110	.can_sleep = 1,
	111	};
	112
33fcc1b8	113	static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
d88b25be	114	{
33fcc1b8 LB	115	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
33fcc1b8 LB	116	int offset = d->irq - tc3589x_gpio->irq_base;
d88b25be RV	117	int regoffset = offset / 8;
	118	int mask = 1 << (offset % 8);
	119
	120	if (type == IRQ_TYPE_EDGE_BOTH) {
20406ebf	121	tc3589x_gpio->regs[REG_IBE][regoffset] \|= mask;
d88b25be RV	122	return 0;
	123	}
	124
20406ebf	125	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
d88b25be RV	126
d88b25be RV	127	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	128	tc3589x_gpio->regs[REG_IS][regoffset] \|= mask;
d88b25be	129	else
20406ebf	130	tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
d88b25be RV	131
d88b25be RV	132	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	133	tc3589x_gpio->regs[REG_IEV][regoffset] \|= mask;
d88b25be	134	else
20406ebf	135	tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
d88b25be RV	136
	137	return 0;
	138	}
	139
33fcc1b8	140	static void tc3589x_gpio_irq_lock(struct irq_data *d)
d88b25be	141	{
33fcc1b8	142	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
d88b25be	143
20406ebf	144	mutex_lock(&tc3589x_gpio->irq_lock);
d88b25be RV	145	}
d88b25be RV	146
33fcc1b8	147	static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
d88b25be	148	{
33fcc1b8	149	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
20406ebf	150	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be	151	static const u8 regmap[] = {
20406ebf SI	152	[REG_IBE] = TC3589x_GPIOIBE0,
	153	[REG_IEV] = TC3589x_GPIOIEV0,
	154	[REG_IS] = TC3589x_GPIOIS0,
	155	[REG_IE] = TC3589x_GPIOIE0,
d88b25be RV	156	};
	157	int i, j;
	158
	159	for (i = 0; i < CACHE_NR_REGS; i++) {
	160	for (j = 0; j < CACHE_NR_BANKS; j++) {
20406ebf SI	161	u8 old = tc3589x_gpio->oldregs[i][j];
20406ebf SI	162	u8 new = tc3589x_gpio->regs[i][j];
d88b25be RV	163
	164	if (new == old)
	165	continue;
	166
20406ebf SI	167	tc3589x_gpio->oldregs[i][j] = new;
20406ebf SI	168	tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
d88b25be RV	169	}
	170	}
	171
20406ebf	172	mutex_unlock(&tc3589x_gpio->irq_lock);
d88b25be RV	173	}
d88b25be RV	174
33fcc1b8	175	static void tc3589x_gpio_irq_mask(struct irq_data *d)
d88b25be	176	{
33fcc1b8 LB	177	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
33fcc1b8 LB	178	int offset = d->irq - tc3589x_gpio->irq_base;
d88b25be RV	179	int regoffset = offset / 8;
	180	int mask = 1 << (offset % 8);
	181
20406ebf	182	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
d88b25be RV	183	}
d88b25be RV	184
33fcc1b8	185	static void tc3589x_gpio_irq_unmask(struct irq_data *d)
d88b25be	186	{
33fcc1b8 LB	187	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
33fcc1b8 LB	188	int offset = d->irq - tc3589x_gpio->irq_base;
d88b25be RV	189	int regoffset = offset / 8;
	190	int mask = 1 << (offset % 8);
	191
20406ebf	192	tc3589x_gpio->regs[REG_IE][regoffset] \|= mask;
d88b25be RV	193	}
d88b25be RV	194
20406ebf SI	195	static struct irq_chip tc3589x_gpio_irq_chip = {
20406ebf SI	196	.name = "tc3589x-gpio",
33fcc1b8 LB	197	.irq_bus_lock = tc3589x_gpio_irq_lock,
	198	.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
	199	.irq_mask = tc3589x_gpio_irq_mask,
	200	.irq_unmask = tc3589x_gpio_irq_unmask,
	201	.irq_set_type = tc3589x_gpio_irq_set_type,
d88b25be RV	202	};
d88b25be RV	203
20406ebf	204	static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
d88b25be	205	{
20406ebf SI	206	struct tc3589x_gpio *tc3589x_gpio = dev;
20406ebf SI	207	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be RV	208	u8 status[CACHE_NR_BANKS];
	209	int ret;
	210	int i;
	211
20406ebf	212	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
d88b25be RV	213	ARRAY_SIZE(status), status);
	214	if (ret < 0)
	215	return IRQ_NONE;
	216
	217	for (i = 0; i < ARRAY_SIZE(status); i++) {
	218	unsigned int stat = status[i];
	219	if (!stat)
	220	continue;
	221
	222	while (stat) {
	223	int bit = __ffs(stat);
	224	int line = i * 8 + bit;
	225
20406ebf	226	handle_nested_irq(tc3589x_gpio->irq_base + line);
d88b25be RV	227	stat &= ~(1 << bit);
	228	}
	229
20406ebf	230	tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
d88b25be RV	231	}
	232
	233	return IRQ_HANDLED;
	234	}
	235
20406ebf	236	static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio)
d88b25be	237	{
20406ebf	238	int base = tc3589x_gpio->irq_base;
d88b25be RV	239	int irq;
d88b25be RV	240
20406ebf	241	for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
b51804bc TG	242	irq_set_chip_data(irq, tc3589x_gpio);
b51804bc TG	243	irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
d88b25be	244	handle_simple_irq);
b51804bc	245	irq_set_nested_thread(irq, 1);
d88b25be RV	246	#ifdef CONFIG_ARM
	247	set_irq_flags(irq, IRQF_VALID);
	248	#else
b51804bc	249	irq_set_noprobe(irq);
d88b25be RV	250	#endif
	251	}
	252
	253	return 0;
	254	}
	255
20406ebf	256	static void tc3589x_gpio_irq_remove(struct tc3589x_gpio *tc3589x_gpio)
d88b25be	257	{
20406ebf	258	int base = tc3589x_gpio->irq_base;
d88b25be RV	259	int irq;
d88b25be RV	260
20406ebf	261	for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
d88b25be RV	262	#ifdef CONFIG_ARM
	263	set_irq_flags(irq, 0);
	264	#endif
b51804bc TG	265	irq_set_chip_and_handler(irq, NULL, NULL);
b51804bc TG	266	irq_set_chip_data(irq, NULL);
d88b25be RV	267	}
	268	}
	269
20406ebf	270	static int __devinit tc3589x_gpio_probe(struct platform_device *pdev)
d88b25be	271	{
20406ebf SI	272	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	273	struct tc3589x_gpio_platform_data *pdata;
	274	struct tc3589x_gpio *tc3589x_gpio;
d88b25be RV	275	int ret;
	276	int irq;
	277
20406ebf	278	pdata = tc3589x->pdata->gpio;
d88b25be RV	279	if (!pdata)
	280	return -ENODEV;
	281
	282	irq = platform_get_irq(pdev, 0);
	283	if (irq < 0)
	284	return irq;
	285
20406ebf SI	286	tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
20406ebf SI	287	if (!tc3589x_gpio)
d88b25be RV	288	return -ENOMEM;
d88b25be RV	289
20406ebf	290	mutex_init(&tc3589x_gpio->irq_lock);
d88b25be	291
20406ebf SI	292	tc3589x_gpio->dev = &pdev->dev;
20406ebf SI	293	tc3589x_gpio->tc3589x = tc3589x;
d88b25be	294
20406ebf SI	295	tc3589x_gpio->chip = template_chip;
	296	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	297	tc3589x_gpio->chip.dev = &pdev->dev;
	298	tc3589x_gpio->chip.base = pdata->gpio_base;
d88b25be	299
20406ebf	300	tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0);
d88b25be RV	301
d88b25be RV	302	/* Bring the GPIO module out of reset */
20406ebf SI	303	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
20406ebf SI	304	TC3589x_RSTCTRL_GPIRST, 0);
d88b25be RV	305	if (ret < 0)
	306	goto out_free;
	307
20406ebf	308	ret = tc3589x_gpio_irq_init(tc3589x_gpio);
d88b25be RV	309	if (ret)
	310	goto out_free;
	311
20406ebf SI	312	ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
20406ebf SI	313	"tc3589x-gpio", tc3589x_gpio);
d88b25be RV	314	if (ret) {
	315	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
	316	goto out_removeirq;
	317	}
	318
20406ebf	319	ret = gpiochip_add(&tc3589x_gpio->chip);
d88b25be RV	320	if (ret) {
	321	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	322	goto out_freeirq;
	323	}
	324
f0a7a98d	325	if (pdata->setup)
20406ebf	326	pdata->setup(tc3589x, tc3589x_gpio->chip.base);
f0a7a98d	327
20406ebf	328	platform_set_drvdata(pdev, tc3589x_gpio);
d88b25be RV	329
	330	return 0;
	331
	332	out_freeirq:
20406ebf	333	free_irq(irq, tc3589x_gpio);
d88b25be	334	out_removeirq:
20406ebf	335	tc3589x_gpio_irq_remove(tc3589x_gpio);
d88b25be	336	out_free:
20406ebf	337	kfree(tc3589x_gpio);
d88b25be RV	338	return ret;
	339	}
	340
20406ebf	341	static int __devexit tc3589x_gpio_remove(struct platform_device *pdev)
d88b25be	342	{
20406ebf SI	343	struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
	344	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	345	struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
d88b25be RV	346	int irq = platform_get_irq(pdev, 0);
	347	int ret;
	348
f0a7a98d	349	if (pdata->remove)
20406ebf	350	pdata->remove(tc3589x, tc3589x_gpio->chip.base);
f0a7a98d	351
20406ebf	352	ret = gpiochip_remove(&tc3589x_gpio->chip);
d88b25be	353	if (ret < 0) {
20406ebf	354	dev_err(tc3589x_gpio->dev,
d88b25be RV	355	"unable to remove gpiochip: %d\n", ret);
	356	return ret;
	357	}
	358
20406ebf SI	359	free_irq(irq, tc3589x_gpio);
20406ebf SI	360	tc3589x_gpio_irq_remove(tc3589x_gpio);
d88b25be RV	361
d88b25be RV	362	platform_set_drvdata(pdev, NULL);
20406ebf	363	kfree(tc3589x_gpio);
d88b25be RV	364
	365	return 0;
	366	}
	367
20406ebf SI	368	static struct platform_driver tc3589x_gpio_driver = {
20406ebf SI	369	.driver.name = "tc3589x-gpio",
d88b25be	370	.driver.owner = THIS_MODULE,
20406ebf SI	371	.probe = tc3589x_gpio_probe,
20406ebf SI	372	.remove = __devexit_p(tc3589x_gpio_remove),
d88b25be RV	373	};
d88b25be RV	374
20406ebf	375	static int __init tc3589x_gpio_init(void)
d88b25be	376	{
20406ebf	377	return platform_driver_register(&tc3589x_gpio_driver);
d88b25be	378	}
20406ebf	379	subsys_initcall(tc3589x_gpio_init);
d88b25be	380
20406ebf	381	static void __exit tc3589x_gpio_exit(void)
d88b25be	382	{
20406ebf	383	platform_driver_unregister(&tc3589x_gpio_driver);
d88b25be	384	}
20406ebf	385	module_exit(tc3589x_gpio_exit);
d88b25be RV	386
d88b25be RV	387	MODULE_LICENSE("GPL v2");
20406ebf	388	MODULE_DESCRIPTION("TC3589x GPIO driver");
d88b25be	389	MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");