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ASoC: wm_adsp: Only write shutdown controls for active firmwares
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
2159ad93
MB		 35#include "wm_adsp.h"
36
37#define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45#define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47
48#define ADSP1_CONTROL_1 0x00
49#define ADSP1_CONTROL_2 0x02
50#define ADSP1_CONTROL_3 0x03
51#define ADSP1_CONTROL_4 0x04
52#define ADSP1_CONTROL_5 0x06
53#define ADSP1_CONTROL_6 0x07
54#define ADSP1_CONTROL_7 0x08
55#define ADSP1_CONTROL_8 0x09
56#define ADSP1_CONTROL_9 0x0A
57#define ADSP1_CONTROL_10 0x0B
58#define ADSP1_CONTROL_11 0x0C
59#define ADSP1_CONTROL_12 0x0D
60#define ADSP1_CONTROL_13 0x0F
61#define ADSP1_CONTROL_14 0x10
62#define ADSP1_CONTROL_15 0x11
63#define ADSP1_CONTROL_16 0x12
64#define ADSP1_CONTROL_17 0x13
65#define ADSP1_CONTROL_18 0x14
66#define ADSP1_CONTROL_19 0x16
67#define ADSP1_CONTROL_20 0x17
68#define ADSP1_CONTROL_21 0x18
69#define ADSP1_CONTROL_22 0x1A
70#define ADSP1_CONTROL_23 0x1B
71#define ADSP1_CONTROL_24 0x1C
72#define ADSP1_CONTROL_25 0x1E
73#define ADSP1_CONTROL_26 0x20
74#define ADSP1_CONTROL_27 0x21
75#define ADSP1_CONTROL_28 0x22
76#define ADSP1_CONTROL_29 0x23
77#define ADSP1_CONTROL_30 0x24
78#define ADSP1_CONTROL_31 0x26
79
80/*
81 * ADSP1 Control 19
82 */
83#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86
87
88/*
89 * ADSP1 Control 30
90 */
91#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103#define ADSP1_START 0x0001 /* DSP1_START */
104#define ADSP1_START_MASK 0x0001 /* DSP1_START */
105#define ADSP1_START_SHIFT 0 /* DSP1_START */
106#define ADSP1_START_WIDTH 1 /* DSP1_START */
107
94e205bf
CR		 108/*
109 * ADSP1 Control 31
110 */
111#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
114
2d30b575
MB		 115#define ADSP2_CONTROL 0x0
116#define ADSP2_CLOCKING 0x1
117#define ADSP2_STATUS1 0x4
118#define ADSP2_WDMA_CONFIG_1 0x30
119#define ADSP2_WDMA_CONFIG_2 0x31
120#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 121
10337b07
RF		 122#define ADSP2_SCRATCH0 0x40
123#define ADSP2_SCRATCH1 0x41
124#define ADSP2_SCRATCH2 0x42
125#define ADSP2_SCRATCH3 0x43
126
2159ad93
MB		 127/*
128 * ADSP2 Control
129 */
130
131#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
132#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
133#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
134#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
135#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
136#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
137#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
138#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
139#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
140#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
141#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
142#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
143#define ADSP2_START 0x0001 /* DSP1_START */
144#define ADSP2_START_MASK 0x0001 /* DSP1_START */
145#define ADSP2_START_SHIFT 0 /* DSP1_START */
146#define ADSP2_START_WIDTH 1 /* DSP1_START */
147
973838a0
MB		 148/*
149 * ADSP2 clocking
150 */
151#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
152#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
153#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
154
2159ad93
MB		 155/*
156 * ADSP2 Status 1
157 */
158#define ADSP2_RAM_RDY 0x0001
159#define ADSP2_RAM_RDY_MASK 0x0001
160#define ADSP2_RAM_RDY_SHIFT 0
161#define ADSP2_RAM_RDY_WIDTH 1
162
9ee78757
CK		 163#define ADSP_MAX_STD_CTRL_SIZE 512
164
f4f0c4c6
RF		 165#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
166#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
a23ebba8
RF		 167#define WM_ADSP_ACKED_CTL_MIN_VALUE 0
168#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
f4f0c4c6
RF		 169
170/*
171 * Event control messages
172 */
173#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
174
cf17c83c
MB		 175struct wm_adsp_buf {
176 struct list_head list;
177 void *buf;
178};
179
180static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
181 struct list_head *list)
182{
183 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
184
185 if (buf == NULL)
186 return NULL;
187
cdcd7f72 188 buf->buf = vmalloc(len);
cf17c83c 189 if (!buf->buf) {
cdcd7f72 190 vfree(buf);
cf17c83c
MB		 191 return NULL;
192 }
cdcd7f72 193 memcpy(buf->buf, src, len);
cf17c83c
MB		 194
195 if (list)
196 list_add_tail(&buf->list, list);
197
198 return buf;
199}
200
201static void wm_adsp_buf_free(struct list_head *list)
202{
203 while (!list_empty(list)) {
204 struct wm_adsp_buf *buf = list_first_entry(list,
205 struct wm_adsp_buf,
206 list);
207 list_del(&buf->list);
cdcd7f72 208 vfree(buf->buf);
cf17c83c
MB		 209 kfree(buf);
210 }
211}
212
04d1300f
CK		 213#define WM_ADSP_FW_MBC_VSS 0
214#define WM_ADSP_FW_HIFI 1
215#define WM_ADSP_FW_TX 2
216#define WM_ADSP_FW_TX_SPK 3
217#define WM_ADSP_FW_RX 4
218#define WM_ADSP_FW_RX_ANC 5
219#define WM_ADSP_FW_CTRL 6
220#define WM_ADSP_FW_ASR 7
221#define WM_ADSP_FW_TRACE 8
222#define WM_ADSP_FW_SPK_PROT 9
223#define WM_ADSP_FW_MISC 10
224
225#define WM_ADSP_NUM_FW 11
dd84f925 226
1023dbd9 227static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 228 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
229 [WM_ADSP_FW_HIFI] = "MasterHiFi",
230 [WM_ADSP_FW_TX] = "Tx",
231 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
232 [WM_ADSP_FW_RX] = "Rx",
233 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
234 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
235 [WM_ADSP_FW_ASR] = "ASR Assist",
236 [WM_ADSP_FW_TRACE] = "Dbg Trace",
237 [WM_ADSP_FW_SPK_PROT] = "Protection",
238 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 239};
240
2cd19bdb
CK		 241struct wm_adsp_system_config_xm_hdr {
242 __be32 sys_enable;
243 __be32 fw_id;
244 __be32 fw_rev;
245 __be32 boot_status;
246 __be32 watchdog;
247 __be32 dma_buffer_size;
248 __be32 rdma[6];
249 __be32 wdma[8];
250 __be32 build_job_name[3];
251 __be32 build_job_number;
252};
253
254struct wm_adsp_alg_xm_struct {
255 __be32 magic;
256 __be32 smoothing;
257 __be32 threshold;
258 __be32 host_buf_ptr;
259 __be32 start_seq;
260 __be32 high_water_mark;
261 __be32 low_water_mark;
262 __be64 smoothed_power;
263};
264
265struct wm_adsp_buffer {
266 __be32 X_buf_base; /* XM base addr of first X area */
267 __be32 X_buf_size; /* Size of 1st X area in words */
268 __be32 X_buf_base2; /* XM base addr of 2nd X area */
269 __be32 X_buf_brk; /* Total X size in words */
270 __be32 Y_buf_base; /* YM base addr of Y area */
271 __be32 wrap; /* Total size X and Y in words */
272 __be32 high_water_mark; /* Point at which IRQ is asserted */
273 __be32 irq_count; /* bits 1-31 count IRQ assertions */
274 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
275 __be32 next_write_index; /* word index of next write */
276 __be32 next_read_index; /* word index of next read */
277 __be32 error; /* error if any */
278 __be32 oldest_block_index; /* word index of oldest surviving */
279 __be32 requested_rewind; /* how many blocks rewind was done */
280 __be32 reserved_space; /* internal */
281 __be32 min_free; /* min free space since stream start */
282 __be32 blocks_written[2]; /* total blocks written (64 bit) */
283 __be32 words_written[2]; /* total words written (64 bit) */
284};
285
721be3be
CK		 286struct wm_adsp_compr;
287
2cd19bdb
CK		 288struct wm_adsp_compr_buf {
289 struct wm_adsp *dsp;
721be3be 290 struct wm_adsp_compr *compr;
2cd19bdb
CK		 291
292 struct wm_adsp_buffer_region *regions;
293 u32 host_buf_ptr;
565ace46
CK		 294
295 u32 error;
296 u32 irq_count;
297 int read_index;
298 int avail;
2cd19bdb
CK		 299};
300
406abc95
CK		 301struct wm_adsp_compr {
302 struct wm_adsp *dsp;
95fe9597 303 struct wm_adsp_compr_buf *buf;
406abc95
CK		 304
305 struct snd_compr_stream *stream;
306 struct snd_compressed_buffer size;
565ace46 307
83a40ce9 308 u32 *raw_buf;
565ace46 309 unsigned int copied_total;
da2b3358
CK		 310
311 unsigned int sample_rate;
406abc95
CK		 312};
313
314#define WM_ADSP_DATA_WORD_SIZE 3
315
316#define WM_ADSP_MIN_FRAGMENTS 1
317#define WM_ADSP_MAX_FRAGMENTS 256
318#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
319#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
320
2cd19bdb
CK		 321#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
322
323#define HOST_BUFFER_FIELD(field) \
324 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
325
326#define ALG_XM_FIELD(field) \
327 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
328
329static int wm_adsp_buffer_init(struct wm_adsp *dsp);
330static int wm_adsp_buffer_free(struct wm_adsp *dsp);
331
332struct wm_adsp_buffer_region {
333 unsigned int offset;
334 unsigned int cumulative_size;
335 unsigned int mem_type;
336 unsigned int base_addr;
337};
338
339struct wm_adsp_buffer_region_def {
340 unsigned int mem_type;
341 unsigned int base_offset;
342 unsigned int size_offset;
343};
344
3a9686c4 345static const struct wm_adsp_buffer_region_def default_regions[] = {
2cd19bdb
CK		 346 {
347 .mem_type = WMFW_ADSP2_XM,
348 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
349 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
350 },
351 {
352 .mem_type = WMFW_ADSP2_XM,
353 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
354 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
355 },
356 {
357 .mem_type = WMFW_ADSP2_YM,
358 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
359 .size_offset = HOST_BUFFER_FIELD(wrap),
360 },
361};
362
406abc95
CK		 363struct wm_adsp_fw_caps {
364 u32 id;
365 struct snd_codec_desc desc;
2cd19bdb 366 int num_regions;
3a9686c4 367 const struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 368};
369
e6d00f34 370static const struct wm_adsp_fw_caps ctrl_caps[] = {
406abc95
CK		 371 {
372 .id = SND_AUDIOCODEC_BESPOKE,
373 .desc = {
374 .max_ch = 1,
375 .sample_rates = { 16000 },
376 .num_sample_rates = 1,
377 .formats = SNDRV_PCM_FMTBIT_S16_LE,
378 },
e6d00f34
CK		 379 .num_regions = ARRAY_SIZE(default_regions),
380 .region_defs = default_regions,
406abc95
CK		 381 },
382};
383
7ce4283c
CK		 384static const struct wm_adsp_fw_caps trace_caps[] = {
385 {
386 .id = SND_AUDIOCODEC_BESPOKE,
387 .desc = {
388 .max_ch = 8,
389 .sample_rates = {
390 4000, 8000, 11025, 12000, 16000, 22050,
391 24000, 32000, 44100, 48000, 64000, 88200,
392 96000, 176400, 192000
393 },
394 .num_sample_rates = 15,
395 .formats = SNDRV_PCM_FMTBIT_S16_LE,
396 },
397 .num_regions = ARRAY_SIZE(default_regions),
398 .region_defs = default_regions,
406abc95
CK		 399 },
400};
401
402static const struct {
1023dbd9 403 const char *file;
406abc95
CK		 404 int compr_direction;
405 int num_caps;
406 const struct wm_adsp_fw_caps *caps;
20b7f7c5 407 bool voice_trigger;
1023dbd9 408} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 409 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
410 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
411 [WM_ADSP_FW_TX] = { .file = "tx" },
412 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
413 [WM_ADSP_FW_RX] = { .file = "rx" },
414 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 415 [WM_ADSP_FW_CTRL] = {
416 .file = "ctrl",
417 .compr_direction = SND_COMPRESS_CAPTURE,
e6d00f34
CK		 418 .num_caps = ARRAY_SIZE(ctrl_caps),
419 .caps = ctrl_caps,
20b7f7c5 420 .voice_trigger = true,
406abc95 421 },
04d1300f 422 [WM_ADSP_FW_ASR] = { .file = "asr" },
7ce4283c
CK		 423 [WM_ADSP_FW_TRACE] = {
424 .file = "trace",
425 .compr_direction = SND_COMPRESS_CAPTURE,
426 .num_caps = ARRAY_SIZE(trace_caps),
427 .caps = trace_caps,
428 },
04d1300f
CK		 429 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
430 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 431};
432
6ab2b7b4
DP		 433struct wm_coeff_ctl_ops {
434 int (*xget)(struct snd_kcontrol *kcontrol,
435 struct snd_ctl_elem_value *ucontrol);
436 int (*xput)(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_value *ucontrol);
438 int (*xinfo)(struct snd_kcontrol *kcontrol,
439 struct snd_ctl_elem_info *uinfo);
440};
441
6ab2b7b4
DP		 442struct wm_coeff_ctl {
443 const char *name;
2323736d 444 const char *fw_name;
3809f001 445 struct wm_adsp_alg_region alg_region;
6ab2b7b4 446 struct wm_coeff_ctl_ops ops;
3809f001 447 struct wm_adsp *dsp;
6ab2b7b4
DP		 448 unsigned int enabled:1;
449 struct list_head list;
450 void *cache;
2323736d 451 unsigned int offset;
6ab2b7b4 452 size_t len;
0c2e3f34 453 unsigned int set:1;
6ab2b7b4 454 struct snd_kcontrol *kcontrol;
9ee78757 455 struct soc_bytes_ext bytes_ext;
26c22a19 456 unsigned int flags;
8eb084d0 457 unsigned int type;
6ab2b7b4
DP		 458};
459
9ce5e6e6
RF		 460static const char *wm_adsp_mem_region_name(unsigned int type)
461{
462 switch (type) {
463 case WMFW_ADSP1_PM:
464 return "PM";
465 case WMFW_ADSP1_DM:
466 return "DM";
467 case WMFW_ADSP2_XM:
468 return "XM";
469 case WMFW_ADSP2_YM:
470 return "YM";
471 case WMFW_ADSP1_ZM:
472 return "ZM";
473 default:
474 return NULL;
475 }
476}
477
f9f55e31
RF		 478#ifdef CONFIG_DEBUG_FS
479static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
480{
481 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
482
f9f55e31
RF		 483 kfree(dsp->wmfw_file_name);
484 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 485}
486
487static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
488{
489 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
490
f9f55e31
RF		 491 kfree(dsp->bin_file_name);
492 dsp->bin_file_name = tmp;
f9f55e31
RF		 493}
494
495static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
496{
f9f55e31
RF		 497 kfree(dsp->wmfw_file_name);
498 kfree(dsp->bin_file_name);
499 dsp->wmfw_file_name = NULL;
500 dsp->bin_file_name = NULL;
f9f55e31
RF		 501}
502
503static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
504 char __user *user_buf,
505 size_t count, loff_t *ppos)
506{
507 struct wm_adsp *dsp = file->private_data;
508 ssize_t ret;
509
078e7183 510 mutex_lock(&dsp->pwr_lock);
f9f55e31 511
28823eba 512 if (!dsp->wmfw_file_name || !dsp->booted)
f9f55e31
RF		 513 ret = 0;
514 else
515 ret = simple_read_from_buffer(user_buf, count, ppos,
516 dsp->wmfw_file_name,
517 strlen(dsp->wmfw_file_name));
518
078e7183 519 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 520 return ret;
521}
522
523static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
524 char __user *user_buf,
525 size_t count, loff_t *ppos)
526{
527 struct wm_adsp *dsp = file->private_data;
528 ssize_t ret;
529
078e7183 530 mutex_lock(&dsp->pwr_lock);
f9f55e31 531
28823eba 532 if (!dsp->bin_file_name || !dsp->booted)
f9f55e31
RF		 533 ret = 0;
534 else
535 ret = simple_read_from_buffer(user_buf, count, ppos,
536 dsp->bin_file_name,
537 strlen(dsp->bin_file_name));
538
078e7183 539 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 540 return ret;
541}
542
543static const struct {
544 const char *name;
545 const struct file_operations fops;
546} wm_adsp_debugfs_fops[] = {
547 {
548 .name = "wmfw_file_name",
549 .fops = {
550 .open = simple_open,
551 .read = wm_adsp_debugfs_wmfw_read,
552 },
553 },
554 {
555 .name = "bin_file_name",
556 .fops = {
557 .open = simple_open,
558 .read = wm_adsp_debugfs_bin_read,
559 },
560 },
561};
562
563static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
564 struct snd_soc_codec *codec)
565{
566 struct dentry *root = NULL;
567 char *root_name;
568 int i;
569
570 if (!codec->component.debugfs_root) {
571 adsp_err(dsp, "No codec debugfs root\n");
572 goto err;
573 }
574
575 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
576 if (!root_name)
577 goto err;
578
579 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
580 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
581 kfree(root_name);
582
583 if (!root)
584 goto err;
585
28823eba
CK		 586 if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted))
587 goto err;
588
f9f55e31
RF		 589 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
590 goto err;
591
592 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
593 goto err;
594
595 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
596 &dsp->fw_id_version))
597 goto err;
598
599 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
600 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
601 S_IRUGO, root, dsp,
602 &wm_adsp_debugfs_fops[i].fops))
603 goto err;
604 }
605
606 dsp->debugfs_root = root;
607 return;
608
609err:
610 debugfs_remove_recursive(root);
611 adsp_err(dsp, "Failed to create debugfs\n");
612}
613
614static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
615{
616 wm_adsp_debugfs_clear(dsp);
617 debugfs_remove_recursive(dsp->debugfs_root);
618}
619#else
620static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
621 struct snd_soc_codec *codec)
622{
623}
624
625static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
626{
627}
628
629static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
630 const char *s)
631{
632}
633
634static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
635 const char *s)
636{
637}
638
639static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
640{
641}
642#endif
643
1023dbd9
MB		 644static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
645 struct snd_ctl_elem_value *ucontrol)
646{
ea53bf77 647 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 648 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 649 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 650
15c66570 651 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 652
653 return 0;
654}
655
656static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
657 struct snd_ctl_elem_value *ucontrol)
658{
ea53bf77 659 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 660 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 661 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 662 int ret = 0;
1023dbd9 663
15c66570 664 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 665 return 0;
666
15c66570 667 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
1023dbd9
MB		 668 return -EINVAL;
669
d27c5e15
CK		 670 mutex_lock(&dsp[e->shift_l].pwr_lock);
671
28823eba 672 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
d27c5e15
CK		 673 ret = -EBUSY;
674 else
15c66570 675 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
1023dbd9 676
d27c5e15 677 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 678
d27c5e15 679 return ret;
1023dbd9
MB		 680}
681
682static const struct soc_enum wm_adsp_fw_enum[] = {
683 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
684 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
685 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
686 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
687};
688
336d0442 689const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 690 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
691 wm_adsp_fw_get, wm_adsp_fw_put),
692 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
693 wm_adsp_fw_get, wm_adsp_fw_put),
694 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
695 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 696 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
697 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 698};
336d0442 699EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 700
701static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
702 int type)
703{
704 int i;
705
706 for (i = 0; i < dsp->num_mems; i++)
707 if (dsp->mem[i].type == type)
708 return &dsp->mem[i];
709
710 return NULL;
711}
712
3809f001 713static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 714 unsigned int offset)
715{
3809f001 716 if (WARN_ON(!mem))
6c452bda 717 return offset;
3809f001 718 switch (mem->type) {
45b9ee72 719 case WMFW_ADSP1_PM:
3809f001 720 return mem->base + (offset * 3);
45b9ee72 721 case WMFW_ADSP1_DM:
3809f001 722 return mem->base + (offset * 2);
45b9ee72 723 case WMFW_ADSP2_XM:
3809f001 724 return mem->base + (offset * 2);
45b9ee72 725 case WMFW_ADSP2_YM:
3809f001 726 return mem->base + (offset * 2);
45b9ee72 727 case WMFW_ADSP1_ZM:
3809f001 728 return mem->base + (offset * 2);
45b9ee72 729 default:
6c452bda 730 WARN(1, "Unknown memory region type");
45b9ee72
MB		 731 return offset;
732 }
733}
734
10337b07
RF		 735static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
736{
737 u16 scratch[4];
738 int ret;
739
740 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
741 scratch, sizeof(scratch));
742 if (ret) {
743 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
744 return;
745 }
746
747 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
748 be16_to_cpu(scratch[0]),
749 be16_to_cpu(scratch[1]),
750 be16_to_cpu(scratch[2]),
751 be16_to_cpu(scratch[3]));
752}
753
9ee78757
CK		 754static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
755{
756 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
757}
758
b396ebca
RF		 759static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
760{
761 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
762 struct wm_adsp *dsp = ctl->dsp;
763 const struct wm_adsp_region *mem;
764
765 mem = wm_adsp_find_region(dsp, alg_region->type);
766 if (!mem) {
767 adsp_err(dsp, "No base for region %x\n",
768 alg_region->type);
769 return -EINVAL;
770 }
771
772 *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
773
774 return 0;
775}
776
7585a5b0 777static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 778 struct snd_ctl_elem_info *uinfo)
779{
9ee78757
CK		 780 struct soc_bytes_ext *bytes_ext =
781 (struct soc_bytes_ext *)kctl->private_value;
782 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 783
a23ebba8
RF		 784 switch (ctl->type) {
785 case WMFW_CTL_TYPE_ACKED:
786 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
787 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
788 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
789 uinfo->value.integer.step = 1;
790 uinfo->count = 1;
791 break;
792 default:
793 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
794 uinfo->count = ctl->len;
795 break;
796 }
797
6ab2b7b4
DP		 798 return 0;
799}
800
f4f0c4c6
RF		 801static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
802 unsigned int event_id)
803{
804 struct wm_adsp *dsp = ctl->dsp;
805 u32 val = cpu_to_be32(event_id);
806 unsigned int reg;
807 int i, ret;
808
809 ret = wm_coeff_base_reg(ctl, &reg);
810 if (ret)
811 return ret;
812
813 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
814 event_id, ctl->alg_region.alg,
815 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
816
817 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
818 if (ret) {
819 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
820 return ret;
821 }
822
823 /*
824 * Poll for ack, we initially poll at ~1ms intervals for firmwares
825 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
826 * to ack instantly so we do the first 1ms delay before reading the
827 * control to avoid a pointless bus transaction
828 */
829 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
830 switch (i) {
831 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
832 usleep_range(1000, 2000);
833 i++;
834 break;
835 default:
836 usleep_range(10000, 20000);
837 i += 10;
838 break;
839 }
840
841 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
842 if (ret) {
843 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
844 return ret;
845 }
846
847 if (val == 0) {
848 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
849 return 0;
850 }
851 }
852
853 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
854 reg, ctl->alg_region.alg,
855 wm_adsp_mem_region_name(ctl->alg_region.type),
856 ctl->offset);
857
858 return -ETIMEDOUT;
859}
860
c9f8dd71 861static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 862 const void *buf, size_t len)
863{
3809f001 864 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 865 void *scratch;
866 int ret;
867 unsigned int reg;
868
b396ebca
RF		 869 ret = wm_coeff_base_reg(ctl, &reg);
870 if (ret)
871 return ret;
6ab2b7b4 872
4f8ea6d7 873 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 874 if (!scratch)
875 return -ENOMEM;
876
3809f001 877 ret = regmap_raw_write(dsp->regmap, reg, scratch,
4f8ea6d7 878 len);
6ab2b7b4 879 if (ret) {
3809f001 880 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
4f8ea6d7 881 len, reg, ret);
6ab2b7b4
DP		 882 kfree(scratch);
883 return ret;
884 }
4f8ea6d7 885 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
6ab2b7b4
DP		 886
887 kfree(scratch);
888
889 return 0;
890}
891
7585a5b0 892static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 893 struct snd_ctl_elem_value *ucontrol)
894{
9ee78757
CK		 895 struct soc_bytes_ext *bytes_ext =
896 (struct soc_bytes_ext *)kctl->private_value;
897 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 898 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 899 int ret = 0;
900
901 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 902
903 memcpy(ctl->cache, p, ctl->len);
904
65d17a9c 905 ctl->set = 1;
cef45771 906 if (ctl->enabled && ctl->dsp->running)
168d10e7 907 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 908
168d10e7
CK		 909 mutex_unlock(&ctl->dsp->pwr_lock);
910
911 return ret;
6ab2b7b4
DP		 912}
913
9ee78757
CK		 914static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
915 const unsigned int __user *bytes, unsigned int size)
916{
917 struct soc_bytes_ext *bytes_ext =
918 (struct soc_bytes_ext *)kctl->private_value;
919 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
920 int ret = 0;
921
922 mutex_lock(&ctl->dsp->pwr_lock);
923
924 if (copy_from_user(ctl->cache, bytes, size)) {
925 ret = -EFAULT;
926 } else {
927 ctl->set = 1;
cef45771 928 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 929 ret = wm_coeff_write_control(ctl, ctl->cache, size);
930 }
931
932 mutex_unlock(&ctl->dsp->pwr_lock);
933
934 return ret;
935}
936
a23ebba8
RF		 937static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
938 struct snd_ctl_elem_value *ucontrol)
939{
940 struct soc_bytes_ext *bytes_ext =
941 (struct soc_bytes_ext *)kctl->private_value;
942 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
943 unsigned int val = ucontrol->value.integer.value[0];
944 int ret;
945
946 if (val == 0)
947 return 0; /* 0 means no event */
948
949 mutex_lock(&ctl->dsp->pwr_lock);
950
951 if (ctl->enabled)
952 ret = wm_coeff_write_acked_control(ctl, val);
953 else
954 ret = -EPERM;
955
956 mutex_unlock(&ctl->dsp->pwr_lock);
957
958 return ret;
959}
960
c9f8dd71 961static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 962 void *buf, size_t len)
963{
3809f001 964 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 965 void *scratch;
966 int ret;
967 unsigned int reg;
968
b396ebca
RF		 969 ret = wm_coeff_base_reg(ctl, &reg);
970 if (ret)
971 return ret;
6ab2b7b4 972
4f8ea6d7 973 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 974 if (!scratch)
975 return -ENOMEM;
976
4f8ea6d7 977 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
6ab2b7b4 978 if (ret) {
3809f001 979 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
5602a643 980 len, reg, ret);
6ab2b7b4
DP		 981 kfree(scratch);
982 return ret;
983 }
4f8ea6d7 984 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
6ab2b7b4 985
4f8ea6d7 986 memcpy(buf, scratch, len);
6ab2b7b4
DP		 987 kfree(scratch);
988
989 return 0;
990}
991
7585a5b0 992static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 993 struct snd_ctl_elem_value *ucontrol)
994{
9ee78757
CK		 995 struct soc_bytes_ext *bytes_ext =
996 (struct soc_bytes_ext *)kctl->private_value;
997 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 998 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 999 int ret = 0;
1000
1001 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 1002
26c22a19 1003 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 1004 if (ctl->enabled && ctl->dsp->running)
168d10e7 1005 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 1006 else
168d10e7
CK		 1007 ret = -EPERM;
1008 } else {
cef45771 1009 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
bc1765d6
CK		 1010 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1011
168d10e7 1012 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 1013 }
1014
168d10e7 1015 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 1016
168d10e7 1017 return ret;
6ab2b7b4
DP		 1018}
1019
9ee78757
CK		 1020static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1021 unsigned int __user *bytes, unsigned int size)
1022{
1023 struct soc_bytes_ext *bytes_ext =
1024 (struct soc_bytes_ext *)kctl->private_value;
1025 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1026 int ret = 0;
1027
1028 mutex_lock(&ctl->dsp->pwr_lock);
1029
1030 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 1031 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 1032 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1033 else
1034 ret = -EPERM;
1035 } else {
cef45771 1036 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
9ee78757
CK		 1037 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1038 }
1039
1040 if (!ret && copy_to_user(bytes, ctl->cache, size))
1041 ret = -EFAULT;
1042
1043 mutex_unlock(&ctl->dsp->pwr_lock);
1044
1045 return ret;
1046}
1047
a23ebba8
RF		 1048static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1049 struct snd_ctl_elem_value *ucontrol)
1050{
1051 /*
1052 * Although it's not useful to read an acked control, we must satisfy
1053 * user-side assumptions that all controls are readable and that a
1054 * write of the same value should be filtered out (it's valid to send
1055 * the same event number again to the firmware). We therefore return 0,
1056 * meaning "no event" so valid event numbers will always be a change
1057 */
1058 ucontrol->value.integer.value[0] = 0;
1059
1060 return 0;
1061}
1062
6ab2b7b4 1063struct wmfw_ctl_work {
3809f001 1064 struct wm_adsp *dsp;
6ab2b7b4
DP		 1065 struct wm_coeff_ctl *ctl;
1066 struct work_struct work;
1067};
1068
9ee78757
CK		 1069static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1070{
1071 unsigned int out, rd, wr, vol;
1072
1073 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1074 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1075 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1076 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1077
1078 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1079 } else {
1080 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1081 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1082 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1083
1084 out = 0;
1085 }
1086
1087 if (in) {
1088 if (in & WMFW_CTL_FLAG_READABLE)
1089 out |= rd;
1090 if (in & WMFW_CTL_FLAG_WRITEABLE)
1091 out |= wr;
1092 if (in & WMFW_CTL_FLAG_VOLATILE)
1093 out |= vol;
1094 } else {
1095 out |= rd | wr | vol;
1096 }
1097
1098 return out;
1099}
1100
3809f001 1101static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 1102{
1103 struct snd_kcontrol_new *kcontrol;
1104 int ret;
1105
92bb4c32 1106 if (!ctl || !ctl->name)
6ab2b7b4
DP		 1107 return -EINVAL;
1108
1109 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1110 if (!kcontrol)
1111 return -ENOMEM;
6ab2b7b4
DP		 1112
1113 kcontrol->name = ctl->name;
1114 kcontrol->info = wm_coeff_info;
9ee78757
CK		 1115 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1116 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1117 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
a23ebba8 1118 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
6ab2b7b4 1119
a23ebba8
RF		 1120 switch (ctl->type) {
1121 case WMFW_CTL_TYPE_ACKED:
1122 kcontrol->get = wm_coeff_get_acked;
1123 kcontrol->put = wm_coeff_put_acked;
1124 break;
1125 default:
1126 kcontrol->get = wm_coeff_get;
1127 kcontrol->put = wm_coeff_put;
9ee78757 1128
a23ebba8
RF		 1129 ctl->bytes_ext.max = ctl->len;
1130 ctl->bytes_ext.get = wm_coeff_tlv_get;
1131 ctl->bytes_ext.put = wm_coeff_tlv_put;
1132 break;
1133 }
26c22a19 1134
7d00cd97 1135 ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1);
6ab2b7b4
DP		 1136 if (ret < 0)
1137 goto err_kcontrol;
1138
1139 kfree(kcontrol);
1140
7d00cd97 1141 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name);
81ad93ec 1142
6ab2b7b4
DP		 1143 return 0;
1144
1145err_kcontrol:
1146 kfree(kcontrol);
1147 return ret;
1148}
1149
b21acc1c
CK		 1150static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1151{
1152 struct wm_coeff_ctl *ctl;
1153 int ret;
1154
1155 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1156 if (!ctl->enabled || ctl->set)
1157 continue;
26c22a19
CK		 1158 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1159 continue;
1160
7d00cd97 1161 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1162 if (ret < 0)
1163 return ret;
1164 }
1165
1166 return 0;
1167}
1168
1169static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1170{
1171 struct wm_coeff_ctl *ctl;
1172 int ret;
1173
1174 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1175 if (!ctl->enabled)
1176 continue;
26c22a19 1177 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
7d00cd97 1178 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1179 if (ret < 0)
1180 return ret;
1181 }
1182 }
1183
1184 return 0;
1185}
1186
f4f0c4c6
RF		 1187static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1188 unsigned int event)
1189{
1190 struct wm_coeff_ctl *ctl;
1191 int ret;
1192
1193 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1194 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1195 continue;
1196
87aa6374
CK		 1197 if (!ctl->enabled)
1198 continue;
1199
f4f0c4c6
RF		 1200 ret = wm_coeff_write_acked_control(ctl, event);
1201 if (ret)
1202 adsp_warn(dsp,
1203 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1204 event, ctl->alg_region.alg, ret);
1205 }
1206}
1207
b21acc1c
CK		 1208static void wm_adsp_ctl_work(struct work_struct *work)
1209{
1210 struct wmfw_ctl_work *ctl_work = container_of(work,
1211 struct wmfw_ctl_work,
1212 work);
1213
1214 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1215 kfree(ctl_work);
1216}
1217
66225e98
RF		 1218static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1219{
1220 kfree(ctl->cache);
1221 kfree(ctl->name);
1222 kfree(ctl);
1223}
1224
b21acc1c
CK		 1225static int wm_adsp_create_control(struct wm_adsp *dsp,
1226 const struct wm_adsp_alg_region *alg_region,
2323736d 1227 unsigned int offset, unsigned int len,
26c22a19 1228 const char *subname, unsigned int subname_len,
8eb084d0 1229 unsigned int flags, unsigned int type)
b21acc1c
CK		 1230{
1231 struct wm_coeff_ctl *ctl;
1232 struct wmfw_ctl_work *ctl_work;
1233 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
9ce5e6e6 1234 const char *region_name;
b21acc1c
CK		 1235 int ret;
1236
9ce5e6e6
RF		 1237 region_name = wm_adsp_mem_region_name(alg_region->type);
1238 if (!region_name) {
2323736d 1239 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 1240 return -EINVAL;
1241 }
1242
cb5b57a9
CK		 1243 switch (dsp->fw_ver) {
1244 case 0:
1245 case 1:
1246 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1247 dsp->num, region_name, alg_region->alg);
1248 break;
1249 default:
1250 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1251 "DSP%d%c %.12s %x", dsp->num, *region_name,
1252 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1253
1254 /* Truncate the subname from the start if it is too long */
1255 if (subname) {
1256 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1257 int skip = 0;
1258
1259 if (subname_len > avail)
1260 skip = subname_len - avail;
1261
1262 snprintf(name + ret,
1263 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1264 subname_len - skip, subname + skip);
1265 }
1266 break;
1267 }
b21acc1c 1268
7585a5b0 1269 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 1270 if (!strcmp(ctl->name, name)) {
1271 if (!ctl->enabled)
1272 ctl->enabled = 1;
1273 return 0;
1274 }
1275 }
1276
1277 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1278 if (!ctl)
1279 return -ENOMEM;
2323736d 1280 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 1281 ctl->alg_region = *alg_region;
1282 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1283 if (!ctl->name) {
1284 ret = -ENOMEM;
1285 goto err_ctl;
1286 }
1287 ctl->enabled = 1;
1288 ctl->set = 0;
1289 ctl->ops.xget = wm_coeff_get;
1290 ctl->ops.xput = wm_coeff_put;
1291 ctl->dsp = dsp;
1292
26c22a19 1293 ctl->flags = flags;
8eb084d0 1294 ctl->type = type;
2323736d 1295 ctl->offset = offset;
b21acc1c
CK		 1296 ctl->len = len;
1297 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1298 if (!ctl->cache) {
1299 ret = -ENOMEM;
1300 goto err_ctl_name;
1301 }
1302
2323736d
CK		 1303 list_add(&ctl->list, &dsp->ctl_list);
1304
8eb084d0
SH		 1305 if (flags & WMFW_CTL_FLAG_SYS)
1306 return 0;
1307
b21acc1c
CK		 1308 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1309 if (!ctl_work) {
1310 ret = -ENOMEM;
1311 goto err_ctl_cache;
1312 }
1313
1314 ctl_work->dsp = dsp;
1315 ctl_work->ctl = ctl;
1316 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1317 schedule_work(&ctl_work->work);
1318
1319 return 0;
1320
1321err_ctl_cache:
1322 kfree(ctl->cache);
1323err_ctl_name:
1324 kfree(ctl->name);
1325err_ctl:
1326 kfree(ctl);
1327
1328 return ret;
1329}
1330
2323736d
CK		 1331struct wm_coeff_parsed_alg {
1332 int id;
1333 const u8 *name;
1334 int name_len;
1335 int ncoeff;
1336};
1337
1338struct wm_coeff_parsed_coeff {
1339 int offset;
1340 int mem_type;
1341 const u8 *name;
1342 int name_len;
1343 int ctl_type;
1344 int flags;
1345 int len;
1346};
1347
cb5b57a9
CK		 1348static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1349{
1350 int length;
1351
1352 switch (bytes) {
1353 case 1:
1354 length = **pos;
1355 break;
1356 case 2:
8299ee81 1357 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1358 break;
1359 default:
1360 return 0;
1361 }
1362
1363 if (str)
1364 *str = *pos + bytes;
1365
1366 *pos += ((length + bytes) + 3) & ~0x03;
1367
1368 return length;
1369}
1370
1371static int wm_coeff_parse_int(int bytes, const u8 **pos)
1372{
1373 int val = 0;
1374
1375 switch (bytes) {
1376 case 2:
8299ee81 1377 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1378 break;
1379 case 4:
8299ee81 1380 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1381 break;
1382 default:
1383 break;
1384 }
1385
1386 *pos += bytes;
1387
1388 return val;
1389}
1390
2323736d
CK		 1391static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1392 struct wm_coeff_parsed_alg *blk)
1393{
1394 const struct wmfw_adsp_alg_data *raw;
1395
cb5b57a9
CK		 1396 switch (dsp->fw_ver) {
1397 case 0:
1398 case 1:
1399 raw = (const struct wmfw_adsp_alg_data *)*data;
1400 *data = raw->data;
2323736d 1401
cb5b57a9
CK		 1402 blk->id = le32_to_cpu(raw->id);
1403 blk->name = raw->name;
1404 blk->name_len = strlen(raw->name);
1405 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1406 break;
1407 default:
1408 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1409 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1410 &blk->name);
1411 wm_coeff_parse_string(sizeof(u16), data, NULL);
1412 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1413 break;
1414 }
2323736d
CK		 1415
1416 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1417 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1418 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1419}
1420
1421static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1422 struct wm_coeff_parsed_coeff *blk)
1423{
1424 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1425 const u8 *tmp;
1426 int length;
2323736d 1427
cb5b57a9
CK		 1428 switch (dsp->fw_ver) {
1429 case 0:
1430 case 1:
1431 raw = (const struct wmfw_adsp_coeff_data *)*data;
1432 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1433
1434 blk->offset = le16_to_cpu(raw->hdr.offset);
1435 blk->mem_type = le16_to_cpu(raw->hdr.type);
1436 blk->name = raw->name;
1437 blk->name_len = strlen(raw->name);
1438 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1439 blk->flags = le16_to_cpu(raw->flags);
1440 blk->len = le32_to_cpu(raw->len);
1441 break;
1442 default:
1443 tmp = *data;
1444 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1445 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1446 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1447 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1448 &blk->name);
1449 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1450 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1451 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1452 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1453 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1454
1455 *data = *data + sizeof(raw->hdr) + length;
1456 break;
1457 }
2323736d
CK		 1458
1459 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1460 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1461 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1462 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1463 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1464 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1465}
1466
f4f0c4c6
RF		 1467static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1468 const struct wm_coeff_parsed_coeff *coeff_blk,
1469 unsigned int f_required,
1470 unsigned int f_illegal)
1471{
1472 if ((coeff_blk->flags & f_illegal) ||
1473 ((coeff_blk->flags & f_required) != f_required)) {
1474 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1475 coeff_blk->flags, coeff_blk->ctl_type);
1476 return -EINVAL;
1477 }
1478
1479 return 0;
1480}
1481
2323736d
CK		 1482static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1483 const struct wmfw_region *region)
1484{
1485 struct wm_adsp_alg_region alg_region = {};
1486 struct wm_coeff_parsed_alg alg_blk;
1487 struct wm_coeff_parsed_coeff coeff_blk;
1488 const u8 *data = region->data;
1489 int i, ret;
1490
1491 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1492 for (i = 0; i < alg_blk.ncoeff; i++) {
1493 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1494
1495 switch (coeff_blk.ctl_type) {
1496 case SNDRV_CTL_ELEM_TYPE_BYTES:
1497 break;
a23ebba8
RF		 1498 case WMFW_CTL_TYPE_ACKED:
1499 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1500 continue; /* ignore */
1501
1502 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1503 WMFW_CTL_FLAG_VOLATILE |
1504 WMFW_CTL_FLAG_WRITEABLE |
1505 WMFW_CTL_FLAG_READABLE,
1506 0);
1507 if (ret)
1508 return -EINVAL;
1509 break;
f4f0c4c6
RF		 1510 case WMFW_CTL_TYPE_HOSTEVENT:
1511 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1512 WMFW_CTL_FLAG_SYS |
1513 WMFW_CTL_FLAG_VOLATILE |
1514 WMFW_CTL_FLAG_WRITEABLE |
1515 WMFW_CTL_FLAG_READABLE,
1516 0);
1517 if (ret)
1518 return -EINVAL;
1519 break;
2323736d
CK		 1520 default:
1521 adsp_err(dsp, "Unknown control type: %d\n",
1522 coeff_blk.ctl_type);
1523 return -EINVAL;
1524 }
1525
1526 alg_region.type = coeff_blk.mem_type;
1527 alg_region.alg = alg_blk.id;
1528
1529 ret = wm_adsp_create_control(dsp, &alg_region,
1530 coeff_blk.offset,
1531 coeff_blk.len,
1532 coeff_blk.name,
26c22a19 1533 coeff_blk.name_len,
8eb084d0
SH		 1534 coeff_blk.flags,
1535 coeff_blk.ctl_type);
2323736d
CK		 1536 if (ret < 0)
1537 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1538 coeff_blk.name_len, coeff_blk.name, ret);
1539 }
1540
1541 return 0;
1542}
1543
2159ad93
MB		 1544static int wm_adsp_load(struct wm_adsp *dsp)
1545{
cf17c83c 1546 LIST_HEAD(buf_list);
2159ad93
MB		 1547 const struct firmware *firmware;
1548 struct regmap *regmap = dsp->regmap;
1549 unsigned int pos = 0;
1550 const struct wmfw_header *header;
1551 const struct wmfw_adsp1_sizes *adsp1_sizes;
1552 const struct wmfw_adsp2_sizes *adsp2_sizes;
1553 const struct wmfw_footer *footer;
1554 const struct wmfw_region *region;
1555 const struct wm_adsp_region *mem;
1556 const char *region_name;
1557 char *file, *text;
cf17c83c 1558 struct wm_adsp_buf *buf;
2159ad93
MB		 1559 unsigned int reg;
1560 int regions = 0;
1561 int ret, offset, type, sizes;
1562
1563 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1564 if (file == NULL)
1565 return -ENOMEM;
1566
1023dbd9
MB		 1567 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1568 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1569 file[PAGE_SIZE - 1] = '\0';
1570
1571 ret = request_firmware(&firmware, file, dsp->dev);
1572 if (ret != 0) {
1573 adsp_err(dsp, "Failed to request '%s'\n", file);
1574 goto out;
1575 }
1576 ret = -EINVAL;
1577
1578 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1579 if (pos >= firmware->size) {
1580 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1581 file, firmware->size);
1582 goto out_fw;
1583 }
1584
7585a5b0 1585 header = (void *)&firmware->data[0];
2159ad93
MB		 1586
1587 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1588 adsp_err(dsp, "%s: invalid magic\n", file);
1589 goto out_fw;
1590 }
1591
2323736d
CK		 1592 switch (header->ver) {
1593 case 0:
c61e59fe
CK		 1594 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1595 file, header->ver);
1596 break;
2323736d 1597 case 1:
cb5b57a9 1598 case 2:
2323736d
CK		 1599 break;
1600 default:
2159ad93
MB		 1601 adsp_err(dsp, "%s: unknown file format %d\n",
1602 file, header->ver);
1603 goto out_fw;
1604 }
2323736d 1605
3626992a 1606 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1607 dsp->fw_ver = header->ver;
2159ad93
MB		 1608
1609 if (header->core != dsp->type) {
1610 adsp_err(dsp, "%s: invalid core %d != %d\n",
1611 file, header->core, dsp->type);
1612 goto out_fw;
1613 }
1614
1615 switch (dsp->type) {
1616 case WMFW_ADSP1:
1617 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1618 adsp1_sizes = (void *)&(header[1]);
1619 footer = (void *)&(adsp1_sizes[1]);
1620 sizes = sizeof(*adsp1_sizes);
1621
1622 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1623 file, le32_to_cpu(adsp1_sizes->dm),
1624 le32_to_cpu(adsp1_sizes->pm),
1625 le32_to_cpu(adsp1_sizes->zm));
1626 break;
1627
1628 case WMFW_ADSP2:
1629 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1630 adsp2_sizes = (void *)&(header[1]);
1631 footer = (void *)&(adsp2_sizes[1]);
1632 sizes = sizeof(*adsp2_sizes);
1633
1634 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1635 file, le32_to_cpu(adsp2_sizes->xm),
1636 le32_to_cpu(adsp2_sizes->ym),
1637 le32_to_cpu(adsp2_sizes->pm),
1638 le32_to_cpu(adsp2_sizes->zm));
1639 break;
1640
1641 default:
6c452bda 1642 WARN(1, "Unknown DSP type");
2159ad93
MB		 1643 goto out_fw;
1644 }
1645
1646 if (le32_to_cpu(header->len) != sizeof(*header) +
1647 sizes + sizeof(*footer)) {
1648 adsp_err(dsp, "%s: unexpected header length %d\n",
1649 file, le32_to_cpu(header->len));
1650 goto out_fw;
1651 }
1652
1653 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1654 le64_to_cpu(footer->timestamp));
1655
1656 while (pos < firmware->size &&
1657 pos - firmware->size > sizeof(*region)) {
1658 region = (void *)&(firmware->data[pos]);
1659 region_name = "Unknown";
1660 reg = 0;
1661 text = NULL;
1662 offset = le32_to_cpu(region->offset) & 0xffffff;
1663 type = be32_to_cpu(region->type) & 0xff;
1664 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1665
2159ad93
MB		 1666 switch (type) {
1667 case WMFW_NAME_TEXT:
1668 region_name = "Firmware name";
1669 text = kzalloc(le32_to_cpu(region->len) + 1,
1670 GFP_KERNEL);
1671 break;
2323736d
CK		 1672 case WMFW_ALGORITHM_DATA:
1673 region_name = "Algorithm";
1674 ret = wm_adsp_parse_coeff(dsp, region);
1675 if (ret != 0)
1676 goto out_fw;
1677 break;
2159ad93
MB		 1678 case WMFW_INFO_TEXT:
1679 region_name = "Information";
1680 text = kzalloc(le32_to_cpu(region->len) + 1,
1681 GFP_KERNEL);
1682 break;
1683 case WMFW_ABSOLUTE:
1684 region_name = "Absolute";
1685 reg = offset;
1686 break;
1687 case WMFW_ADSP1_PM:
2159ad93 1688 case WMFW_ADSP1_DM:
2159ad93 1689 case WMFW_ADSP2_XM:
2159ad93 1690 case WMFW_ADSP2_YM:
2159ad93 1691 case WMFW_ADSP1_ZM:
9ce5e6e6 1692 region_name = wm_adsp_mem_region_name(type);
45b9ee72 1693 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1694 break;
1695 default:
1696 adsp_warn(dsp,
1697 "%s.%d: Unknown region type %x at %d(%x)\n",
1698 file, regions, type, pos, pos);
1699 break;
1700 }
1701
1702 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1703 regions, le32_to_cpu(region->len), offset,
1704 region_name);
1705
1706 if (text) {
1707 memcpy(text, region->data, le32_to_cpu(region->len));
1708 adsp_info(dsp, "%s: %s\n", file, text);
1709 kfree(text);
1710 }
1711
1712 if (reg) {
cdcd7f72
CK		 1713 buf = wm_adsp_buf_alloc(region->data,
1714 le32_to_cpu(region->len),
1715 &buf_list);
1716 if (!buf) {
1717 adsp_err(dsp, "Out of memory\n");
1718 ret = -ENOMEM;
1719 goto out_fw;
1720 }
c1a7898d 1721
cdcd7f72
CK		 1722 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1723 le32_to_cpu(region->len));
1724 if (ret != 0) {
1725 adsp_err(dsp,
1726 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1727 file, regions,
1728 le32_to_cpu(region->len), offset,
1729 region_name, ret);
1730 goto out_fw;
2159ad93
MB		 1731 }
1732 }
1733
1734 pos += le32_to_cpu(region->len) + sizeof(*region);
1735 regions++;
1736 }
cf17c83c
MB		 1737
1738 ret = regmap_async_complete(regmap);
1739 if (ret != 0) {
1740 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1741 goto out_fw;
1742 }
1743
2159ad93
MB		 1744 if (pos > firmware->size)
1745 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1746 file, regions, pos - firmware->size);
1747
f9f55e31
RF		 1748 wm_adsp_debugfs_save_wmfwname(dsp, file);
1749
2159ad93 1750out_fw:
cf17c83c
MB		 1751 regmap_async_complete(regmap);
1752 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1753 release_firmware(firmware);
1754out:
1755 kfree(file);
1756
1757 return ret;
1758}
1759
2323736d
CK		 1760static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1761 const struct wm_adsp_alg_region *alg_region)
1762{
1763 struct wm_coeff_ctl *ctl;
1764
1765 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1766 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1767 alg_region->alg == ctl->alg_region.alg &&
1768 alg_region->type == ctl->alg_region.type) {
1769 ctl->alg_region.base = alg_region->base;
1770 }
1771 }
1772}
1773
3809f001 1774static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1775 unsigned int pos, unsigned int len)
db40517c 1776{
b618a185
CK		 1777 void *alg;
1778 int ret;
db40517c 1779 __be32 val;
db40517c 1780
3809f001 1781 if (n_algs == 0) {
b618a185
CK		 1782 adsp_err(dsp, "No algorithms\n");
1783 return ERR_PTR(-EINVAL);
db40517c
MB		 1784 }
1785
3809f001
CK		 1786 if (n_algs > 1024) {
1787 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1788 return ERR_PTR(-EINVAL);
1789 }
db40517c 1790
b618a185
CK		 1791 /* Read the terminator first to validate the length */
1792 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1793 if (ret != 0) {
1794 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1795 ret);
1796 return ERR_PTR(ret);
1797 }
db40517c 1798
b618a185
CK		 1799 if (be32_to_cpu(val) != 0xbedead)
1800 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1801 pos + len, be32_to_cpu(val));
d62f4bc6 1802
b618a185
CK		 1803 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1804 if (!alg)
1805 return ERR_PTR(-ENOMEM);
db40517c 1806
b618a185
CK		 1807 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1808 if (ret != 0) {
7d00cd97 1809 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
b618a185
CK		 1810 kfree(alg);
1811 return ERR_PTR(ret);
1812 }
ac50009f 1813
b618a185
CK		 1814 return alg;
1815}
ac50009f 1816
14197095
CK		 1817static struct wm_adsp_alg_region *
1818 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1819{
1820 struct wm_adsp_alg_region *alg_region;
1821
1822 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1823 if (id == alg_region->alg && type == alg_region->type)
1824 return alg_region;
1825 }
1826
1827 return NULL;
1828}
1829
d9d20e17
CK		 1830static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1831 int type, __be32 id,
1832 __be32 base)
1833{
1834 struct wm_adsp_alg_region *alg_region;
1835
1836 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1837 if (!alg_region)
1838 return ERR_PTR(-ENOMEM);
1839
1840 alg_region->type = type;
1841 alg_region->alg = be32_to_cpu(id);
1842 alg_region->base = be32_to_cpu(base);
1843
1844 list_add_tail(&alg_region->list, &dsp->alg_regions);
1845
2323736d
CK		 1846 if (dsp->fw_ver > 0)
1847 wm_adsp_ctl_fixup_base(dsp, alg_region);
1848
d9d20e17
CK		 1849 return alg_region;
1850}
1851
56574d54
RF		 1852static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1853{
1854 struct wm_adsp_alg_region *alg_region;
1855
1856 while (!list_empty(&dsp->alg_regions)) {
1857 alg_region = list_first_entry(&dsp->alg_regions,
1858 struct wm_adsp_alg_region,
1859 list);
1860 list_del(&alg_region->list);
1861 kfree(alg_region);
1862 }
1863}
1864
b618a185
CK		 1865static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1866{
1867 struct wmfw_adsp1_id_hdr adsp1_id;
1868 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1869 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1870 const struct wm_adsp_region *mem;
1871 unsigned int pos, len;
3809f001 1872 size_t n_algs;
b618a185 1873 int i, ret;
db40517c 1874
b618a185
CK		 1875 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1876 if (WARN_ON(!mem))
1877 return -EINVAL;
1878
1879 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1880 sizeof(adsp1_id));
1881 if (ret != 0) {
1882 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1883 ret);
1884 return ret;
1885 }
db40517c 1886
3809f001 1887 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1888 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1889 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1890 dsp->fw_id,
1891 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1892 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1893 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1894 n_algs);
b618a185 1895
d9d20e17
CK		 1896 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1897 adsp1_id.fw.id, adsp1_id.zm);
1898 if (IS_ERR(alg_region))
1899 return PTR_ERR(alg_region);
d62f4bc6 1900
d9d20e17
CK		 1901 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1902 adsp1_id.fw.id, adsp1_id.dm);
1903 if (IS_ERR(alg_region))
1904 return PTR_ERR(alg_region);
db40517c 1905
b618a185 1906 pos = sizeof(adsp1_id) / 2;
3809f001 1907 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1908
3809f001 1909 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1910 if (IS_ERR(adsp1_alg))
1911 return PTR_ERR(adsp1_alg);
1912
3809f001 1913 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1914 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1915 i, be32_to_cpu(adsp1_alg[i].alg.id),
1916 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1917 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1918 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1919 be32_to_cpu(adsp1_alg[i].dm),
1920 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1921
d9d20e17
CK		 1922 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1923 adsp1_alg[i].alg.id,
1924 adsp1_alg[i].dm);
1925 if (IS_ERR(alg_region)) {
1926 ret = PTR_ERR(alg_region);
b618a185
CK		 1927 goto out;
1928 }
2323736d
CK		 1929 if (dsp->fw_ver == 0) {
1930 if (i + 1 < n_algs) {
1931 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1932 len -= be32_to_cpu(adsp1_alg[i].dm);
1933 len *= 4;
1934 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 1935 len, NULL, 0, 0,
1936 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 1937 } else {
1938 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1939 be32_to_cpu(adsp1_alg[i].alg.id));
1940 }
b618a185 1941 }
ac50009f 1942
d9d20e17
CK		 1943 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1944 adsp1_alg[i].alg.id,
1945 adsp1_alg[i].zm);
1946 if (IS_ERR(alg_region)) {
1947 ret = PTR_ERR(alg_region);
b618a185
CK		 1948 goto out;
1949 }
2323736d
CK		 1950 if (dsp->fw_ver == 0) {
1951 if (i + 1 < n_algs) {
1952 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1953 len -= be32_to_cpu(adsp1_alg[i].zm);
1954 len *= 4;
1955 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 1956 len, NULL, 0, 0,
1957 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 1958 } else {
1959 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1960 be32_to_cpu(adsp1_alg[i].alg.id));
1961 }
b618a185 1962 }
db40517c
MB		 1963 }
1964
b618a185
CK		 1965out:
1966 kfree(adsp1_alg);
1967 return ret;
1968}
db40517c 1969
b618a185
CK		 1970static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1971{
1972 struct wmfw_adsp2_id_hdr adsp2_id;
1973 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1974 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1975 const struct wm_adsp_region *mem;
1976 unsigned int pos, len;
3809f001 1977 size_t n_algs;
b618a185
CK		 1978 int i, ret;
1979
1980 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1981 if (WARN_ON(!mem))
d62f4bc6 1982 return -EINVAL;
d62f4bc6 1983
b618a185
CK		 1984 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1985 sizeof(adsp2_id));
db40517c 1986 if (ret != 0) {
b618a185
CK		 1987 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1988 ret);
db40517c
MB		 1989 return ret;
1990 }
1991
3809f001 1992 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1993 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1994 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1995 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1996 dsp->fw_id,
f9f55e31
RF		 1997 (dsp->fw_id_version & 0xff0000) >> 16,
1998 (dsp->fw_id_version & 0xff00) >> 8,
1999 dsp->fw_id_version & 0xff,
3809f001 2000 n_algs);
b618a185 2001
d9d20e17
CK		 2002 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2003 adsp2_id.fw.id, adsp2_id.xm);
2004 if (IS_ERR(alg_region))
2005 return PTR_ERR(alg_region);
db40517c 2006
d9d20e17
CK		 2007 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2008 adsp2_id.fw.id, adsp2_id.ym);
2009 if (IS_ERR(alg_region))
2010 return PTR_ERR(alg_region);
db40517c 2011
d9d20e17
CK		 2012 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2013 adsp2_id.fw.id, adsp2_id.zm);
2014 if (IS_ERR(alg_region))
2015 return PTR_ERR(alg_region);
db40517c 2016
b618a185 2017 pos = sizeof(adsp2_id) / 2;
3809f001 2018 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 2019
3809f001 2020 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 2021 if (IS_ERR(adsp2_alg))
2022 return PTR_ERR(adsp2_alg);
471f4885 2023
3809f001 2024 for (i = 0; i < n_algs; i++) {
b618a185
CK		 2025 adsp_info(dsp,
2026 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2027 i, be32_to_cpu(adsp2_alg[i].alg.id),
2028 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2029 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2030 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2031 be32_to_cpu(adsp2_alg[i].xm),
2032 be32_to_cpu(adsp2_alg[i].ym),
2033 be32_to_cpu(adsp2_alg[i].zm));
db40517c 2034
d9d20e17
CK		 2035 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2036 adsp2_alg[i].alg.id,
2037 adsp2_alg[i].xm);
2038 if (IS_ERR(alg_region)) {
2039 ret = PTR_ERR(alg_region);
b618a185
CK		 2040 goto out;
2041 }
2323736d
CK		 2042 if (dsp->fw_ver == 0) {
2043 if (i + 1 < n_algs) {
2044 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2045 len -= be32_to_cpu(adsp2_alg[i].xm);
2046 len *= 4;
2047 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2048 len, NULL, 0, 0,
2049 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2050 } else {
2051 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2052 be32_to_cpu(adsp2_alg[i].alg.id));
2053 }
b618a185 2054 }
471f4885 2055
d9d20e17
CK		 2056 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2057 adsp2_alg[i].alg.id,
2058 adsp2_alg[i].ym);
2059 if (IS_ERR(alg_region)) {
2060 ret = PTR_ERR(alg_region);
b618a185
CK		 2061 goto out;
2062 }
2323736d
CK		 2063 if (dsp->fw_ver == 0) {
2064 if (i + 1 < n_algs) {
2065 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2066 len -= be32_to_cpu(adsp2_alg[i].ym);
2067 len *= 4;
2068 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2069 len, NULL, 0, 0,
2070 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2071 } else {
2072 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2073 be32_to_cpu(adsp2_alg[i].alg.id));
2074 }
b618a185 2075 }
471f4885 2076
d9d20e17
CK		 2077 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2078 adsp2_alg[i].alg.id,
2079 adsp2_alg[i].zm);
2080 if (IS_ERR(alg_region)) {
2081 ret = PTR_ERR(alg_region);
b618a185
CK		 2082 goto out;
2083 }
2323736d
CK		 2084 if (dsp->fw_ver == 0) {
2085 if (i + 1 < n_algs) {
2086 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2087 len -= be32_to_cpu(adsp2_alg[i].zm);
2088 len *= 4;
2089 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2090 len, NULL, 0, 0,
2091 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2092 } else {
2093 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2094 be32_to_cpu(adsp2_alg[i].alg.id));
2095 }
db40517c
MB		 2096 }
2097 }
2098
2099out:
b618a185 2100 kfree(adsp2_alg);
db40517c
MB		 2101 return ret;
2102}
2103
2159ad93
MB		 2104static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2105{
cf17c83c 2106 LIST_HEAD(buf_list);
2159ad93
MB		 2107 struct regmap *regmap = dsp->regmap;
2108 struct wmfw_coeff_hdr *hdr;
2109 struct wmfw_coeff_item *blk;
2110 const struct firmware *firmware;
471f4885
MB		 2111 const struct wm_adsp_region *mem;
2112 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 2113 const char *region_name;
2114 int ret, pos, blocks, type, offset, reg;
2115 char *file;
cf17c83c 2116 struct wm_adsp_buf *buf;
2159ad93
MB		 2117
2118 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2119 if (file == NULL)
2120 return -ENOMEM;
2121
1023dbd9
MB		 2122 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2123 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 2124 file[PAGE_SIZE - 1] = '\0';
2125
2126 ret = request_firmware(&firmware, file, dsp->dev);
2127 if (ret != 0) {
2128 adsp_warn(dsp, "Failed to request '%s'\n", file);
2129 ret = 0;
2130 goto out;
2131 }
2132 ret = -EINVAL;
2133
2134 if (sizeof(*hdr) >= firmware->size) {
2135 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2136 file, firmware->size);
2137 goto out_fw;
2138 }
2139
7585a5b0 2140 hdr = (void *)&firmware->data[0];
2159ad93
MB		 2141 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2142 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 2143 goto out_fw;
2159ad93
MB		 2144 }
2145
c712326d
MB		 2146 switch (be32_to_cpu(hdr->rev) & 0xff) {
2147 case 1:
2148 break;
2149 default:
2150 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2151 file, be32_to_cpu(hdr->rev) & 0xff);
2152 ret = -EINVAL;
2153 goto out_fw;
2154 }
2155
2159ad93
MB		 2156 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2157 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2158 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2159 le32_to_cpu(hdr->ver) & 0xff);
2160
2161 pos = le32_to_cpu(hdr->len);
2162
2163 blocks = 0;
2164 while (pos < firmware->size &&
2165 pos - firmware->size > sizeof(*blk)) {
7585a5b0 2166 blk = (void *)(&firmware->data[pos]);
2159ad93 2167
c712326d
MB		 2168 type = le16_to_cpu(blk->type);
2169 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 2170
2171 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2172 file, blocks, le32_to_cpu(blk->id),
2173 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2174 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2175 le32_to_cpu(blk->ver) & 0xff);
2176 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2177 file, blocks, le32_to_cpu(blk->len), offset, type);
2178
2179 reg = 0;
2180 region_name = "Unknown";
2181 switch (type) {
c712326d
MB		 2182 case (WMFW_NAME_TEXT << 8):
2183 case (WMFW_INFO_TEXT << 8):
2159ad93 2184 break;
c712326d 2185 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 2186 /*
2187 * Old files may use this for global
2188 * coefficients.
2189 */
2190 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2191 offset == 0) {
2192 region_name = "global coefficients";
2193 mem = wm_adsp_find_region(dsp, type);
2194 if (!mem) {
2195 adsp_err(dsp, "No ZM\n");
2196 break;
2197 }
2198 reg = wm_adsp_region_to_reg(mem, 0);
2199
2200 } else {
2201 region_name = "register";
2202 reg = offset;
2203 }
2159ad93 2204 break;
471f4885
MB		 2205
2206 case WMFW_ADSP1_DM:
2207 case WMFW_ADSP1_ZM:
2208 case WMFW_ADSP2_XM:
2209 case WMFW_ADSP2_YM:
2210 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2211 file, blocks, le32_to_cpu(blk->len),
2212 type, le32_to_cpu(blk->id));
2213
2214 mem = wm_adsp_find_region(dsp, type);
2215 if (!mem) {
2216 adsp_err(dsp, "No base for region %x\n", type);
2217 break;
2218 }
2219
14197095
CK		 2220 alg_region = wm_adsp_find_alg_region(dsp, type,
2221 le32_to_cpu(blk->id));
2222 if (alg_region) {
2223 reg = alg_region->base;
2224 reg = wm_adsp_region_to_reg(mem, reg);
2225 reg += offset;
2226 } else {
471f4885
MB		 2227 adsp_err(dsp, "No %x for algorithm %x\n",
2228 type, le32_to_cpu(blk->id));
14197095 2229 }
471f4885
MB		 2230 break;
2231
2159ad93 2232 default:
25c62f7e
MB		 2233 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2234 file, blocks, type, pos);
2159ad93
MB		 2235 break;
2236 }
2237
2238 if (reg) {
cf17c83c
MB		 2239 buf = wm_adsp_buf_alloc(blk->data,
2240 le32_to_cpu(blk->len),
2241 &buf_list);
a76fefab
MB		 2242 if (!buf) {
2243 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 2244 ret = -ENOMEM;
2245 goto out_fw;
a76fefab
MB		 2246 }
2247
20da6d5a
MB		 2248 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2249 file, blocks, le32_to_cpu(blk->len),
2250 reg);
cf17c83c
MB		 2251 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2252 le32_to_cpu(blk->len));
2159ad93
MB		 2253 if (ret != 0) {
2254 adsp_err(dsp,
43bc3bf6
DP		 2255 "%s.%d: Failed to write to %x in %s: %d\n",
2256 file, blocks, reg, region_name, ret);
2159ad93
MB		 2257 }
2258 }
2259
be951017 2260 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 2261 blocks++;
2262 }
2263
cf17c83c
MB		 2264 ret = regmap_async_complete(regmap);
2265 if (ret != 0)
2266 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2267
2159ad93
MB		 2268 if (pos > firmware->size)
2269 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2270 file, blocks, pos - firmware->size);
2271
f9f55e31
RF		 2272 wm_adsp_debugfs_save_binname(dsp, file);
2273
2159ad93 2274out_fw:
9da7a5a9 2275 regmap_async_complete(regmap);
2159ad93 2276 release_firmware(firmware);
cf17c83c 2277 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 2278out:
2279 kfree(file);
f4b82812 2280 return ret;
2159ad93
MB		 2281}
2282
3809f001 2283int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 2284{
3809f001 2285 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 2286
078e7183
CK		 2287 mutex_init(&dsp->pwr_lock);
2288
5e7a7a22
MB		 2289 return 0;
2290}
2291EXPORT_SYMBOL_GPL(wm_adsp1_init);
2292
2159ad93
MB		 2293int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2294 struct snd_kcontrol *kcontrol,
2295 int event)
2296{
72718517 2297 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 2298 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2299 struct wm_adsp *dsp = &dsps[w->shift];
6ab2b7b4 2300 struct wm_coeff_ctl *ctl;
2159ad93 2301 int ret;
7585a5b0 2302 unsigned int val;
2159ad93 2303
00200107 2304 dsp->card = codec->component.card;
92bb4c32 2305
078e7183
CK		 2306 mutex_lock(&dsp->pwr_lock);
2307
2159ad93
MB		 2308 switch (event) {
2309 case SND_SOC_DAPM_POST_PMU:
2310 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2311 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2312
94e205bf
CR		 2313 /*
2314 * For simplicity set the DSP clock rate to be the
2315 * SYSCLK rate rather than making it configurable.
2316 */
7585a5b0 2317 if (dsp->sysclk_reg) {
94e205bf
CR		 2318 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2319 if (ret != 0) {
2320 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2321 ret);
078e7183 2322 goto err_mutex;
94e205bf
CR		 2323 }
2324
7d00cd97 2325 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
94e205bf
CR		 2326
2327 ret = regmap_update_bits(dsp->regmap,
2328 dsp->base + ADSP1_CONTROL_31,
2329 ADSP1_CLK_SEL_MASK, val);
2330 if (ret != 0) {
2331 adsp_err(dsp, "Failed to set clock rate: %d\n",
2332 ret);
078e7183 2333 goto err_mutex;
94e205bf
CR		 2334 }
2335 }
2336
2159ad93
MB		 2337 ret = wm_adsp_load(dsp);
2338 if (ret != 0)
078e7183 2339 goto err_ena;
2159ad93 2340
b618a185 2341 ret = wm_adsp1_setup_algs(dsp);
db40517c 2342 if (ret != 0)
078e7183 2343 goto err_ena;
db40517c 2344
2159ad93
MB		 2345 ret = wm_adsp_load_coeff(dsp);
2346 if (ret != 0)
078e7183 2347 goto err_ena;
2159ad93 2348
0c2e3f34 2349 /* Initialize caches for enabled and unset controls */
81ad93ec 2350 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2351 if (ret != 0)
078e7183 2352 goto err_ena;
6ab2b7b4 2353
0c2e3f34 2354 /* Sync set controls */
81ad93ec 2355 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2356 if (ret != 0)
078e7183 2357 goto err_ena;
6ab2b7b4 2358
28823eba
CK		 2359 dsp->booted = true;
2360
2159ad93
MB		 2361 /* Start the core running */
2362 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2363 ADSP1_CORE_ENA | ADSP1_START,
2364 ADSP1_CORE_ENA | ADSP1_START);
28823eba
CK		 2365
2366 dsp->running = true;
2159ad93
MB		 2367 break;
2368
2369 case SND_SOC_DAPM_PRE_PMD:
28823eba
CK		 2370 dsp->running = false;
2371 dsp->booted = false;
2372
2159ad93
MB		 2373 /* Halt the core */
2374 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2375 ADSP1_CORE_ENA | ADSP1_START, 0);
2376
2377 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2378 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2379
2380 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2381 ADSP1_SYS_ENA, 0);
6ab2b7b4 2382
81ad93ec 2383 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2384 ctl->enabled = 0;
b0101b4f 2385
56574d54
RF		 2386
2387 wm_adsp_free_alg_regions(dsp);
2159ad93
MB		 2388 break;
2389
2390 default:
2391 break;
2392 }
2393
078e7183
CK		 2394 mutex_unlock(&dsp->pwr_lock);
2395
2159ad93
MB		 2396 return 0;
2397
078e7183 2398err_ena:
2159ad93
MB		 2399 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2400 ADSP1_SYS_ENA, 0);
078e7183
CK		 2401err_mutex:
2402 mutex_unlock(&dsp->pwr_lock);
2403
2159ad93
MB		 2404 return ret;
2405}
2406EXPORT_SYMBOL_GPL(wm_adsp1_event);
2407
2408static int wm_adsp2_ena(struct wm_adsp *dsp)
2409{
2410 unsigned int val;
2411 int ret, count;
2412
1552c325
MB		 2413 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2414 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 2415 if (ret != 0)
2416 return ret;
2417
2418 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2419 for (count = 0; count < 10; ++count) {
7d00cd97 2420 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2159ad93
MB		 2421 if (ret != 0)
2422 return ret;
939fd1e8
CK		 2423
2424 if (val & ADSP2_RAM_RDY)
2425 break;
2426
1fa96f3f 2427 usleep_range(250, 500);
939fd1e8 2428 }
2159ad93
MB		 2429
2430 if (!(val & ADSP2_RAM_RDY)) {
2431 adsp_err(dsp, "Failed to start DSP RAM\n");
2432 return -EBUSY;
2433 }
2434
2435 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2436
2437 return 0;
2438}
2439
18b1a902 2440static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2441{
d8a64d6a
CK		 2442 struct wm_adsp *dsp = container_of(work,
2443 struct wm_adsp,
2444 boot_work);
2159ad93
MB		 2445 int ret;
2446
078e7183
CK		 2447 mutex_lock(&dsp->pwr_lock);
2448
90d19ba5
CK		 2449 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2450 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2451 if (ret != 0)
2452 goto err_mutex;
2453
d8a64d6a
CK		 2454 ret = wm_adsp2_ena(dsp);
2455 if (ret != 0)
078e7183 2456 goto err_mutex;
2159ad93 2457
d8a64d6a
CK		 2458 ret = wm_adsp_load(dsp);
2459 if (ret != 0)
078e7183 2460 goto err_ena;
2159ad93 2461
b618a185 2462 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2463 if (ret != 0)
078e7183 2464 goto err_ena;
db40517c 2465
d8a64d6a
CK		 2466 ret = wm_adsp_load_coeff(dsp);
2467 if (ret != 0)
078e7183 2468 goto err_ena;
2159ad93 2469
d8a64d6a
CK		 2470 /* Initialize caches for enabled and unset controls */
2471 ret = wm_coeff_init_control_caches(dsp);
2472 if (ret != 0)
078e7183 2473 goto err_ena;
6ab2b7b4 2474
28823eba 2475 dsp->booted = true;
d8a64d6a 2476
90d19ba5
CK		 2477 /* Turn DSP back off until we are ready to run */
2478 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2479 ADSP2_SYS_ENA, 0);
2480 if (ret != 0)
2481 goto err_ena;
2482
078e7183
CK		 2483 mutex_unlock(&dsp->pwr_lock);
2484
d8a64d6a 2485 return;
6ab2b7b4 2486
078e7183 2487err_ena:
d8a64d6a
CK		 2488 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2489 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2490err_mutex:
2491 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2492}
2493
d82d767f
CK		 2494static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2495{
2496 int ret;
2497
2498 ret = regmap_update_bits_async(dsp->regmap,
2499 dsp->base + ADSP2_CLOCKING,
2500 ADSP2_CLK_SEL_MASK,
2501 freq << ADSP2_CLK_SEL_SHIFT);
2502 if (ret != 0)
2503 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2504}
2505
12db5edd 2506int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
d82d767f
CK		 2507 struct snd_kcontrol *kcontrol, int event,
2508 unsigned int freq)
12db5edd 2509{
72718517 2510 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2511 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2512 struct wm_adsp *dsp = &dsps[w->shift];
57a60cc3 2513 struct wm_coeff_ctl *ctl;
12db5edd 2514
00200107 2515 dsp->card = codec->component.card;
12db5edd
CK		 2516
2517 switch (event) {
2518 case SND_SOC_DAPM_PRE_PMU:
d82d767f 2519 wm_adsp2_set_dspclk(dsp, freq);
12db5edd
CK		 2520 queue_work(system_unbound_wq, &dsp->boot_work);
2521 break;
57a60cc3
CK		 2522 case SND_SOC_DAPM_PRE_PMD:
2523 wm_adsp_debugfs_clear(dsp);
2524
2525 dsp->fw_id = 0;
2526 dsp->fw_id_version = 0;
2527
2528 dsp->booted = false;
2529
2530 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2531 ADSP2_MEM_ENA, 0);
2532
2533 list_for_each_entry(ctl, &dsp->ctl_list, list)
2534 ctl->enabled = 0;
2535
2536 wm_adsp_free_alg_regions(dsp);
2537
2538 adsp_dbg(dsp, "Shutdown complete\n");
2539 break;
12db5edd
CK		 2540 default:
2541 break;
cab27258 2542 }
12db5edd
CK		 2543
2544 return 0;
2545}
2546EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2547
d8a64d6a
CK		 2548int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2549 struct snd_kcontrol *kcontrol, int event)
2550{
72718517 2551 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2552 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2553 struct wm_adsp *dsp = &dsps[w->shift];
d8a64d6a
CK		 2554 int ret;
2555
d8a64d6a
CK		 2556 switch (event) {
2557 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2558 flush_work(&dsp->boot_work);
2559
28823eba 2560 if (!dsp->booted)
d8a64d6a 2561 return -EIO;
6ab2b7b4 2562
90d19ba5
CK		 2563 ret = wm_adsp2_ena(dsp);
2564 if (ret != 0)
2565 goto err;
2566
cef45771
CK		 2567 /* Sync set controls */
2568 ret = wm_coeff_sync_controls(dsp);
2569 if (ret != 0)
2570 goto err;
2571
d8a64d6a
CK		 2572 ret = regmap_update_bits(dsp->regmap,
2573 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2574 ADSP2_CORE_ENA | ADSP2_START,
2575 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2576 if (ret != 0)
2577 goto err;
2cd19bdb 2578
28823eba
CK		 2579 dsp->running = true;
2580
612047f0
CK		 2581 mutex_lock(&dsp->pwr_lock);
2582
2cd19bdb
CK		 2583 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2584 ret = wm_adsp_buffer_init(dsp);
2585
612047f0
CK		 2586 mutex_unlock(&dsp->pwr_lock);
2587
2159ad93
MB		 2588 break;
2589
2590 case SND_SOC_DAPM_PRE_PMD:
f4f0c4c6
RF		 2591 /* Tell the firmware to cleanup */
2592 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2593
10337b07
RF		 2594 /* Log firmware state, it can be useful for analysis */
2595 wm_adsp2_show_fw_status(dsp);
2596
078e7183
CK		 2597 mutex_lock(&dsp->pwr_lock);
2598
1023dbd9
MB		 2599 dsp->running = false;
2600
2159ad93 2601 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
57a60cc3 2602 ADSP2_CORE_ENA | ADSP2_START, 0);
973838a0 2603
2d30b575 2604 /* Make sure DMAs are quiesced */
6facd2d1 2605 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2d30b575
MB		 2606 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2607 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
6facd2d1
ST		 2608
2609 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2610 ADSP2_SYS_ENA, 0);
2d30b575 2611
2cd19bdb
CK		 2612 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2613 wm_adsp_buffer_free(dsp);
2614
078e7183
CK		 2615 mutex_unlock(&dsp->pwr_lock);
2616
57a60cc3 2617 adsp_dbg(dsp, "Execution stopped\n");
2159ad93
MB		 2618 break;
2619
2620 default:
2621 break;
2622 }
2623
2624 return 0;
2625err:
2626 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2627 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2628 return ret;
2629}
2630EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2631
f5e2ce92
RF		 2632int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2633{
f9f55e31
RF		 2634 wm_adsp2_init_debugfs(dsp, codec);
2635
218e5087 2636 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2637 &wm_adsp_fw_controls[dsp->num - 1],
2638 1);
f5e2ce92
RF		 2639}
2640EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2641
2642int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2643{
f9f55e31
RF		 2644 wm_adsp2_cleanup_debugfs(dsp);
2645
f5e2ce92
RF		 2646 return 0;
2647}
2648EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2649
81ac58b1 2650int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2651{
2652 int ret;
2653
10a2b662
MB		 2654 /*
2655 * Disable the DSP memory by default when in reset for a small
2656 * power saving.
2657 */
3809f001 2658 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2659 ADSP2_MEM_ENA, 0);
2660 if (ret != 0) {
3809f001 2661 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2662 return ret;
2663 }
2664
3809f001
CK		 2665 INIT_LIST_HEAD(&dsp->alg_regions);
2666 INIT_LIST_HEAD(&dsp->ctl_list);
2667 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2668
078e7183
CK		 2669 mutex_init(&dsp->pwr_lock);
2670
973838a0
MB		 2671 return 0;
2672}
2673EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2674
66225e98
RF		 2675void wm_adsp2_remove(struct wm_adsp *dsp)
2676{
2677 struct wm_coeff_ctl *ctl;
2678
2679 while (!list_empty(&dsp->ctl_list)) {
2680 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2681 list);
2682 list_del(&ctl->list);
2683 wm_adsp_free_ctl_blk(ctl);
2684 }
2685}
2686EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2687
edd71350
CK		 2688static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2689{
2690 return compr->buf != NULL;
2691}
2692
2693static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2694{
2695 /*
2696 * Note this will be more complex once each DSP can support multiple
2697 * streams
2698 */
2699 if (!compr->dsp->buffer)
2700 return -EINVAL;
2701
2702 compr->buf = compr->dsp->buffer;
721be3be 2703 compr->buf->compr = compr;
edd71350
CK		 2704
2705 return 0;
2706}
2707
721be3be
CK		 2708static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2709{
2710 if (!compr)
2711 return;
2712
2713 /* Wake the poll so it can see buffer is no longer attached */
2714 if (compr->stream)
2715 snd_compr_fragment_elapsed(compr->stream);
2716
2717 if (wm_adsp_compr_attached(compr)) {
2718 compr->buf->compr = NULL;
2719 compr->buf = NULL;
2720 }
2721}
2722
406abc95
CK		 2723int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2724{
2725 struct wm_adsp_compr *compr;
2726 int ret = 0;
2727
2728 mutex_lock(&dsp->pwr_lock);
2729
2730 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2731 adsp_err(dsp, "Firmware does not support compressed API\n");
2732 ret = -ENXIO;
2733 goto out;
2734 }
2735
2736 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2737 adsp_err(dsp, "Firmware does not support stream direction\n");
2738 ret = -EINVAL;
2739 goto out;
2740 }
2741
95fe9597
CK		 2742 if (dsp->compr) {
2743 /* It is expect this limitation will be removed in future */
2744 adsp_err(dsp, "Only a single stream supported per DSP\n");
2745 ret = -EBUSY;
2746 goto out;
2747 }
2748
406abc95
CK		 2749 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2750 if (!compr) {
2751 ret = -ENOMEM;
2752 goto out;
2753 }
2754
2755 compr->dsp = dsp;
2756 compr->stream = stream;
2757
2758 dsp->compr = compr;
2759
2760 stream->runtime->private_data = compr;
2761
2762out:
2763 mutex_unlock(&dsp->pwr_lock);
2764
2765 return ret;
2766}
2767EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2768
2769int wm_adsp_compr_free(struct snd_compr_stream *stream)
2770{
2771 struct wm_adsp_compr *compr = stream->runtime->private_data;
2772 struct wm_adsp *dsp = compr->dsp;
2773
2774 mutex_lock(&dsp->pwr_lock);
2775
721be3be 2776 wm_adsp_compr_detach(compr);
406abc95
CK		 2777 dsp->compr = NULL;
2778
83a40ce9 2779 kfree(compr->raw_buf);
406abc95
CK		 2780 kfree(compr);
2781
2782 mutex_unlock(&dsp->pwr_lock);
2783
2784 return 0;
2785}
2786EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
2787
2788static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
2789 struct snd_compr_params *params)
2790{
2791 struct wm_adsp_compr *compr = stream->runtime->private_data;
2792 struct wm_adsp *dsp = compr->dsp;
2793 const struct wm_adsp_fw_caps *caps;
2794 const struct snd_codec_desc *desc;
2795 int i, j;
2796
2797 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
2798 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
2799 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
2800 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
2801 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
2802 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
2803 params->buffer.fragment_size,
2804 params->buffer.fragments);
2805
2806 return -EINVAL;
2807 }
2808
2809 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
2810 caps = &wm_adsp_fw[dsp->fw].caps[i];
2811 desc = &caps->desc;
2812
2813 if (caps->id != params->codec.id)
2814 continue;
2815
2816 if (stream->direction == SND_COMPRESS_PLAYBACK) {
2817 if (desc->max_ch < params->codec.ch_out)
2818 continue;
2819 } else {
2820 if (desc->max_ch < params->codec.ch_in)
2821 continue;
2822 }
2823
2824 if (!(desc->formats & (1 << params->codec.format)))
2825 continue;
2826
2827 for (j = 0; j < desc->num_sample_rates; ++j)
2828 if (desc->sample_rates[j] == params->codec.sample_rate)
2829 return 0;
2830 }
2831
2832 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
2833 params->codec.id, params->codec.ch_in, params->codec.ch_out,
2834 params->codec.sample_rate, params->codec.format);
2835 return -EINVAL;
2836}
2837
565ace46
CK		 2838static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
2839{
2840 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
2841}
2842
406abc95
CK		 2843int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
2844 struct snd_compr_params *params)
2845{
2846 struct wm_adsp_compr *compr = stream->runtime->private_data;
83a40ce9 2847 unsigned int size;
406abc95
CK		 2848 int ret;
2849
2850 ret = wm_adsp_compr_check_params(stream, params);
2851 if (ret)
2852 return ret;
2853
2854 compr->size = params->buffer;
2855
2856 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
2857 compr->size.fragment_size, compr->size.fragments);
2858
83a40ce9
CK		 2859 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
2860 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
2861 if (!compr->raw_buf)
2862 return -ENOMEM;
2863
da2b3358
CK		 2864 compr->sample_rate = params->codec.sample_rate;
2865
406abc95
CK		 2866 return 0;
2867}
2868EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
2869
2870int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
2871 struct snd_compr_caps *caps)
2872{
2873 struct wm_adsp_compr *compr = stream->runtime->private_data;
2874 int fw = compr->dsp->fw;
2875 int i;
2876
2877 if (wm_adsp_fw[fw].caps) {
2878 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
2879 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
2880
2881 caps->num_codecs = i;
2882 caps->direction = wm_adsp_fw[fw].compr_direction;
2883
2884 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
2885 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
2886 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
2887 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
2888 }
2889
2890 return 0;
2891}
2892EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
2893
2cd19bdb
CK		 2894static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
2895 unsigned int mem_addr,
2896 unsigned int num_words, u32 *data)
2897{
2898 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2899 unsigned int i, reg;
2900 int ret;
2901
2902 if (!mem)
2903 return -EINVAL;
2904
2905 reg = wm_adsp_region_to_reg(mem, mem_addr);
2906
2907 ret = regmap_raw_read(dsp->regmap, reg, data,
2908 sizeof(*data) * num_words);
2909 if (ret < 0)
2910 return ret;
2911
2912 for (i = 0; i < num_words; ++i)
2913 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
2914
2915 return 0;
2916}
2917
2918static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
2919 unsigned int mem_addr, u32 *data)
2920{
2921 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
2922}
2923
2924static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
2925 unsigned int mem_addr, u32 data)
2926{
2927 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2928 unsigned int reg;
2929
2930 if (!mem)
2931 return -EINVAL;
2932
2933 reg = wm_adsp_region_to_reg(mem, mem_addr);
2934
2935 data = cpu_to_be32(data & 0x00ffffffu);
2936
2937 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
2938}
2939
2940static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
2941 unsigned int field_offset, u32 *data)
2942{
2943 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
2944 buf->host_buf_ptr + field_offset, data);
2945}
2946
2947static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
2948 unsigned int field_offset, u32 data)
2949{
2950 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
2951 buf->host_buf_ptr + field_offset, data);
2952}
2953
2954static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
2955{
2956 struct wm_adsp_alg_region *alg_region;
2957 struct wm_adsp *dsp = buf->dsp;
2958 u32 xmalg, addr, magic;
2959 int i, ret;
2960
2961 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
2962 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
2963
2964 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
2965 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
2966 if (ret < 0)
2967 return ret;
2968
2969 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
2970 return -EINVAL;
2971
2972 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
2973 for (i = 0; i < 5; ++i) {
2974 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
2975 &buf->host_buf_ptr);
2976 if (ret < 0)
2977 return ret;
2978
2979 if (buf->host_buf_ptr)
2980 break;
2981
2982 usleep_range(1000, 2000);
2983 }
2984
2985 if (!buf->host_buf_ptr)
2986 return -EIO;
2987
2988 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
2989
2990 return 0;
2991}
2992
2993static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
2994{
2995 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
2996 struct wm_adsp_buffer_region *region;
2997 u32 offset = 0;
2998 int i, ret;
2999
3000 for (i = 0; i < caps->num_regions; ++i) {
3001 region = &buf->regions[i];
3002
3003 region->offset = offset;
3004 region->mem_type = caps->region_defs[i].mem_type;
3005
3006 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3007 &region->base_addr);
3008 if (ret < 0)
3009 return ret;
3010
3011 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3012 &offset);
3013 if (ret < 0)
3014 return ret;
3015
3016 region->cumulative_size = offset;
3017
3018 adsp_dbg(buf->dsp,
3019 "region=%d type=%d base=%04x off=%04x size=%04x\n",
3020 i, region->mem_type, region->base_addr,
3021 region->offset, region->cumulative_size);
3022 }
3023
3024 return 0;
3025}
3026
3027static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3028{
3029 struct wm_adsp_compr_buf *buf;
3030 int ret;
3031
3032 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3033 if (!buf)
3034 return -ENOMEM;
3035
3036 buf->dsp = dsp;
565ace46
CK		 3037 buf->read_index = -1;
3038 buf->irq_count = 0xFFFFFFFF;
2cd19bdb
CK		 3039
3040 ret = wm_adsp_buffer_locate(buf);
3041 if (ret < 0) {
3042 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
3043 goto err_buffer;
3044 }
3045
3046 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
3047 sizeof(*buf->regions), GFP_KERNEL);
3048 if (!buf->regions) {
3049 ret = -ENOMEM;
3050 goto err_buffer;
3051 }
3052
3053 ret = wm_adsp_buffer_populate(buf);
3054 if (ret < 0) {
3055 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
3056 goto err_regions;
3057 }
3058
3059 dsp->buffer = buf;
3060
3061 return 0;
3062
3063err_regions:
3064 kfree(buf->regions);
3065err_buffer:
3066 kfree(buf);
3067 return ret;
3068}
3069
3070static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3071{
3072 if (dsp->buffer) {
721be3be
CK		 3073 wm_adsp_compr_detach(dsp->buffer->compr);
3074
2cd19bdb
CK		 3075 kfree(dsp->buffer->regions);
3076 kfree(dsp->buffer);
3077
3078 dsp->buffer = NULL;
3079 }
3080
3081 return 0;
3082}
3083
95fe9597
CK		 3084int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3085{
3086 struct wm_adsp_compr *compr = stream->runtime->private_data;
3087 struct wm_adsp *dsp = compr->dsp;
3088 int ret = 0;
3089
3090 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3091
3092 mutex_lock(&dsp->pwr_lock);
3093
3094 switch (cmd) {
3095 case SNDRV_PCM_TRIGGER_START:
3096 if (wm_adsp_compr_attached(compr))
3097 break;
3098
3099 ret = wm_adsp_compr_attach(compr);
3100 if (ret < 0) {
3101 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3102 ret);
3103 break;
3104 }
565ace46
CK		 3105
3106 /* Trigger the IRQ at one fragment of data */
3107 ret = wm_adsp_buffer_write(compr->buf,
3108 HOST_BUFFER_FIELD(high_water_mark),
3109 wm_adsp_compr_frag_words(compr));
3110 if (ret < 0) {
3111 adsp_err(dsp, "Failed to set high water mark: %d\n",
3112 ret);
3113 break;
3114 }
95fe9597
CK		 3115 break;
3116 case SNDRV_PCM_TRIGGER_STOP:
3117 break;
3118 default:
3119 ret = -EINVAL;
3120 break;
3121 }
3122
3123 mutex_unlock(&dsp->pwr_lock);
3124
3125 return ret;
3126}
3127EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3128
565ace46
CK		 3129static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3130{
3131 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3132
3133 return buf->regions[last_region].cumulative_size;
3134}
3135
3136static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3137{
3138 u32 next_read_index, next_write_index;
3139 int write_index, read_index, avail;
3140 int ret;
3141
3142 /* Only sync read index if we haven't already read a valid index */
3143 if (buf->read_index < 0) {
3144 ret = wm_adsp_buffer_read(buf,
3145 HOST_BUFFER_FIELD(next_read_index),
3146 &next_read_index);
3147 if (ret < 0)
3148 return ret;
3149
3150 read_index = sign_extend32(next_read_index, 23);
3151
3152 if (read_index < 0) {
3153 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3154 return 0;
3155 }
3156
3157 buf->read_index = read_index;
3158 }
3159
3160 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3161 &next_write_index);
3162 if (ret < 0)
3163 return ret;
3164
3165 write_index = sign_extend32(next_write_index, 23);
3166
3167 avail = write_index - buf->read_index;
3168 if (avail < 0)
3169 avail += wm_adsp_buffer_size(buf);
3170
3171 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
33d740e0 3172 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
565ace46
CK		 3173
3174 buf->avail = avail;
3175
3176 return 0;
3177}
3178
9771b18a
CK		 3179static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3180{
3181 int ret;
3182
3183 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3184 if (ret < 0) {
3185 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3186 return ret;
3187 }
3188 if (buf->error != 0) {
3189 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3190 return -EIO;
3191 }
3192
3193 return 0;
3194}
3195
565ace46
CK		 3196int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3197{
612047f0
CK		 3198 struct wm_adsp_compr_buf *buf;
3199 struct wm_adsp_compr *compr;
565ace46
CK		 3200 int ret = 0;
3201
3202 mutex_lock(&dsp->pwr_lock);
3203
612047f0
CK		 3204 buf = dsp->buffer;
3205 compr = dsp->compr;
3206
565ace46 3207 if (!buf) {
565ace46
CK		 3208 ret = -ENODEV;
3209 goto out;
3210 }
3211
3212 adsp_dbg(dsp, "Handling buffer IRQ\n");
3213
9771b18a
CK		 3214 ret = wm_adsp_buffer_get_error(buf);
3215 if (ret < 0)
5847609e 3216 goto out_notify; /* Wake poll to report error */
565ace46
CK		 3217
3218 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3219 &buf->irq_count);
3220 if (ret < 0) {
3221 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3222 goto out;
3223 }
3224
3225 ret = wm_adsp_buffer_update_avail(buf);
3226 if (ret < 0) {
3227 adsp_err(dsp, "Error reading avail: %d\n", ret);
3228 goto out;
3229 }
3230
20b7f7c5
CK		 3231 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3232 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3233
5847609e 3234out_notify:
c7dae7c4 3235 if (compr && compr->stream)
83a40ce9
CK		 3236 snd_compr_fragment_elapsed(compr->stream);
3237
565ace46
CK		 3238out:
3239 mutex_unlock(&dsp->pwr_lock);
3240
3241 return ret;
3242}
3243EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3244
3245static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3246{
3247 if (buf->irq_count & 0x01)
3248 return 0;
3249
3250 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3251 buf->irq_count);
3252
3253 buf->irq_count |= 0x01;
3254
3255 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3256 buf->irq_count);
3257}
3258
3259int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3260 struct snd_compr_tstamp *tstamp)
3261{
3262 struct wm_adsp_compr *compr = stream->runtime->private_data;
565ace46 3263 struct wm_adsp *dsp = compr->dsp;
612047f0 3264 struct wm_adsp_compr_buf *buf;
565ace46
CK		 3265 int ret = 0;
3266
3267 adsp_dbg(dsp, "Pointer request\n");
3268
3269 mutex_lock(&dsp->pwr_lock);
3270
612047f0
CK		 3271 buf = compr->buf;
3272
28ee3d73 3273 if (!compr->buf || compr->buf->error) {
8d280664 3274 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
565ace46
CK		 3275 ret = -EIO;
3276 goto out;
3277 }
3278
3279 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3280 ret = wm_adsp_buffer_update_avail(buf);
3281 if (ret < 0) {
3282 adsp_err(dsp, "Error reading avail: %d\n", ret);
3283 goto out;
3284 }
3285
3286 /*
3287 * If we really have less than 1 fragment available tell the
3288 * DSP to inform us once a whole fragment is available.
3289 */
3290 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
5847609e 3291 ret = wm_adsp_buffer_get_error(buf);
8d280664
CK		 3292 if (ret < 0) {
3293 if (compr->buf->error)
3294 snd_compr_stop_error(stream,
3295 SNDRV_PCM_STATE_XRUN);
5847609e 3296 goto out;
8d280664 3297 }
5847609e 3298
565ace46
CK		 3299 ret = wm_adsp_buffer_reenable_irq(buf);
3300 if (ret < 0) {
3301 adsp_err(dsp,
3302 "Failed to re-enable buffer IRQ: %d\n",
3303 ret);
3304 goto out;
3305 }
3306 }
3307 }
3308
3309 tstamp->copied_total = compr->copied_total;
3310 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
da2b3358 3311 tstamp->sampling_rate = compr->sample_rate;
565ace46
CK		 3312
3313out:
3314 mutex_unlock(&dsp->pwr_lock);
3315
3316 return ret;
3317}
3318EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3319
83a40ce9
CK		 3320static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3321{
3322 struct wm_adsp_compr_buf *buf = compr->buf;
3323 u8 *pack_in = (u8 *)compr->raw_buf;
3324 u8 *pack_out = (u8 *)compr->raw_buf;
3325 unsigned int adsp_addr;
3326 int mem_type, nwords, max_read;
3327 int i, j, ret;
3328
3329 /* Calculate read parameters */
3330 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3331 if (buf->read_index < buf->regions[i].cumulative_size)
3332 break;
3333
3334 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3335 return -EINVAL;
3336
3337 mem_type = buf->regions[i].mem_type;
3338 adsp_addr = buf->regions[i].base_addr +
3339 (buf->read_index - buf->regions[i].offset);
3340
3341 max_read = wm_adsp_compr_frag_words(compr);
3342 nwords = buf->regions[i].cumulative_size - buf->read_index;
3343
3344 if (nwords > target)
3345 nwords = target;
3346 if (nwords > buf->avail)
3347 nwords = buf->avail;
3348 if (nwords > max_read)
3349 nwords = max_read;
3350 if (!nwords)
3351 return 0;
3352
3353 /* Read data from DSP */
3354 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3355 nwords, compr->raw_buf);
3356 if (ret < 0)
3357 return ret;
3358
3359 /* Remove the padding bytes from the data read from the DSP */
3360 for (i = 0; i < nwords; i++) {
3361 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3362 *pack_out++ = *pack_in++;
3363
3364 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3365 }
3366
3367 /* update read index to account for words read */
3368 buf->read_index += nwords;
3369 if (buf->read_index == wm_adsp_buffer_size(buf))
3370 buf->read_index = 0;
3371
3372 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3373 buf->read_index);
3374 if (ret < 0)
3375 return ret;
3376
3377 /* update avail to account for words read */
3378 buf->avail -= nwords;
3379
3380 return nwords;
3381}
3382
3383static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3384 char __user *buf, size_t count)
3385{
3386 struct wm_adsp *dsp = compr->dsp;
3387 int ntotal = 0;
3388 int nwords, nbytes;
3389
3390 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3391
28ee3d73 3392 if (!compr->buf || compr->buf->error) {
8d280664 3393 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
83a40ce9 3394 return -EIO;
8d280664 3395 }
83a40ce9
CK		 3396
3397 count /= WM_ADSP_DATA_WORD_SIZE;
3398
3399 do {
3400 nwords = wm_adsp_buffer_capture_block(compr, count);
3401 if (nwords < 0) {
3402 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3403 return nwords;
3404 }
3405
3406 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3407
3408 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3409
3410 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3411 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3412 ntotal, nbytes);
3413 return -EFAULT;
3414 }
3415
3416 count -= nwords;
3417 ntotal += nbytes;
3418 } while (nwords > 0 && count > 0);
3419
3420 compr->copied_total += ntotal;
3421
3422 return ntotal;
3423}
3424
3425int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3426 size_t count)
3427{
3428 struct wm_adsp_compr *compr = stream->runtime->private_data;
3429 struct wm_adsp *dsp = compr->dsp;
3430 int ret;
3431
3432 mutex_lock(&dsp->pwr_lock);
3433
3434 if (stream->direction == SND_COMPRESS_CAPTURE)
3435 ret = wm_adsp_compr_read(compr, buf, count);
3436 else
3437 ret = -ENOTSUPP;
3438
3439 mutex_unlock(&dsp->pwr_lock);
3440
3441 return ret;
3442}
3443EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3444
0a37c6ef 3445MODULE_LICENSE("GPL v2");
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