[linux.git] / drivers / ide / au1xxx-ide.c

/*
 * BRIEF MODULE DESCRIPTION
 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
 *
 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free Software
 * Foundation; either version 2 of the License, or (at your option) any later
 * version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
 *       Interface and Linux Device Driver" Application Note.
 */
#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/scatterlist.h>

#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1xxx_ide.h>

#define DRV_NAME	"au1200-ide"
#define DRV_AUTHOR	"Enrico Walther <[email protected]> / Pete Popov <[email protected]>"

/* enable the burstmode in the dbdma */
#define IDE_AU1XXX_BURSTMODE	1

static _auide_hwif auide_hwif;

#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)

static inline void auide_insw(unsigned long port, void *addr, u32 count)
{
	_auide_hwif *ahwif = &auide_hwif;
	chan_tab_t *ctp;
	au1x_ddma_desc_t *dp;

	if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 
			   DDMA_FLAGS_NOIE)) {
		printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
		return;
	}
	ctp = *((chan_tab_t **)ahwif->rx_chan);
	dp = ctp->cur_ptr;
	while (dp->dscr_cmd0 & DSCR_CMD0_V)
		;
	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
}

static inline void auide_outsw(unsigned long port, void *addr, u32 count)
{
	_auide_hwif *ahwif = &auide_hwif;
	chan_tab_t *ctp;
	au1x_ddma_desc_t *dp;

	if(!put_source_flags(ahwif->tx_chan, (void*)addr,
			     count << 1, DDMA_FLAGS_NOIE)) {
		printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
		return;
	}
	ctp = *((chan_tab_t **)ahwif->tx_chan);
	dp = ctp->cur_ptr;
	while (dp->dscr_cmd0 & DSCR_CMD0_V)
		;
	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
}

static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
			      void *buf, unsigned int len)
{
	auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
}

static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
			       void *buf, unsigned int len)
{
	auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
}
#endif

static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);

	switch (drive->pio_mode - XFER_PIO_0) {
	case 0:
		mem_sttime = SBC_IDE_TIMING(PIO0);

		/* set configuration for RCS2# */
		mem_stcfg |= TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
		break;

	case 1:
		mem_sttime = SBC_IDE_TIMING(PIO1);

		/* set configuration for RCS2# */
		mem_stcfg |= TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
		break;

	case 2:
		mem_sttime = SBC_IDE_TIMING(PIO2);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
		break;

	case 3:
		mem_sttime = SBC_IDE_TIMING(PIO3);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;

		break;

	case 4:
		mem_sttime = SBC_IDE_TIMING(PIO4);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
		break;
	}

	au_writel(mem_sttime,MEM_STTIME2);
	au_writel(mem_stcfg,MEM_STCFG2);
}

static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);

	switch (drive->dma_mode) {
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	case XFER_MW_DMA_2:
		mem_sttime = SBC_IDE_TIMING(MDMA2);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;

		break;
	case XFER_MW_DMA_1:
		mem_sttime = SBC_IDE_TIMING(MDMA1);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;

		break;
	case XFER_MW_DMA_0:
		mem_sttime = SBC_IDE_TIMING(MDMA0);

		/* set configuration for RCS2# */
		mem_stcfg |= TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;

		break;
#endif
	}

	au_writel(mem_sttime,MEM_STTIME2);
	au_writel(mem_stcfg,MEM_STCFG2);
}

/*
 * Multi-Word DMA + DbDMA functions
 */

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	_auide_hwif *ahwif = &auide_hwif;
	struct scatterlist *sg;
	int i = cmd->sg_nents, count = 0;
	int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);

	/* Save for interrupt context */
	ahwif->drive = drive;

	/* fill the descriptors */
	sg = hwif->sg_table;
	while (i && sg_dma_len(sg)) {
		u32 cur_addr;
		u32 cur_len;

		cur_addr = sg_dma_address(sg);
		cur_len = sg_dma_len(sg);

		while (cur_len) {
			u32 flags = DDMA_FLAGS_NOIE;
			unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;

			if (++count >= PRD_ENTRIES) {
				printk(KERN_WARNING "%s: DMA table too small\n",
				       drive->name);
				return 0;
			}

			/* Lets enable intr for the last descriptor only */
			if (1==i)
				flags = DDMA_FLAGS_IE;
			else
				flags = DDMA_FLAGS_NOIE;

			if (iswrite) {
				if(!put_source_flags(ahwif->tx_chan, 
						     (void*) sg_virt(sg),
						     tc, flags)) { 
					printk(KERN_ERR "%s failed %d\n", 
					       __func__, __LINE__);
				}
			} else 
			{
				if(!put_dest_flags(ahwif->rx_chan, 
						   (void*) sg_virt(sg),
						   tc, flags)) { 
					printk(KERN_ERR "%s failed %d\n", 
					       __func__, __LINE__);
				}
			}

			cur_addr += tc;
			cur_len -= tc;
		}
		sg = sg_next(sg);
		i--;
	}

	if (count)
		return 1;

	return 0; /* revert to PIO for this request */
}

static int auide_dma_end(ide_drive_t *drive)
{
	return 0;
}

static void auide_dma_start(ide_drive_t *drive )
{
}


static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	if (auide_build_dmatable(drive, cmd) == 0)
		return 1;

	return 0;
}

static int auide_dma_test_irq(ide_drive_t *drive)
{
	/* If dbdma didn't execute the STOP command yet, the
	 * active bit is still set
	 */
	drive->waiting_for_dma++;
	if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
		printk(KERN_WARNING "%s: timeout waiting for ddma to \
                                     complete\n", drive->name);
		return 1;
	}
	udelay(10);
	return 0;
}

static void auide_dma_host_set(ide_drive_t *drive, int on)
{
}

static void auide_ddma_tx_callback(int irq, void *param)
{
}

static void auide_ddma_rx_callback(int irq, void *param)
{
}
#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */

static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
{
	dev->dev_id          = dev_id;
	dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
	dev->dev_intlevel    = 0;
	dev->dev_intpolarity = 0;
	dev->dev_tsize       = tsize;
	dev->dev_devwidth    = devwidth;
	dev->dev_flags       = flags;
}

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
static const struct ide_dma_ops au1xxx_dma_ops = {
	.dma_host_set		= auide_dma_host_set,
	.dma_setup		= auide_dma_setup,
	.dma_start		= auide_dma_start,
	.dma_end		= auide_dma_end,
	.dma_test_irq		= auide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
};

static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	_auide_hwif *auide = &auide_hwif;
	dbdev_tab_t source_dev_tab, target_dev_tab;
	u32 dev_id, tsize, devwidth, flags;

	dev_id	 = IDE_DDMA_REQ;

	tsize    =  8; /*  1 */
	devwidth = 32; /* 16 */

#ifdef IDE_AU1XXX_BURSTMODE 
	flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
#else
	flags = DEV_FLAGS_SYNC;
#endif

	/* setup dev_tab for tx channel */
	auide_init_dbdma_dev( &source_dev_tab,
			      dev_id,
			      tsize, devwidth, DEV_FLAGS_OUT | flags);
 	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );

	auide_init_dbdma_dev( &source_dev_tab,
			      dev_id,
			      tsize, devwidth, DEV_FLAGS_IN | flags);
 	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	
	/* We also need to add a target device for the DMA */
	auide_init_dbdma_dev( &target_dev_tab,
			      (u32)DSCR_CMD0_ALWAYS,
			      tsize, devwidth, DEV_FLAGS_ANYUSE);
	auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);	
 
	/* Get a channel for TX */
	auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
						 auide->tx_dev_id,
						 auide_ddma_tx_callback,
						 (void*)auide);
 
	/* Get a channel for RX */
	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
						 auide->target_dev_id,
						 auide_ddma_rx_callback,
						 (void*)auide);

	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
							     NUM_DESCRIPTORS);
	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
							     NUM_DESCRIPTORS);

	/* FIXME: check return value */
	(void)ide_allocate_dma_engine(hwif);
	
	au1xxx_dbdma_start( auide->tx_chan );
	au1xxx_dbdma_start( auide->rx_chan );
 
	return 0;
} 
#else
static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	_auide_hwif *auide = &auide_hwif;
	dbdev_tab_t source_dev_tab;
	int flags;

#ifdef IDE_AU1XXX_BURSTMODE 
	flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
#else
	flags = DEV_FLAGS_SYNC;
#endif

	/* setup dev_tab for tx channel */
	auide_init_dbdma_dev( &source_dev_tab,
			      (u32)DSCR_CMD0_ALWAYS,
			      8, 32, DEV_FLAGS_OUT | flags);
 	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );

	auide_init_dbdma_dev( &source_dev_tab,
			      (u32)DSCR_CMD0_ALWAYS,
			      8, 32, DEV_FLAGS_IN | flags);
 	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	
	/* Get a channel for TX */
	auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
						 auide->tx_dev_id,
						 NULL,
						 (void*)auide);
 
	/* Get a channel for RX */
	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
						 DSCR_CMD0_ALWAYS,
						 NULL,
						 (void*)auide);
 
	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
							     NUM_DESCRIPTORS);
	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
							     NUM_DESCRIPTORS);
 
	au1xxx_dbdma_start( auide->tx_chan );
	au1xxx_dbdma_start( auide->rx_chan );
 	
	return 0;
}
#endif

static void auide_setup_ports(struct ide_hw *hw, _auide_hwif *ahwif)
{
	int i;
	unsigned long *ata_regs = hw->io_ports_array;

	/* FIXME? */
	for (i = 0; i < 8; i++)
		*ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);

	/* set the Alternative Status register */
	*ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
}

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
static const struct ide_tp_ops au1xxx_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ide_dev_select,
	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= au1xxx_input_data,
	.output_data		= au1xxx_output_data,
};
#endif

static const struct ide_port_ops au1xxx_port_ops = {
	.set_pio_mode		= au1xxx_set_pio_mode,
	.set_dma_mode		= auide_set_dma_mode,
};

static const struct ide_port_info au1xxx_port_info = {
	.init_dma		= auide_ddma_init,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
	.tp_ops			= &au1xxx_tp_ops,
#endif
	.port_ops		= &au1xxx_port_ops,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	.dma_ops		= &au1xxx_dma_ops,
#endif
	.host_flags		= IDE_HFLAG_POST_SET_MODE |
				  IDE_HFLAG_NO_IO_32BIT |
				  IDE_HFLAG_UNMASK_IRQS,
	.pio_mask		= ATA_PIO4,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	.mwdma_mask		= ATA_MWDMA2,
#endif
	.chipset		= ide_au1xxx,
};

static int au_ide_probe(struct platform_device *dev)
{
	_auide_hwif *ahwif = &auide_hwif;
	struct resource *res;
	struct ide_host *host;
	int ret = 0;
	struct ide_hw hw, *hws[] = { &hw };

#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
	char *mode = "MWDMA2";
#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
	char *mode = "PIO+DDMA(offload)";
#endif

	memset(&auide_hwif, 0, sizeof(_auide_hwif));
	ahwif->irq = platform_get_irq(dev, 0);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);

	if (res == NULL) {
		pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
		ret = -ENODEV;
		goto out;
	}
	if (ahwif->irq < 0) {
		pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
		ret = -ENODEV;
		goto out;
	}

	if (!request_mem_region(res->start, resource_size(res), dev->name)) {
		pr_debug("%s: request_mem_region failed\n", DRV_NAME);
		ret =  -EBUSY;
		goto out;
	}

	ahwif->regbase = (u32)ioremap(res->start, resource_size(res));
	if (ahwif->regbase == 0) {
		ret = -ENOMEM;
		goto out;
	}

	memset(&hw, 0, sizeof(hw));
	auide_setup_ports(&hw, ahwif);
	hw.irq = ahwif->irq;
	hw.dev = &dev->dev;

	ret = ide_host_add(&au1xxx_port_info, hws, 1, &host);
	if (ret)
		goto out;

	auide_hwif.hwif = host->ports[0];

	platform_set_drvdata(dev, host);

	printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );

 out:
	return ret;
}

static int au_ide_remove(struct platform_device *dev)
{
	struct resource *res;
	struct ide_host *host = platform_get_drvdata(dev);
	_auide_hwif *ahwif = &auide_hwif;

	ide_host_remove(host);

	iounmap((void *)ahwif->regbase);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, resource_size(res));

	return 0;
}

static struct platform_driver au1200_ide_driver = {
	.driver = {
		.name		= "au1200-ide",
		.owner		= THIS_MODULE,
	},
	.probe 		= au_ide_probe,
	.remove		= au_ide_remove,
};

static int __init au_ide_init(void)
{
	return platform_driver_register(&au1200_ide_driver);
}

static void __exit au_ide_exit(void)
{
	platform_driver_unregister(&au1200_ide_driver);
}

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("AU1200 IDE driver");

module_init(au_ide_init);
module_exit(au_ide_exit);
Commit	Line	Data
26a940e2	1	/*
26a940e2 PP	2	* BRIEF MODULE DESCRIPTION
	3	* AMD Alchemy Au1xxx IDE interface routines over the Static Bus
	4	*
	5	* Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
	6	*
	7	* This program is free software; you can redistribute it and/or modify it under
	8	* the terms of the GNU General Public License as published by the Free Software
	9	* Foundation; either version 2 of the License, or (at your option) any later
	10	* version.
	11	*
	12	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
	13	* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
	14	* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
	15	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	16	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	17	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	18	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	19	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	20	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	21	* POSSIBILITY OF SUCH DAMAGE.
	22	*
	23	* You should have received a copy of the GNU General Public License along with
	24	* this program; if not, write to the Free Software Foundation, Inc.,
	25	* 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	* Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
	28	* Interface and Linux Device Driver" Application Note.
	29	*/
26a940e2 PP	30	#include <linux/types.h>
	31	#include <linux/module.h>
	32	#include <linux/kernel.h>
	33	#include <linux/delay.h>
8f29e650	34	#include <linux/platform_device.h>
26a940e2 PP	35	#include <linux/init.h>
26a940e2 PP	36	#include <linux/ide.h>
fabd3a22	37	#include <linux/scatterlist.h>
26a940e2	38
26a940e2 PP	39	#include <asm/mach-au1x00/au1xxx.h>
26a940e2 PP	40	#include <asm/mach-au1x00/au1xxx_dbdma.h>
26a940e2 PP	41	#include <asm/mach-au1x00/au1xxx_ide.h>
	42
	43	#define DRV_NAME "au1200-ide"
8f29e650	44	#define DRV_AUTHOR "Enrico Walther <[email protected]> / Pete Popov <[email protected]>"
26a940e2	45
8f29e650 JC	46	/* enable the burstmode in the dbdma */
8f29e650 JC	47	#define IDE_AU1XXX_BURSTMODE 1
26a940e2	48
8f29e650	49	static _auide_hwif auide_hwif;
26a940e2	50
26a940e2 PP	51	#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
26a940e2 PP	52
985232e3	53	static inline void auide_insw(unsigned long port, void *addr, u32 count)
26a940e2	54	{
8f29e650 JC	55	_auide_hwif *ahwif = &auide_hwif;
	56	chan_tab_t *ctp;
	57	au1x_ddma_desc_t *dp;
26a940e2	58
8f29e650 JC	59	if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
8f29e650 JC	60	DDMA_FLAGS_NOIE)) {
eb63963a	61	printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
8f29e650 JC	62	return;
	63	}
	64	ctp = ((chan_tab_t *)ahwif->rx_chan);
	65	dp = ctp->cur_ptr;
	66	while (dp->dscr_cmd0 & DSCR_CMD0_V)
	67	;
	68	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
26a940e2 PP	69	}
26a940e2 PP	70
985232e3	71	static inline void auide_outsw(unsigned long port, void *addr, u32 count)
26a940e2	72	{
8f29e650 JC	73	_auide_hwif *ahwif = &auide_hwif;
	74	chan_tab_t *ctp;
	75	au1x_ddma_desc_t *dp;
26a940e2	76
8f29e650 JC	77	if(!put_source_flags(ahwif->tx_chan, (void*)addr,
8f29e650 JC	78	count << 1, DDMA_FLAGS_NOIE)) {
eb63963a	79	printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
8f29e650 JC	80	return;
	81	}
	82	ctp = ((chan_tab_t *)ahwif->tx_chan);
	83	dp = ctp->cur_ptr;
	84	while (dp->dscr_cmd0 & DSCR_CMD0_V)
	85	;
	86	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
26a940e2 PP	87	}
26a940e2 PP	88
adb1af98	89	static void au1xxx_input_data(ide_drive_t drive, struct ide_cmd cmd,
70f91e0d BZ	90	void *buf, unsigned int len)
	91	{
	92	auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
	93	}
	94
adb1af98	95	static void au1xxx_output_data(ide_drive_t drive, struct ide_cmd cmd,
70f91e0d BZ	96	void *buf, unsigned int len)
	97	{
	98	auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
	99	}
26a940e2	100	#endif
26a940e2	101
e085b3ca	102	static void au1xxx_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
26a940e2	103	{
88b2b32b	104	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
8f29e650	105
e085b3ca	106	switch (drive->pio_mode - XFER_PIO_0) {
8f29e650 JC	107	case 0:
	108	mem_sttime = SBC_IDE_TIMING(PIO0);
	109
	110	/* set configuration for RCS2# */
	111	mem_stcfg \|= TS_MASK;
	112	mem_stcfg &= ~TCSOE_MASK;
	113	mem_stcfg &= ~TOECS_MASK;
	114	mem_stcfg \|= SBC_IDE_PIO0_TCSOE \| SBC_IDE_PIO0_TOECS;
	115	break;
	116
	117	case 1:
	118	mem_sttime = SBC_IDE_TIMING(PIO1);
	119
	120	/* set configuration for RCS2# */
	121	mem_stcfg \|= TS_MASK;
	122	mem_stcfg &= ~TCSOE_MASK;
	123	mem_stcfg &= ~TOECS_MASK;
	124	mem_stcfg \|= SBC_IDE_PIO1_TCSOE \| SBC_IDE_PIO1_TOECS;
	125	break;
	126
	127	case 2:
	128	mem_sttime = SBC_IDE_TIMING(PIO2);
	129
	130	/* set configuration for RCS2# */
	131	mem_stcfg &= ~TS_MASK;
	132	mem_stcfg &= ~TCSOE_MASK;
	133	mem_stcfg &= ~TOECS_MASK;
	134	mem_stcfg \|= SBC_IDE_PIO2_TCSOE \| SBC_IDE_PIO2_TOECS;
	135	break;
	136
	137	case 3:
	138	mem_sttime = SBC_IDE_TIMING(PIO3);
	139
	140	/* set configuration for RCS2# */
	141	mem_stcfg &= ~TS_MASK;
	142	mem_stcfg &= ~TCSOE_MASK;
	143	mem_stcfg &= ~TOECS_MASK;
	144	mem_stcfg \|= SBC_IDE_PIO3_TCSOE \| SBC_IDE_PIO3_TOECS;
	145
	146	break;
	147
	148	case 4:
	149	mem_sttime = SBC_IDE_TIMING(PIO4);
	150
	151	/* set configuration for RCS2# */
	152	mem_stcfg &= ~TS_MASK;
	153	mem_stcfg &= ~TCSOE_MASK;
	154	mem_stcfg &= ~TOECS_MASK;
	155	mem_stcfg \|= SBC_IDE_PIO4_TCSOE \| SBC_IDE_PIO4_TOECS;
	156	break;
	157	}
	158
	159	au_writel(mem_sttime,MEM_STTIME2);
	160	au_writel(mem_stcfg,MEM_STCFG2);
26a940e2 PP	161	}
26a940e2 PP	162
8776168c	163	static void auide_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
26a940e2	164	{
88b2b32b	165	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
26a940e2	166
8776168c	167	switch (drive->dma_mode) {
26a940e2	168	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
8f29e650 JC	169	case XFER_MW_DMA_2:
	170	mem_sttime = SBC_IDE_TIMING(MDMA2);
	171
	172	/* set configuration for RCS2# */
	173	mem_stcfg &= ~TS_MASK;
	174	mem_stcfg &= ~TCSOE_MASK;
	175	mem_stcfg &= ~TOECS_MASK;
	176	mem_stcfg \|= SBC_IDE_MDMA2_TCSOE \| SBC_IDE_MDMA2_TOECS;
	177
8f29e650 JC	178	break;
	179	case XFER_MW_DMA_1:
	180	mem_sttime = SBC_IDE_TIMING(MDMA1);
	181
	182	/* set configuration for RCS2# */
	183	mem_stcfg &= ~TS_MASK;
	184	mem_stcfg &= ~TCSOE_MASK;
	185	mem_stcfg &= ~TOECS_MASK;
	186	mem_stcfg \|= SBC_IDE_MDMA1_TCSOE \| SBC_IDE_MDMA1_TOECS;
	187
8f29e650 JC	188	break;
	189	case XFER_MW_DMA_0:
	190	mem_sttime = SBC_IDE_TIMING(MDMA0);
	191
	192	/* set configuration for RCS2# */
	193	mem_stcfg \|= TS_MASK;
	194	mem_stcfg &= ~TCSOE_MASK;
	195	mem_stcfg &= ~TOECS_MASK;
	196	mem_stcfg \|= SBC_IDE_MDMA0_TCSOE \| SBC_IDE_MDMA0_TOECS;
	197
8f29e650	198	break;
26a940e2	199	#endif
8f29e650	200	}
a523a175	201
8f29e650 JC	202	au_writel(mem_sttime,MEM_STTIME2);
8f29e650 JC	203	au_writel(mem_stcfg,MEM_STCFG2);
26a940e2 PP	204	}
	205
	206	/*
	207	* Multi-Word DMA + DbDMA functions
	208	*/
26a940e2	209
8f29e650	210	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
22981694	211	static int auide_build_dmatable(ide_drive_t drive, struct ide_cmd cmd)
26a940e2	212	{
898ec223	213	ide_hwif_t *hwif = drive->hwif;
a536f326	214	_auide_hwif *ahwif = &auide_hwif;
8f29e650	215	struct scatterlist *sg;
22981694 BZ	216	int i = cmd->sg_nents, count = 0;
22981694 BZ	217	int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
8f29e650	218
8f29e650 JC	219	/* Save for interrupt context */
	220	ahwif->drive = drive;
	221
8f29e650 JC	222	/* fill the descriptors */
	223	sg = hwif->sg_table;
	224	while (i && sg_dma_len(sg)) {
	225	u32 cur_addr;
	226	u32 cur_len;
	227
	228	cur_addr = sg_dma_address(sg);
	229	cur_len = sg_dma_len(sg);
	230
	231	while (cur_len) {
	232	u32 flags = DDMA_FLAGS_NOIE;
	233	unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
	234
	235	if (++count >= PRD_ENTRIES) {
	236	printk(KERN_WARNING "%s: DMA table too small\n",
	237	drive->name);
11998b31	238	return 0;
8f29e650 JC	239	}
	240
	241	/* Lets enable intr for the last descriptor only */
	242	if (1==i)
	243	flags = DDMA_FLAGS_IE;
	244	else
	245	flags = DDMA_FLAGS_NOIE;
	246
	247	if (iswrite) {
	248	if(!put_source_flags(ahwif->tx_chan,
45711f1a	249	(void*) sg_virt(sg),
8f29e650 JC	250	tc, flags)) {
8f29e650 JC	251	printk(KERN_ERR "%s failed %d\n",
eb63963a	252	__func__, __LINE__);
26a940e2	253	}
8f29e650	254	} else
26a940e2	255	{
8f29e650	256	if(!put_dest_flags(ahwif->rx_chan,
45711f1a	257	(void*) sg_virt(sg),
8f29e650 JC	258	tc, flags)) {
8f29e650 JC	259	printk(KERN_ERR "%s failed %d\n",
eb63963a	260	__func__, __LINE__);
26a940e2	261	}
8f29e650	262	}
26a940e2	263
8f29e650 JC	264	cur_addr += tc;
	265	cur_len -= tc;
	266	}
55c16a70	267	sg = sg_next(sg);
8f29e650 JC	268	i--;
8f29e650 JC	269	}
26a940e2	270
8f29e650 JC	271	if (count)
8f29e650 JC	272	return 1;
26a940e2	273
8f29e650	274	return 0; /* revert to PIO for this request */
26a940e2 PP	275	}
	276
	277	static int auide_dma_end(ide_drive_t *drive)
	278	{
8f29e650	279	return 0;
26a940e2 PP	280	}
	281
	282	static void auide_dma_start(ide_drive_t *drive )
	283	{
26a940e2 PP	284	}
26a940e2 PP	285
26a940e2	286
22981694	287	static int auide_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
b65fac32	288	{
11998b31	289	if (auide_build_dmatable(drive, cmd) == 0)
8f29e650	290	return 1;
26a940e2	291
8f29e650	292	return 0;
26a940e2 PP	293	}
26a940e2 PP	294
26a940e2	295	static int auide_dma_test_irq(ide_drive_t *drive)
c67c216d	296	{
8f29e650 JC	297	/* If dbdma didn't execute the STOP command yet, the
8f29e650 JC	298	* active bit is still set
26a940e2	299	*/
8f29e650 JC	300	drive->waiting_for_dma++;
	301	if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
	302	printk(KERN_WARNING "%s: timeout waiting for ddma to \
26a940e2	303	complete\n", drive->name);
8f29e650 JC	304	return 1;
	305	}
	306	udelay(10);
	307	return 0;
26a940e2 PP	308	}
26a940e2 PP	309
15ce926a	310	static void auide_dma_host_set(ide_drive_t *drive, int on)
26a940e2	311	{
26a940e2 PP	312	}
26a940e2 PP	313
53e62d3a	314	static void auide_ddma_tx_callback(int irq, void *param)
26a940e2	315	{
26a940e2 PP	316	}
26a940e2 PP	317
53e62d3a	318	static void auide_ddma_rx_callback(int irq, void *param)
26a940e2	319	{
8f29e650	320	}
8f29e650	321	#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
26a940e2	322
8f29e650 JC	323	static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
	324	{
	325	dev->dev_id = dev_id;
fcbd3b4b	326	dev->dev_physaddr = (u32)IDE_PHYS_ADDR;
8f29e650 JC	327	dev->dev_intlevel = 0;
	328	dev->dev_intpolarity = 0;
	329	dev->dev_tsize = tsize;
	330	dev->dev_devwidth = devwidth;
	331	dev->dev_flags = flags;
26a940e2 PP	332	}
26a940e2 PP	333
5e37bdc0	334	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
f37afdac	335	static const struct ide_dma_ops au1xxx_dma_ops = {
5e37bdc0 BZ	336	.dma_host_set = auide_dma_host_set,
5e37bdc0 BZ	337	.dma_setup = auide_dma_setup,
5e37bdc0 BZ	338	.dma_start = auide_dma_start,
	339	.dma_end = auide_dma_end,
	340	.dma_test_irq = auide_dma_test_irq,
de23ec9c	341	.dma_lost_irq = ide_dma_lost_irq,
5e37bdc0 BZ	342	};
5e37bdc0 BZ	343
85528659 BZ	344	static int auide_ddma_init(ide_hwif_t hwif, const struct ide_port_info d)
85528659 BZ	345	{
a536f326	346	_auide_hwif *auide = &auide_hwif;
8f29e650 JC	347	dbdev_tab_t source_dev_tab, target_dev_tab;
8f29e650 JC	348	u32 dev_id, tsize, devwidth, flags;
26a940e2	349
fcbd3b4b	350	dev_id = IDE_DDMA_REQ;
26a940e2	351
f629b38b BZ	352	tsize = 8; /* 1 */
f629b38b BZ	353	devwidth = 32; /* 16 */
26a940e2	354
8f29e650 JC	355	#ifdef IDE_AU1XXX_BURSTMODE
8f29e650 JC	356	flags = DEV_FLAGS_SYNC \| DEV_FLAGS_BURSTABLE;
26a940e2	357	#else
8f29e650	358	flags = DEV_FLAGS_SYNC;
26a940e2 PP	359	#endif
26a940e2 PP	360
8f29e650 JC	361	/* setup dev_tab for tx channel */
	362	auide_init_dbdma_dev( &source_dev_tab,
	363	dev_id,
	364	tsize, devwidth, DEV_FLAGS_OUT \| flags);
	365	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	366
	367	auide_init_dbdma_dev( &source_dev_tab,
	368	dev_id,
	369	tsize, devwidth, DEV_FLAGS_IN \| flags);
	370	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	371
	372	/* We also need to add a target device for the DMA */
	373	auide_init_dbdma_dev( &target_dev_tab,
	374	(u32)DSCR_CMD0_ALWAYS,
	375	tsize, devwidth, DEV_FLAGS_ANYUSE);
	376	auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
	377
	378	/* Get a channel for TX */
	379	auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
	380	auide->tx_dev_id,
	381	auide_ddma_tx_callback,
	382	(void*)auide);
	383
	384	/* Get a channel for RX */
	385	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
	386	auide->target_dev_id,
	387	auide_ddma_rx_callback,
	388	(void*)auide);
	389
	390	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
	391	NUM_DESCRIPTORS);
	392	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
	393	NUM_DESCRIPTORS);
2bbd57ca BZ	394
	395	/* FIXME: check return value */
	396	(void)ide_allocate_dma_engine(hwif);
8f29e650 JC	397
	398	au1xxx_dbdma_start( auide->tx_chan );
	399	au1xxx_dbdma_start( auide->rx_chan );
	400
	401	return 0;
	402	}
26a940e2	403	#else
85528659	404	static int auide_ddma_init(ide_hwif_t hwif, const struct ide_port_info d)
8f29e650	405	{
a536f326	406	_auide_hwif *auide = &auide_hwif;
8f29e650 JC	407	dbdev_tab_t source_dev_tab;
8f29e650 JC	408	int flags;
26a940e2	409
8f29e650 JC	410	#ifdef IDE_AU1XXX_BURSTMODE
	411	flags = DEV_FLAGS_SYNC \| DEV_FLAGS_BURSTABLE;
	412	#else
	413	flags = DEV_FLAGS_SYNC;
26a940e2	414	#endif
26a940e2	415
8f29e650 JC	416	/* setup dev_tab for tx channel */
	417	auide_init_dbdma_dev( &source_dev_tab,
	418	(u32)DSCR_CMD0_ALWAYS,
	419	8, 32, DEV_FLAGS_OUT \| flags);
	420	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	421
	422	auide_init_dbdma_dev( &source_dev_tab,
	423	(u32)DSCR_CMD0_ALWAYS,
	424	8, 32, DEV_FLAGS_IN \| flags);
	425	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	426
	427	/* Get a channel for TX */
	428	auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
	429	auide->tx_dev_id,
	430	NULL,
	431	(void*)auide);
	432
	433	/* Get a channel for RX */
	434	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
	435	DSCR_CMD0_ALWAYS,
	436	NULL,
	437	(void*)auide);
	438
	439	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
	440	NUM_DESCRIPTORS);
	441	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
	442	NUM_DESCRIPTORS);
	443
	444	au1xxx_dbdma_start( auide->tx_chan );
	445	au1xxx_dbdma_start( auide->rx_chan );
	446
	447	return 0;
26a940e2	448	}
8f29e650	449	#endif
26a940e2	450
9f36d314	451	static void auide_setup_ports(struct ide_hw hw, _auide_hwif ahwif)
26a940e2	452	{
8f29e650	453	int i;
4c3032d8	454	unsigned long *ata_regs = hw->io_ports_array;
8f29e650 JC	455
8f29e650 JC	456	/* FIXME? */
4c3032d8	457	for (i = 0; i < 8; i++)
fcbd3b4b	458	*ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
8f29e650 JC	459
8f29e650 JC	460	/* set the Alternative Status register */
fcbd3b4b	461	*ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
26a940e2 PP	462	}
26a940e2 PP	463
374e042c BZ	464	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
	465	static const struct ide_tp_ops au1xxx_tp_ops = {
	466	.exec_command = ide_exec_command,
	467	.read_status = ide_read_status,
	468	.read_altstatus = ide_read_altstatus,
ecf3a31d	469	.write_devctl = ide_write_devctl,
374e042c	470
abb596b2	471	.dev_select = ide_dev_select,
374e042c BZ	472	.tf_load = ide_tf_load,
	473	.tf_read = ide_tf_read,
	474
	475	.input_data = au1xxx_input_data,
	476	.output_data = au1xxx_output_data,
	477	};
	478	#endif
	479
ac95beed BZ	480	static const struct ide_port_ops au1xxx_port_ops = {
	481	.set_pio_mode = au1xxx_set_pio_mode,
	482	.set_dma_mode = auide_set_dma_mode,
ac95beed BZ	483	};
ac95beed BZ	484
c413b9b9	485	static const struct ide_port_info au1xxx_port_info = {
85528659	486	.init_dma = auide_ddma_init,
374e042c BZ	487	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
	488	.tp_ops = &au1xxx_tp_ops,
	489	#endif
ac95beed	490	.port_ops = &au1xxx_port_ops,
5e37bdc0 BZ	491	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	492	.dma_ops = &au1xxx_dma_ops,
	493	#endif
c413b9b9	494	.host_flags = IDE_HFLAG_POST_SET_MODE \|
807b90d0	495	IDE_HFLAG_NO_IO_32BIT \|
c413b9b9 BZ	496	IDE_HFLAG_UNMASK_IRQS,
	497	.pio_mask = ATA_PIO4,
	498	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	499	.mwdma_mask = ATA_MWDMA2,
	500	#endif
29e52cf7	501	.chipset = ide_au1xxx,
c413b9b9 BZ	502	};
c413b9b9 BZ	503
7a192ec3	504	static int au_ide_probe(struct platform_device *dev)
26a940e2	505	{
8f29e650	506	_auide_hwif *ahwif = &auide_hwif;
26a940e2	507	struct resource *res;
48c3c107	508	struct ide_host *host;
26a940e2	509	int ret = 0;
9f36d314	510	struct ide_hw hw, *hws[] = { &hw };
26a940e2 PP	511
26a940e2 PP	512	#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
8f29e650	513	char *mode = "MWDMA2";
26a940e2	514	#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
8f29e650	515	char *mode = "PIO+DDMA(offload)";
26a940e2 PP	516	#endif
26a940e2 PP	517
8f29e650	518	memset(&auide_hwif, 0, sizeof(_auide_hwif));
7a192ec3	519	ahwif->irq = platform_get_irq(dev, 0);
26a940e2	520
7a192ec3	521	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
26a940e2 PP	522
26a940e2 PP	523	if (res == NULL) {
7a192ec3	524	pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
26a940e2	525	ret = -ENODEV;
48944738 DV	526	goto out;
	527	}
	528	if (ahwif->irq < 0) {
7a192ec3	529	pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
48944738	530	ret = -ENODEV;
26a940e2 PP	531	goto out;
	532	}
	533
4b7c7237	534	if (!request_mem_region(res->start, resource_size(res), dev->name)) {
26a940e2	535	pr_debug("%s: request_mem_region failed\n", DRV_NAME);
8f29e650	536	ret = -EBUSY;
26a940e2	537	goto out;
8f29e650	538	}
26a940e2	539
4b7c7237	540	ahwif->regbase = (u32)ioremap(res->start, resource_size(res));
26a940e2 PP	541	if (ahwif->regbase == 0) {
	542	ret = -ENOMEM;
	543	goto out;
	544	}
	545
9239b333 BZ	546	memset(&hw, 0, sizeof(hw));
9239b333 BZ	547	auide_setup_ports(&hw, ahwif);
aa79a2fa	548	hw.irq = ahwif->irq;
7a192ec3	549	hw.dev = &dev->dev;
aa79a2fa	550
dca39830	551	ret = ide_host_add(&au1xxx_port_info, hws, 1, &host);
6f904d01	552	if (ret)
48c3c107	553	goto out;
5cbf79cd	554
48c3c107	555	auide_hwif.hwif = host->ports[0];
5cbf79cd	556
7a192ec3	557	platform_set_drvdata(dev, host);
26a940e2	558
8f29e650	559	printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
26a940e2	560
8f29e650 JC	561	out:
8f29e650 JC	562	return ret;
26a940e2 PP	563	}
26a940e2 PP	564
7a192ec3	565	static int au_ide_remove(struct platform_device *dev)
26a940e2	566	{
26a940e2	567	struct resource *res;
7a192ec3	568	struct ide_host *host = platform_get_drvdata(dev);
8f29e650	569	_auide_hwif *ahwif = &auide_hwif;
26a940e2	570
48c3c107	571	ide_host_remove(host);
26a940e2 PP	572
	573	iounmap((void *)ahwif->regbase);
	574
7a192ec3	575	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
4b7c7237	576	release_mem_region(res->start, resource_size(res));
26a940e2 PP	577
	578	return 0;
	579	}
	580
7a192ec3 ML	581	static struct platform_driver au1200_ide_driver = {
	582	.driver = {
	583	.name = "au1200-ide",
	584	.owner = THIS_MODULE,
	585	},
26a940e2 PP	586	.probe = au_ide_probe,
	587	.remove = au_ide_remove,
	588	};
	589
	590	static int __init au_ide_init(void)
	591	{
7a192ec3	592	return platform_driver_register(&au1200_ide_driver);
26a940e2 PP	593	}
26a940e2 PP	594
8f29e650	595	static void __exit au_ide_exit(void)
26a940e2	596	{
7a192ec3	597	platform_driver_unregister(&au1200_ide_driver);
26a940e2 PP	598	}
26a940e2 PP	599
26a940e2 PP	600	MODULE_LICENSE("GPL");
	601	MODULE_DESCRIPTION("AU1200 IDE driver");
	602
	603	module_init(au_ide_init);
	604	module_exit(au_ide_exit);