[linux.git] / lib / iomap.c

/*
 * Implement the default iomap interfaces
 *
 * (C) Copyright 2004 Linus Torvalds
 */
#include <linux/pci.h>
#include <linux/io.h>

#include <linux/module.h>

/*
 * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
 * access or a MMIO access, these functions don't care. The info is
 * encoded in the hardware mapping set up by the mapping functions
 * (or the cookie itself, depending on implementation and hw).
 *
 * The generic routines don't assume any hardware mappings, and just
 * encode the PIO/MMIO as part of the cookie. They coldly assume that
 * the MMIO IO mappings are not in the low address range.
 *
 * Architectures for which this is not true can't use this generic
 * implementation and should do their own copy.
 */

#ifndef HAVE_ARCH_PIO_SIZE
/*
 * We encode the physical PIO addresses (0-0xffff) into the
 * pointer by offsetting them with a constant (0x10000) and
 * assuming that all the low addresses are always PIO. That means
 * we can do some sanity checks on the low bits, and don't
 * need to just take things for granted.
 */
#define PIO_OFFSET	0x10000UL
#define PIO_MASK	0x0ffffUL
#define PIO_RESERVED	0x40000UL
#endif

static void bad_io_access(unsigned long port, const char *access)
{
	static int count = 10;
	if (count) {
		count--;
		printk(KERN_ERR "Bad IO access at port %#lx (%s)\n", port, access);
		WARN_ON(1);
	}
}

/*
 * Ugly macros are a way of life.
 */
#define IO_COND(addr, is_pio, is_mmio) do {			\
	unsigned long port = (unsigned long __force)addr;	\
	if (port >= PIO_RESERVED) {				\
		is_mmio;					\
	} else if (port > PIO_OFFSET) {				\
		port &= PIO_MASK;				\
		is_pio;						\
	} else							\
		bad_io_access(port, #is_pio );			\
} while (0)

#ifndef pio_read16be
#define pio_read16be(port) swab16(inw(port))
#define pio_read32be(port) swab32(inl(port))
#endif

#ifndef mmio_read16be
#define mmio_read16be(addr) be16_to_cpu(__raw_readw(addr))
#define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
#endif

unsigned int fastcall ioread8(void __iomem *addr)
{
	IO_COND(addr, return inb(port), return readb(addr));
	return 0xff;
}
unsigned int fastcall ioread16(void __iomem *addr)
{
	IO_COND(addr, return inw(port), return readw(addr));
	return 0xffff;
}
unsigned int fastcall ioread16be(void __iomem *addr)
{
	IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
	return 0xffff;
}
unsigned int fastcall ioread32(void __iomem *addr)
{
	IO_COND(addr, return inl(port), return readl(addr));
	return 0xffffffff;
}
unsigned int fastcall ioread32be(void __iomem *addr)
{
	IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
	return 0xffffffff;
}
EXPORT_SYMBOL(ioread8);
EXPORT_SYMBOL(ioread16);
EXPORT_SYMBOL(ioread16be);
EXPORT_SYMBOL(ioread32);
EXPORT_SYMBOL(ioread32be);

#ifndef pio_write16be
#define pio_write16be(val,port) outw(swab16(val),port)
#define pio_write32be(val,port) outl(swab32(val),port)
#endif

#ifndef mmio_write16be
#define mmio_write16be(val,port) __raw_writew(be16_to_cpu(val),port)
#define mmio_write32be(val,port) __raw_writel(be32_to_cpu(val),port)
#endif

void fastcall iowrite8(u8 val, void __iomem *addr)
{
	IO_COND(addr, outb(val,port), writeb(val, addr));
}
void fastcall iowrite16(u16 val, void __iomem *addr)
{
	IO_COND(addr, outw(val,port), writew(val, addr));
}
void fastcall iowrite16be(u16 val, void __iomem *addr)
{
	IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
}
void fastcall iowrite32(u32 val, void __iomem *addr)
{
	IO_COND(addr, outl(val,port), writel(val, addr));
}
void fastcall iowrite32be(u32 val, void __iomem *addr)
{
	IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
}
EXPORT_SYMBOL(iowrite8);
EXPORT_SYMBOL(iowrite16);
EXPORT_SYMBOL(iowrite16be);
EXPORT_SYMBOL(iowrite32);
EXPORT_SYMBOL(iowrite32be);

/*
 * These are the "repeat MMIO read/write" functions.
 * Note the "__raw" accesses, since we don't want to
 * convert to CPU byte order. We write in "IO byte
 * order" (we also don't have IO barriers).
 */
#ifndef mmio_insb
static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
{
	while (--count >= 0) {
		u8 data = __raw_readb(addr);
		*dst = data;
		dst++;
	}
}
static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
{
	while (--count >= 0) {
		u16 data = __raw_readw(addr);
		*dst = data;
		dst++;
	}
}
static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
{
	while (--count >= 0) {
		u32 data = __raw_readl(addr);
		*dst = data;
		dst++;
	}
}
#endif

#ifndef mmio_outsb
static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
{
	while (--count >= 0) {
		__raw_writeb(*src, addr);
		src++;
	}
}
static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
{
	while (--count >= 0) {
		__raw_writew(*src, addr);
		src++;
	}
}
static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
{
	while (--count >= 0) {
		__raw_writel(*src, addr);
		src++;
	}
}
#endif

void fastcall ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
{
	IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
}
void fastcall ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
{
	IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
}
void fastcall ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
{
	IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
}
EXPORT_SYMBOL(ioread8_rep);
EXPORT_SYMBOL(ioread16_rep);
EXPORT_SYMBOL(ioread32_rep);

void fastcall iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
{
	IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
}
void fastcall iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
{
	IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
}
void fastcall iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
{
	IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
}
EXPORT_SYMBOL(iowrite8_rep);
EXPORT_SYMBOL(iowrite16_rep);
EXPORT_SYMBOL(iowrite32_rep);

/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
	if (port > PIO_MASK)
		return NULL;
	return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
}

void ioport_unmap(void __iomem *addr)
{
	/* Nothing to do */
}
EXPORT_SYMBOL(ioport_map);
EXPORT_SYMBOL(ioport_unmap);

/**
 * pci_iomap - create a virtual mapping cookie for a PCI BAR
 * @dev: PCI device that owns the BAR
 * @bar: BAR number
 * @maxlen: length of the memory to map
 *
 * Using this function you will get a __iomem address to your device BAR.
 * You can access it using ioread*() and iowrite*(). These functions hide
 * the details if this is a MMIO or PIO address space and will just do what
 * you expect from them in the correct way.
 *
 * @maxlen specifies the maximum length to map. If you want to get access to
 * the complete BAR without checking for its length first, pass %0 here.
 * */
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
	unsigned long start = pci_resource_start(dev, bar);
	unsigned long len = pci_resource_len(dev, bar);
	unsigned long flags = pci_resource_flags(dev, bar);

	if (!len || !start)
		return NULL;
	if (maxlen && len > maxlen)
		len = maxlen;
	if (flags & IORESOURCE_IO)
		return ioport_map(start, len);
	if (flags & IORESOURCE_MEM) {
		if (flags & IORESOURCE_CACHEABLE)
			return ioremap(start, len);
		return ioremap_nocache(start, len);
	}
	/* What? */
	return NULL;
}

void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
	IO_COND(addr, /* nothing */, iounmap(addr));
}
EXPORT_SYMBOL(pci_iomap);
EXPORT_SYMBOL(pci_iounmap);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Implement the default iomap interfaces
	3	*
	4	* (C) Copyright 2004 Linus Torvalds
	5	*/
	6	#include <linux/pci.h>
9ac7849e TH	7	#include <linux/io.h>
9ac7849e TH	8
1da177e4	9	#include <linux/module.h>
1da177e4 LT	10
	11	/*
	12	* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
	13	* access or a MMIO access, these functions don't care. The info is
	14	* encoded in the hardware mapping set up by the mapping functions
	15	* (or the cookie itself, depending on implementation and hw).
	16	*
	17	* The generic routines don't assume any hardware mappings, and just
	18	* encode the PIO/MMIO as part of the cookie. They coldly assume that
	19	* the MMIO IO mappings are not in the low address range.
	20	*
	21	* Architectures for which this is not true can't use this generic
	22	* implementation and should do their own copy.
	23	*/
	24
	25	#ifndef HAVE_ARCH_PIO_SIZE
	26	/*
	27	* We encode the physical PIO addresses (0-0xffff) into the
	28	* pointer by offsetting them with a constant (0x10000) and
	29	* assuming that all the low addresses are always PIO. That means
	30	* we can do some sanity checks on the low bits, and don't
	31	* need to just take things for granted.
	32	*/
	33	#define PIO_OFFSET 0x10000UL
	34	#define PIO_MASK 0x0ffffUL
	35	#define PIO_RESERVED 0x40000UL
	36	#endif
	37
6cbf0c70 LT	38	static void bad_io_access(unsigned long port, const char *access)
	39	{
	40	static int count = 10;
	41	if (count) {
	42	count--;
debe6214	43	printk(KERN_ERR "Bad IO access at port %#lx (%s)\n", port, access);
6cbf0c70 LT	44	WARN_ON(1);
	45	}
	46	}
	47
1da177e4 LT	48	/*
	49	* Ugly macros are a way of life.
	50	*/
1da177e4 LT	51	#define IO_COND(addr, is_pio, is_mmio) do { \
1da177e4 LT	52	unsigned long port = (unsigned long __force)addr; \
6cbf0c70 LT	53	if (port >= PIO_RESERVED) { \
	54	is_mmio; \
	55	} else if (port > PIO_OFFSET) { \
1da177e4 LT	56	port &= PIO_MASK; \
1da177e4 LT	57	is_pio; \
6cbf0c70 LT	58	} else \
6cbf0c70 LT	59	bad_io_access(port, #is_pio ); \
1da177e4 LT	60	} while (0)
1da177e4 LT	61
34ba8a5c LT	62	#ifndef pio_read16be
	63	#define pio_read16be(port) swab16(inw(port))
	64	#define pio_read32be(port) swab32(inl(port))
	65	#endif
	66
	67	#ifndef mmio_read16be
	68	#define mmio_read16be(addr) be16_to_cpu(__raw_readw(addr))
	69	#define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
	70	#endif
	71
1da177e4 LT	72	unsigned int fastcall ioread8(void __iomem *addr)
	73	{
	74	IO_COND(addr, return inb(port), return readb(addr));
6cbf0c70	75	return 0xff;
1da177e4 LT	76	}
	77	unsigned int fastcall ioread16(void __iomem *addr)
	78	{
	79	IO_COND(addr, return inw(port), return readw(addr));
6cbf0c70	80	return 0xffff;
1da177e4	81	}
dae409a2 JB	82	unsigned int fastcall ioread16be(void __iomem *addr)
dae409a2 JB	83	{
34ba8a5c	84	IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
6cbf0c70	85	return 0xffff;
dae409a2	86	}
1da177e4 LT	87	unsigned int fastcall ioread32(void __iomem *addr)
	88	{
	89	IO_COND(addr, return inl(port), return readl(addr));
6cbf0c70	90	return 0xffffffff;
1da177e4	91	}
dae409a2 JB	92	unsigned int fastcall ioread32be(void __iomem *addr)
dae409a2 JB	93	{
34ba8a5c	94	IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
6cbf0c70	95	return 0xffffffff;
dae409a2	96	}
1da177e4 LT	97	EXPORT_SYMBOL(ioread8);
1da177e4 LT	98	EXPORT_SYMBOL(ioread16);
dae409a2	99	EXPORT_SYMBOL(ioread16be);
1da177e4	100	EXPORT_SYMBOL(ioread32);
dae409a2	101	EXPORT_SYMBOL(ioread32be);
1da177e4	102
34ba8a5c LT	103	#ifndef pio_write16be
	104	#define pio_write16be(val,port) outw(swab16(val),port)
	105	#define pio_write32be(val,port) outl(swab32(val),port)
	106	#endif
	107
	108	#ifndef mmio_write16be
	109	#define mmio_write16be(val,port) __raw_writew(be16_to_cpu(val),port)
	110	#define mmio_write32be(val,port) __raw_writel(be32_to_cpu(val),port)
	111	#endif
	112
1da177e4 LT	113	void fastcall iowrite8(u8 val, void __iomem *addr)
	114	{
	115	IO_COND(addr, outb(val,port), writeb(val, addr));
	116	}
	117	void fastcall iowrite16(u16 val, void __iomem *addr)
	118	{
	119	IO_COND(addr, outw(val,port), writew(val, addr));
	120	}
dae409a2 JB	121	void fastcall iowrite16be(u16 val, void __iomem *addr)
dae409a2 JB	122	{
34ba8a5c	123	IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
dae409a2	124	}
1da177e4 LT	125	void fastcall iowrite32(u32 val, void __iomem *addr)
	126	{
	127	IO_COND(addr, outl(val,port), writel(val, addr));
	128	}
dae409a2 JB	129	void fastcall iowrite32be(u32 val, void __iomem *addr)
dae409a2 JB	130	{
34ba8a5c	131	IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
dae409a2	132	}
1da177e4 LT	133	EXPORT_SYMBOL(iowrite8);
1da177e4 LT	134	EXPORT_SYMBOL(iowrite16);
dae409a2	135	EXPORT_SYMBOL(iowrite16be);
1da177e4	136	EXPORT_SYMBOL(iowrite32);
dae409a2	137	EXPORT_SYMBOL(iowrite32be);
1da177e4 LT	138
	139	/*
	140	* These are the "repeat MMIO read/write" functions.
	141	* Note the "__raw" accesses, since we don't want to
	142	* convert to CPU byte order. We write in "IO byte
	143	* order" (we also don't have IO barriers).
	144	*/
34ba8a5c	145	#ifndef mmio_insb
1da177e4 LT	146	static inline void mmio_insb(void __iomem addr, u8 dst, int count)
	147	{
	148	while (--count >= 0) {
	149	u8 data = __raw_readb(addr);
	150	*dst = data;
	151	dst++;
	152	}
	153	}
	154	static inline void mmio_insw(void __iomem addr, u16 dst, int count)
	155	{
	156	while (--count >= 0) {
	157	u16 data = __raw_readw(addr);
	158	*dst = data;
	159	dst++;
	160	}
	161	}
	162	static inline void mmio_insl(void __iomem addr, u32 dst, int count)
	163	{
	164	while (--count >= 0) {
	165	u32 data = __raw_readl(addr);
	166	*dst = data;
	167	dst++;
	168	}
	169	}
34ba8a5c	170	#endif
1da177e4	171
34ba8a5c	172	#ifndef mmio_outsb
1da177e4 LT	173	static inline void mmio_outsb(void __iomem addr, const u8 src, int count)
	174	{
	175	while (--count >= 0) {
	176	__raw_writeb(*src, addr);
	177	src++;
	178	}
	179	}
	180	static inline void mmio_outsw(void __iomem addr, const u16 src, int count)
	181	{
	182	while (--count >= 0) {
	183	__raw_writew(*src, addr);
	184	src++;
	185	}
	186	}
	187	static inline void mmio_outsl(void __iomem addr, const u32 src, int count)
	188	{
	189	while (--count >= 0) {
	190	__raw_writel(*src, addr);
	191	src++;
	192	}
	193	}
34ba8a5c	194	#endif
1da177e4 LT	195
	196	void fastcall ioread8_rep(void __iomem addr, void dst, unsigned long count)
	197	{
	198	IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
	199	}
	200	void fastcall ioread16_rep(void __iomem addr, void dst, unsigned long count)
	201	{
	202	IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
	203	}
	204	void fastcall ioread32_rep(void __iomem addr, void dst, unsigned long count)
	205	{
	206	IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
	207	}
	208	EXPORT_SYMBOL(ioread8_rep);
	209	EXPORT_SYMBOL(ioread16_rep);
	210	EXPORT_SYMBOL(ioread32_rep);
	211
	212	void fastcall iowrite8_rep(void __iomem addr, const void src, unsigned long count)
	213	{
	214	IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
	215	}
	216	void fastcall iowrite16_rep(void __iomem addr, const void src, unsigned long count)
	217	{
	218	IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
	219	}
	220	void fastcall iowrite32_rep(void __iomem addr, const void src, unsigned long count)
	221	{
	222	IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
	223	}
	224	EXPORT_SYMBOL(iowrite8_rep);
	225	EXPORT_SYMBOL(iowrite16_rep);
	226	EXPORT_SYMBOL(iowrite32_rep);
	227
	228	/* Create a virtual mapping cookie for an IO port range */
	229	void __iomem *ioport_map(unsigned long port, unsigned int nr)
	230	{
	231	if (port > PIO_MASK)
	232	return NULL;
	233	return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
	234	}
	235
	236	void ioport_unmap(void __iomem *addr)
	237	{
	238	/* Nothing to do */
	239	}
	240	EXPORT_SYMBOL(ioport_map);
	241	EXPORT_SYMBOL(ioport_unmap);
	242
5ca24814 REB	243	/**
	244	* pci_iomap - create a virtual mapping cookie for a PCI BAR
	245	* @dev: PCI device that owns the BAR
	246	* @bar: BAR number
	247	* @maxlen: length of the memory to map
	248	*
	249	* Using this function you will get a __iomem address to your device BAR.
	250	* You can access it using ioread() and iowrite(). These functions hide
	251	* the details if this is a MMIO or PIO address space and will just do what
	252	* you expect from them in the correct way.
	253	*
	254	* @maxlen specifies the maximum length to map. If you want to get access to
	255	* the complete BAR without checking for its length first, pass %0 here.
	256	* */
1da177e4 LT	257	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen)
	258	{
	259	unsigned long start = pci_resource_start(dev, bar);
	260	unsigned long len = pci_resource_len(dev, bar);
	261	unsigned long flags = pci_resource_flags(dev, bar);
	262
	263	if (!len \|\| !start)
	264	return NULL;
	265	if (maxlen && len > maxlen)
	266	len = maxlen;
	267	if (flags & IORESOURCE_IO)
	268	return ioport_map(start, len);
	269	if (flags & IORESOURCE_MEM) {
	270	if (flags & IORESOURCE_CACHEABLE)
	271	return ioremap(start, len);
	272	return ioremap_nocache(start, len);
	273	}
	274	/* What? */
	275	return NULL;
	276	}
	277
	278	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	279	{
	280	IO_COND(addr, /* nothing */, iounmap(addr));
	281	}
	282	EXPORT_SYMBOL(pci_iomap);
	283	EXPORT_SYMBOL(pci_iounmap);