[linux.git] / drivers / block / cciss.h

#ifndef CCISS_H
#define CCISS_H

#include <linux/genhd.h>
#include <linux/mutex.h>

#include "cciss_cmd.h"


#define NWD_SHIFT	4
#define MAX_PART	(1 << NWD_SHIFT)

#define IO_OK		0
#define IO_ERROR	1
#define IO_NEEDS_RETRY  3

#define VENDOR_LEN	8
#define MODEL_LEN	16
#define REV_LEN		4

struct ctlr_info;
typedef struct ctlr_info ctlr_info_t;

struct access_method {
	void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
	void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
	unsigned long (*fifo_full)(ctlr_info_t *h);
	bool (*intr_pending)(ctlr_info_t *h);
	unsigned long (*command_completed)(ctlr_info_t *h);
};
typedef struct _drive_info_struct
{
	unsigned char LunID[8];
	int 	usage_count;
	struct request_queue *queue;
	sector_t nr_blocks;
	int	block_size;
	int 	heads;
	int	sectors;
	int 	cylinders;
	int	raid_level; /* set to -1 to indicate that
			     * the drive is not in use/configured
			     */
	int	busy_configuring; /* This is set when a drive is being removed
				   * to prevent it from being opened or it's
				   * queue from being started.
				   */
	struct	device dev;
	__u8 serial_no[16]; /* from inquiry page 0x83,
			     * not necc. null terminated.
			     */
	char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
	char model[MODEL_LEN + 1];   /* SCSI model string */
	char rev[REV_LEN + 1];       /* SCSI revision string */
	char device_initialized;     /* indicates whether dev is initialized */
} drive_info_struct;

struct ctlr_info
{
	int	ctlr;
	char	devname[8];
	char    *product_name;
	char	firm_ver[4]; /* Firmware version */
	struct pci_dev *pdev;
	__u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
	CfgTable_struct __iomem *cfgtable;
	int	interrupts_enabled;
	int	major;
	int 	max_commands;
	int	commands_outstanding;
	int 	max_outstanding; /* Debug */ 
	int	num_luns;
	int 	highest_lun;
	int	usage_count;  /* number of opens all all minor devices */
	/* Need space for temp sg list
	 * number of scatter/gathers supported
	 * number of scatter/gathers in chained block
	 */
	struct	scatterlist **scatter_list;
	int	maxsgentries;
	int	chainsize;
	int	max_cmd_sgentries;
	SGDescriptor_struct **cmd_sg_list;

#	define PERF_MODE_INT	0
#	define DOORBELL_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[4];
	int	intr_mode;
	int 	cciss_max_sectors;
	BYTE	cciss_read;
	BYTE	cciss_write;
	BYTE	cciss_read_capacity;

	/* information about each logical volume */
	drive_info_struct *drv[CISS_MAX_LUN];

	struct access_method access;

	/* queue and queue Info */ 
	struct list_head reqQ;
	struct list_head cmpQ;
	unsigned int Qdepth;
	unsigned int maxQsinceinit;
	unsigned int maxSG;
	spinlock_t lock;

	/* pointers to command and error info pool */
	CommandList_struct 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle; 
	ErrorInfo_struct 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle; 
        unsigned long  		*cmd_pool_bits;
	int			nr_allocs;
	int			nr_frees; 
	int			busy_configuring;
	int			busy_initializing;
	int			busy_scanning;
	struct mutex		busy_shutting_down;

	/* This element holds the zero based queue number of the last
	 * queue to be started.  It is used for fairness.
	*/
	int			next_to_run;

	/* Disk structures we need to pass back */
	struct gendisk   *gendisk[CISS_MAX_LUN];
#ifdef CONFIG_CISS_SCSI_TAPE
	struct cciss_scsi_adapter_data_t *scsi_ctlr;
#endif
	unsigned char alive;
	struct list_head scan_list;
	struct completion scan_wait;
	struct device dev;
	/*
	 * Performant mode tables.
	 */
	u32 trans_support;
	u32 trans_offset;
	struct TransTable_struct *transtable;
	unsigned long transMethod;

	/*
	 * Performant mode completion buffer
	 */
	u64 *reply_pool;
	dma_addr_t reply_pool_dhandle;
	u64 *reply_pool_head;
	size_t reply_pool_size;
	unsigned char reply_pool_wraparound;
	u32 *blockFetchTable;
};

/*  Defining the diffent access_methods
 *
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff	
#define CCISS_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */
/* Perf. mode flags */
#define SA5_PERF_INTR_PENDING	0x04
#define SA5_PERF_INTR_OFF	0x05
#define SA5_OUTDB_STATUS_PERF_BIT	0x01
#define SA5_OUTDB_CLEAR_PERF_BIT	0x01
#define SA5_OUTDB_CLEAR         0xA0
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_STATUS        0x9C


#define  CISS_ERROR_BIT		0x02

#define CCISS_INTR_ON 	1 
#define CCISS_INTR_OFF	0


/* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  CCISS_BOARD_READY_ITERATIONS is derived
 * the above.
 */
#define CCISS_BOARD_READY_WAIT_SECS (120)
#define CCISS_BOARD_NOT_READY_WAIT_SECS (100)
#define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define CCISS_BOARD_READY_ITERATIONS \
	((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
		CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
#define CCISS_BOARD_NOT_READY_ITERATIONS \
	((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
		CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
#define CCISS_POST_RESET_PAUSE_MSECS (3000)
#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (4000)
#define CCISS_POST_RESET_NOOP_RETRIES (12)
#define CCISS_POST_RESET_NOOP_TIMEOUT_MSECS (10000)

/* 
	Send the command to the hardware 
*/
static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c) 
{
#ifdef CCISS_DEBUG
	printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
			h->ctlr, c->busaddr);
#endif /* CCISS_DEBUG */
         writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
	 h->commands_outstanding++;
	 if ( h->commands_outstanding > h->max_outstanding)
		h->max_outstanding = h->commands_outstanding;
}

/*  
 *  This card is the opposite of the other cards.  
 *   0 turns interrupts on... 
 *   0x08 turns them off... 
 */
static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
{
	if (val) 
	{ /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else /* Turn them off */
	{
		h->interrupts_enabled = 0;
        	writel( SA5_INTR_OFF, 
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}
/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x04 turns them off...
 */
static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
{
        if (val)
        { /* Turn interrupts on */
		h->interrupts_enabled = 1;
                writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
        } else /* Turn them off */
        {
		h->interrupts_enabled = 0;
                writel( SA5B_INTR_OFF,
                        h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
        }
}

/* Performant mode intr_mask */
static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
{
	if (val) { /* turn on interrupts */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else {
		h->interrupts_enabled = 0;
		writel(SA5_PERF_INTR_OFF,
				h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

/*
 *  Returns true if fifo is full.  
 * 
 */ 
static unsigned long SA5_fifo_full(ctlr_info_t *h)
{
	if( h->commands_outstanding >= h->max_commands)
		return(1);
	else 
		return(0);

}
/* 
 *   returns value read from hardware. 
 *     returns FIFO_EMPTY if there is nothing to read 
 */ 
static unsigned long SA5_completed(ctlr_info_t *h)
{
	unsigned long register_value 
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	if(register_value != FIFO_EMPTY)
	{
		h->commands_outstanding--;
#ifdef CCISS_DEBUG
		printk("cciss:  Read %lx back from board\n", register_value);
#endif /* CCISS_DEBUG */ 
	} 
#ifdef CCISS_DEBUG
	else
	{
		printk("cciss:  FIFO Empty read\n");
	}
#endif 
	return ( register_value); 

}

/* Performant mode command completed */
static unsigned long SA5_performant_completed(ctlr_info_t *h)
{
	unsigned long register_value = FIFO_EMPTY;

	/* flush the controller write of the reply queue by reading
	 * outbound doorbell status register.
	 */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	/* msi auto clears the interrupt pending bit. */
	if (!(h->pdev->msi_enabled || h->pdev->msix_enabled)) {
		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
		/* Do a read in order to flush the write to the controller
		 * (as per spec.)
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	}

	if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
		register_value = *(h->reply_pool_head);
		(h->reply_pool_head)++;
		h->commands_outstanding--;
	} else {
		register_value = FIFO_EMPTY;
	}
	/* Check for wraparound */
	if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
		h->reply_pool_head = h->reply_pool;
		h->reply_pool_wraparound ^= 1;
	}

	return register_value;
}
/*
 *	Returns true if an interrupt is pending.. 
 */
static bool SA5_intr_pending(ctlr_info_t *h)
{
	unsigned long register_value  = 
		readl(h->vaddr + SA5_INTR_STATUS);
#ifdef CCISS_DEBUG
	printk("cciss: intr_pending %lx\n", register_value);
#endif  /* CCISS_DEBUG */
	if( register_value &  SA5_INTR_PENDING) 
		return  1;	
	return 0 ;
}

/*
 *      Returns true if an interrupt is pending..
 */
static bool SA5B_intr_pending(ctlr_info_t *h)
{
        unsigned long register_value  =
                readl(h->vaddr + SA5_INTR_STATUS);
#ifdef CCISS_DEBUG
        printk("cciss: intr_pending %lx\n", register_value);
#endif  /* CCISS_DEBUG */
        if( register_value &  SA5B_INTR_PENDING)
                return  1;
        return 0 ;
}

static bool SA5_performant_intr_pending(ctlr_info_t *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	if (!register_value)
		return false;

	if (h->pdev->msi_enabled || h->pdev->msix_enabled)
		return true;

	/* Read outbound doorbell to flush */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
}

static struct access_method SA5_access = {
	.submit_command = SA5_submit_command,
	.set_intr_mask = SA5_intr_mask,
	.fifo_full = SA5_fifo_full,
	.intr_pending = SA5_intr_pending,
	.command_completed = SA5_completed,
};

static struct access_method SA5B_access = {
	.submit_command = SA5_submit_command,
	.set_intr_mask = SA5B_intr_mask,
	.fifo_full = SA5_fifo_full,
	.intr_pending = SA5B_intr_pending,
	.command_completed = SA5_completed,
};

static struct access_method SA5_performant_access = {
	.submit_command = SA5_submit_command,
	.set_intr_mask = SA5_performant_intr_mask,
	.fifo_full = SA5_fifo_full,
	.intr_pending = SA5_performant_intr_pending,
	.command_completed = SA5_performant_completed,
};

struct board_type {
	__u32	board_id;
	char	*product_name;
	struct access_method *access;
	int nr_cmds; /* Max cmds this kind of ctlr can handle. */
};

#endif /* CCISS_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef CCISS_H
	2	#define CCISS_H
	3
	4	#include <linux/genhd.h>
b368c9dd	5	#include <linux/mutex.h>
1da177e4 LT	6
	7	#include "cciss_cmd.h"
	8
	9
1da177e4 LT	10	#define NWD_SHIFT 4
	11	#define MAX_PART (1 << NWD_SHIFT)
	12
	13	#define IO_OK 0
	14	#define IO_ERROR 1
789a424a	15	#define IO_NEEDS_RETRY 3
1da177e4	16
7fe06326 AP	17	#define VENDOR_LEN 8
	18	#define MODEL_LEN 16
	19	#define REV_LEN 4
	20
1da177e4 LT	21	struct ctlr_info;
	22	typedef struct ctlr_info ctlr_info_t;
	23
	24	struct access_method {
	25	void (submit_command)(ctlr_info_t h, CommandList_struct *c);
	26	void (set_intr_mask)(ctlr_info_t h, unsigned long val);
	27	unsigned long (fifo_full)(ctlr_info_t h);
1d141441	28	bool (intr_pending)(ctlr_info_t h);
1da177e4 LT	29	unsigned long (command_completed)(ctlr_info_t h);
	30	};
	31	typedef struct _drive_info_struct
	32	{
39ccf9a6	33	unsigned char LunID[8];
1da177e4	34	int usage_count;
ad2b9312	35	struct request_queue *queue;
1da177e4 LT	36	sector_t nr_blocks;
	37	int block_size;
	38	int heads;
	39	int sectors;
	40	int cylinders;
ddd47442 MM	41	int raid_level; /* set to -1 to indicate that
ddd47442 MM	42	* the drive is not in use/configured
7fe06326 AP	43	*/
	44	int busy_configuring; /* This is set when a drive is being removed
	45	* to prevent it from being opened or it's
	46	* queue from being started.
	47	*/
9cef0d2f	48	struct device dev;
7fe06326 AP	49	__u8 serial_no[16]; /* from inquiry page 0x83,
	50	* not necc. null terminated.
	51	*/
	52	char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
	53	char model[MODEL_LEN + 1]; /* SCSI model string */
	54	char rev[REV_LEN + 1]; /* SCSI revision string */
9cef0d2f	55	char device_initialized; /* indicates whether dev is initialized */
1da177e4 LT	56	} drive_info_struct;
1da177e4 LT	57
5c07a311	58	struct ctlr_info
1da177e4 LT	59	{
	60	int ctlr;
	61	char devname[8];
	62	char *product_name;
b028461d	63	char firm_ver[4]; /* Firmware version */
1da177e4 LT	64	struct pci_dev *pdev;
	65	__u32 board_id;
	66	void __iomem *vaddr;
	67	unsigned long paddr;
f880632f	68	int nr_cmds; /* Number of commands allowed on this controller */
1da177e4	69	CfgTable_struct __iomem *cfgtable;
1da177e4 LT	70	int interrupts_enabled;
	71	int major;
	72	int max_commands;
	73	int commands_outstanding;
	74	int max_outstanding; /* Debug */
	75	int num_luns;
	76	int highest_lun;
	77	int usage_count; /* number of opens all all minor devices */
5c07a311 DB	78	/* Need space for temp sg list
	79	* number of scatter/gathers supported
	80	* number of scatter/gathers in chained block
	81	*/
	82	struct scatterlist **scatter_list;
	83	int maxsgentries;
	84	int chainsize;
	85	int max_cmd_sgentries;
dccc9b56	86	SGDescriptor_struct **cmd_sg_list;
5c07a311	87
5e216153 MM	88	# define PERF_MODE_INT 0
5e216153 MM	89	# define DOORBELL_INT 1
fb86a35b MM	90	# define SIMPLE_MODE_INT 2
	91	# define MEMQ_MODE_INT 3
	92	unsigned int intr[4];
13049537	93	int intr_mode;
92c4231a	94	int cciss_max_sectors;
00988a35 MMOD	95	BYTE cciss_read;
	96	BYTE cciss_write;
	97	BYTE cciss_read_capacity;
1da177e4	98
b028461d	99	/* information about each logical volume */
9cef0d2f	100	drive_info_struct *drv[CISS_MAX_LUN];
1da177e4 LT	101
	102	struct access_method access;
	103
	104	/* queue and queue Info */
e6e1ee93 JA	105	struct list_head reqQ;
e6e1ee93 JA	106	struct list_head cmpQ;
1da177e4 LT	107	unsigned int Qdepth;
	108	unsigned int maxQsinceinit;
	109	unsigned int maxSG;
	110	spinlock_t lock;
1da177e4	111
b028461d	112	/* pointers to command and error info pool */
1da177e4 LT	113	CommandList_struct *cmd_pool;
	114	dma_addr_t cmd_pool_dhandle;
	115	ErrorInfo_struct *errinfo_pool;
	116	dma_addr_t errinfo_pool_dhandle;
	117	unsigned long *cmd_pool_bits;
	118	int nr_allocs;
	119	int nr_frees;
	120	int busy_configuring;
1f8ef380	121	int busy_initializing;
b368c9dd AP	122	int busy_scanning;
b368c9dd AP	123	struct mutex busy_shutting_down;
1da177e4 LT	124
	125	/* This element holds the zero based queue number of the last
	126	* queue to be started. It is used for fairness.
	127	*/
	128	int next_to_run;
	129
b028461d	130	/* Disk structures we need to pass back */
799202cb	131	struct gendisk *gendisk[CISS_MAX_LUN];
1da177e4	132	#ifdef CONFIG_CISS_SCSI_TAPE
aad9fb6f	133	struct cciss_scsi_adapter_data_t *scsi_ctlr;
1da177e4	134	#endif
33079b21	135	unsigned char alive;
b368c9dd AP	136	struct list_head scan_list;
b368c9dd AP	137	struct completion scan_wait;
7fe06326	138	struct device dev;
5e216153 MM	139	/*
	140	* Performant mode tables.
	141	*/
	142	u32 trans_support;
	143	u32 trans_offset;
	144	struct TransTable_struct *transtable;
	145	unsigned long transMethod;
	146
	147	/*
	148	* Performant mode completion buffer
	149	*/
	150	u64 *reply_pool;
	151	dma_addr_t reply_pool_dhandle;
	152	u64 *reply_pool_head;
	153	size_t reply_pool_size;
	154	unsigned char reply_pool_wraparound;
	155	u32 *blockFetchTable;
1da177e4 LT	156	};
1da177e4 LT	157
5e216153 MM	158	/* Defining the diffent access_methods
5e216153 MM	159	*
1da177e4 LT	160	* Memory mapped FIFO interface (SMART 53xx cards)
	161	*/
	162	#define SA5_DOORBELL 0x20
	163	#define SA5_REQUEST_PORT_OFFSET 0x40
	164	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
	165	#define SA5_REPLY_PORT_OFFSET 0x44
	166	#define SA5_INTR_STATUS 0x30
	167	#define SA5_SCRATCHPAD_OFFSET 0xB0
	168
	169	#define SA5_CTCFG_OFFSET 0xB4
	170	#define SA5_CTMEM_OFFSET 0xB8
	171
	172	#define SA5_INTR_OFF 0x08
	173	#define SA5B_INTR_OFF 0x04
	174	#define SA5_INTR_PENDING 0x08
	175	#define SA5B_INTR_PENDING 0x04
	176	#define FIFO_EMPTY 0xffffffff
	177	#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
5e216153 MM	178	/* Perf. mode flags */
	179	#define SA5_PERF_INTR_PENDING 0x04
	180	#define SA5_PERF_INTR_OFF 0x05
	181	#define SA5_OUTDB_STATUS_PERF_BIT 0x01
	182	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	183	#define SA5_OUTDB_CLEAR 0xA0
	184	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	185	#define SA5_OUTDB_STATUS 0x9C
	186
1da177e4 LT	187
	188	#define CISS_ERROR_BIT 0x02
	189
	190	#define CCISS_INTR_ON 1
	191	#define CCISS_INTR_OFF 0
e99ba136 SC	192
	193
	194	/* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board
	195	* to become ready, in seconds, before giving up on it.
	196	* CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
	197	* between polling the board to see if it is ready, in
	198	* milliseconds. CCISS_BOARD_READY_ITERATIONS is derived
	199	* the above.
	200	*/
	201	#define CCISS_BOARD_READY_WAIT_SECS (120)
19adbb92	202	#define CCISS_BOARD_NOT_READY_WAIT_SECS (100)
e99ba136 SC	203	#define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
	204	#define CCISS_BOARD_READY_ITERATIONS \
	205	((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
	206	CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
afa842fa SC	207	#define CCISS_BOARD_NOT_READY_ITERATIONS \
	208	((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
	209	CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
83123cb1	210	#define CCISS_POST_RESET_PAUSE_MSECS (3000)
3e28601f	211	#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (4000)
83123cb1	212	#define CCISS_POST_RESET_NOOP_RETRIES (12)
3e28601f	213	#define CCISS_POST_RESET_NOOP_TIMEOUT_MSECS (10000)
e99ba136	214
1da177e4 LT	215	/*
	216	Send the command to the hardware
	217	*/
	218	static void SA5_submit_command( ctlr_info_t h, CommandList_struct c)
	219	{
	220	#ifdef CCISS_DEBUG
5e216153 MM	221	printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
	222	h->ctlr, c->busaddr);
	223	#endif /* CCISS_DEBUG */
1da177e4	224	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
07d0c38e	225	readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
1da177e4 LT	226	h->commands_outstanding++;
	227	if ( h->commands_outstanding > h->max_outstanding)
	228	h->max_outstanding = h->commands_outstanding;
	229	}
	230
	231	/*
	232	* This card is the opposite of the other cards.
	233	* 0 turns interrupts on...
	234	* 0x08 turns them off...
	235	*/
	236	static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
	237	{
	238	if (val)
	239	{ /* Turn interrupts on */
	240	h->interrupts_enabled = 1;
	241	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
9bd3c204	242	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
1da177e4 LT	243	} else /* Turn them off */
	244	{
	245	h->interrupts_enabled = 0;
	246	writel( SA5_INTR_OFF,
	247	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
9bd3c204	248	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
1da177e4 LT	249	}
	250	}
	251	/*
	252	* This card is the opposite of the other cards.
	253	* 0 turns interrupts on...
	254	* 0x04 turns them off...
	255	*/
	256	static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
	257	{
	258	if (val)
	259	{ /* Turn interrupts on */
	260	h->interrupts_enabled = 1;
	261	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
9bd3c204	262	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
1da177e4 LT	263	} else /* Turn them off */
	264	{
	265	h->interrupts_enabled = 0;
	266	writel( SA5B_INTR_OFF,
	267	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
9bd3c204	268	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
1da177e4 LT	269	}
1da177e4 LT	270	}
5e216153 MM	271
	272	/* Performant mode intr_mask */
	273	static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
	274	{
	275	if (val) { /* turn on interrupts */
	276	h->interrupts_enabled = 1;
	277	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
9bd3c204	278	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
5e216153 MM	279	} else {
	280	h->interrupts_enabled = 0;
	281	writel(SA5_PERF_INTR_OFF,
	282	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
9bd3c204	283	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
5e216153 MM	284	}
	285	}
	286
1da177e4 LT	287	/*
	288	* Returns true if fifo is full.
	289	*
	290	*/
	291	static unsigned long SA5_fifo_full(ctlr_info_t *h)
	292	{
	293	if( h->commands_outstanding >= h->max_commands)
	294	return(1);
	295	else
	296	return(0);
	297
	298	}
	299	/*
	300	* returns value read from hardware.
	301	* returns FIFO_EMPTY if there is nothing to read
	302	*/
	303	static unsigned long SA5_completed(ctlr_info_t *h)
	304	{
	305	unsigned long register_value
	306	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	307	if(register_value != FIFO_EMPTY)
	308	{
	309	h->commands_outstanding--;
	310	#ifdef CCISS_DEBUG
	311	printk("cciss: Read %lx back from board\n", register_value);
	312	#endif /* CCISS_DEBUG */
	313	}
	314	#ifdef CCISS_DEBUG
	315	else
	316	{
	317	printk("cciss: FIFO Empty read\n");
	318	}
	319	#endif
	320	return ( register_value);
	321
	322	}
5e216153 MM	323
	324	/* Performant mode command completed */
	325	static unsigned long SA5_performant_completed(ctlr_info_t *h)
	326	{
	327	unsigned long register_value = FIFO_EMPTY;
	328
	329	/* flush the controller write of the reply queue by reading
	330	* outbound doorbell status register.
	331	*/
	332	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	333	/* msi auto clears the interrupt pending bit. */
c5c9b26e	334	if (!(h->pdev->msi_enabled \|\| h->pdev->msix_enabled)) {
5e216153 MM	335	writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
	336	/* Do a read in order to flush the write to the controller
	337	* (as per spec.)
	338	*/
	339	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	340	}
	341
	342	if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
	343	register_value = *(h->reply_pool_head);
	344	(h->reply_pool_head)++;
	345	h->commands_outstanding--;
	346	} else {
	347	register_value = FIFO_EMPTY;
	348	}
	349	/* Check for wraparound */
	350	if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
	351	h->reply_pool_head = h->reply_pool;
	352	h->reply_pool_wraparound ^= 1;
	353	}
	354
	355	return register_value;
	356	}
1da177e4 LT	357	/*
	358	* Returns true if an interrupt is pending..
	359	*/
1d141441	360	static bool SA5_intr_pending(ctlr_info_t *h)
1da177e4 LT	361	{
	362	unsigned long register_value =
	363	readl(h->vaddr + SA5_INTR_STATUS);
	364	#ifdef CCISS_DEBUG
	365	printk("cciss: intr_pending %lx\n", register_value);
	366	#endif /* CCISS_DEBUG */
	367	if( register_value & SA5_INTR_PENDING)
	368	return 1;
	369	return 0 ;
	370	}
	371
	372	/*
	373	* Returns true if an interrupt is pending..
	374	*/
1d141441	375	static bool SA5B_intr_pending(ctlr_info_t *h)
1da177e4 LT	376	{
	377	unsigned long register_value =
	378	readl(h->vaddr + SA5_INTR_STATUS);
	379	#ifdef CCISS_DEBUG
	380	printk("cciss: intr_pending %lx\n", register_value);
	381	#endif /* CCISS_DEBUG */
	382	if( register_value & SA5B_INTR_PENDING)
	383	return 1;
	384	return 0 ;
	385	}
	386
5e216153 MM	387	static bool SA5_performant_intr_pending(ctlr_info_t *h)
	388	{
	389	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	390
	391	if (!register_value)
	392	return false;
	393
c5c9b26e	394	if (h->pdev->msi_enabled \|\| h->pdev->msix_enabled)
5e216153 MM	395	return true;
	396
	397	/* Read outbound doorbell to flush */
	398	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	399	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
	400	}
1da177e4 LT	401
1da177e4 LT	402	static struct access_method SA5_access = {
5f5fca6d KC	403	.submit_command = SA5_submit_command,
	404	.set_intr_mask = SA5_intr_mask,
	405	.fifo_full = SA5_fifo_full,
	406	.intr_pending = SA5_intr_pending,
	407	.command_completed = SA5_completed,
1da177e4 LT	408	};
	409
	410	static struct access_method SA5B_access = {
5f5fca6d KC	411	.submit_command = SA5_submit_command,
	412	.set_intr_mask = SA5B_intr_mask,
	413	.fifo_full = SA5_fifo_full,
	414	.intr_pending = SA5B_intr_pending,
	415	.command_completed = SA5_completed,
1da177e4 LT	416	};
1da177e4 LT	417
5e216153	418	static struct access_method SA5_performant_access = {
5f5fca6d KC	419	.submit_command = SA5_submit_command,
	420	.set_intr_mask = SA5_performant_intr_mask,
	421	.fifo_full = SA5_fifo_full,
	422	.intr_pending = SA5_performant_intr_pending,
	423	.command_completed = SA5_performant_completed,
5e216153 MM	424	};
5e216153 MM	425
1da177e4 LT	426	struct board_type {
	427	__u32 board_id;
	428	char *product_name;
	429	struct access_method *access;
f880632f	430	int nr_cmds; /* Max cmds this kind of ctlr can handle. */
1da177e4 LT	431	};
1da177e4 LT	432
1da177e4	433	#endif /* CCISS_H */