[linux.git] / drivers / spi / spi-fsl-espi.c

/*
 * Freescale eSPI controller driver.
 *
 * Copyright 2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_spi.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <sysdev/fsl_soc.h>

#include "spi-fsl-lib.h"

/* eSPI Controller registers */
struct fsl_espi_reg {
	__be32 mode;		/* 0x000 - eSPI mode register */
	__be32 event;		/* 0x004 - eSPI event register */
	__be32 mask;		/* 0x008 - eSPI mask register */
	__be32 command;		/* 0x00c - eSPI command register */
	__be32 transmit;	/* 0x010 - eSPI transmit FIFO access register*/
	__be32 receive;		/* 0x014 - eSPI receive FIFO access register*/
	u8 res[8];		/* 0x018 - 0x01c reserved */
	__be32 csmode[4];	/* 0x020 - 0x02c eSPI cs mode register */
};

struct fsl_espi_transfer {
	const void *tx_buf;
	void *rx_buf;
	unsigned len;
	unsigned n_tx;
	unsigned n_rx;
	unsigned actual_length;
	int status;
};

/* eSPI Controller mode register definitions */
#define SPMODE_ENABLE		(1 << 31)
#define SPMODE_LOOP		(1 << 30)
#define SPMODE_TXTHR(x)		((x) << 8)
#define SPMODE_RXTHR(x)		((x) << 0)

/* eSPI Controller CS mode register definitions */
#define CSMODE_CI_INACTIVEHIGH	(1 << 31)
#define CSMODE_CP_BEGIN_EDGECLK	(1 << 30)
#define CSMODE_REV		(1 << 29)
#define CSMODE_DIV16		(1 << 28)
#define CSMODE_PM(x)		((x) << 24)
#define CSMODE_POL_1		(1 << 20)
#define CSMODE_LEN(x)		((x) << 16)
#define CSMODE_BEF(x)		((x) << 12)
#define CSMODE_AFT(x)		((x) << 8)
#define CSMODE_CG(x)		((x) << 3)

/* Default mode/csmode for eSPI controller */
#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
		| CSMODE_AFT(0) | CSMODE_CG(1))

/* SPIE register values */
#define	SPIE_NE		0x00000200	/* Not empty */
#define	SPIE_NF		0x00000100	/* Not full */

/* SPIM register values */
#define	SPIM_NE		0x00000200	/* Not empty */
#define	SPIM_NF		0x00000100	/* Not full */
#define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)
#define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)

/* SPCOM register values */
#define SPCOM_CS(x)		((x) << 30)
#define SPCOM_TRANLEN(x)	((x) << 0)
#define	SPCOM_TRANLEN_MAX	0xFFFF	/* Max transaction length */

static void fsl_espi_change_mode(struct spi_device *spi)
{
	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
	struct spi_mpc8xxx_cs *cs = spi->controller_state;
	struct fsl_espi_reg *reg_base = mspi->reg_base;
	__be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
	__be32 __iomem *espi_mode = &reg_base->mode;
	u32 tmp;
	unsigned long flags;

	/* Turn off IRQs locally to minimize time that SPI is disabled. */
	local_irq_save(flags);

	/* Turn off SPI unit prior changing mode */
	tmp = mpc8xxx_spi_read_reg(espi_mode);
	mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
	mpc8xxx_spi_write_reg(mode, cs->hw_mode);
	mpc8xxx_spi_write_reg(espi_mode, tmp);

	local_irq_restore(flags);
}

static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
{
	u32 data;
	u16 data_h;
	u16 data_l;
	const u32 *tx = mpc8xxx_spi->tx;

	if (!tx)
		return 0;

	data = *tx++ << mpc8xxx_spi->tx_shift;
	data_l = data & 0xffff;
	data_h = (data >> 16) & 0xffff;
	swab16s(&data_l);
	swab16s(&data_h);
	data = data_h | data_l;

	mpc8xxx_spi->tx = tx;
	return data;
}

static int fsl_espi_setup_transfer(struct spi_device *spi,
					struct spi_transfer *t)
{
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
	int bits_per_word = 0;
	u8 pm;
	u32 hz = 0;
	struct spi_mpc8xxx_cs *cs = spi->controller_state;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/* Make sure its a bit width we support [4..16] */
	if ((bits_per_word < 4) || (bits_per_word > 16))
		return -EINVAL;

	if (!hz)
		hz = spi->max_speed_hz;

	cs->rx_shift = 0;
	cs->tx_shift = 0;
	cs->get_rx = mpc8xxx_spi_rx_buf_u32;
	cs->get_tx = mpc8xxx_spi_tx_buf_u32;
	if (bits_per_word <= 8) {
		cs->rx_shift = 8 - bits_per_word;
	} else if (bits_per_word <= 16) {
		cs->rx_shift = 16 - bits_per_word;
		if (spi->mode & SPI_LSB_FIRST)
			cs->get_tx = fsl_espi_tx_buf_lsb;
	} else {
		return -EINVAL;
	}

	mpc8xxx_spi->rx_shift = cs->rx_shift;
	mpc8xxx_spi->tx_shift = cs->tx_shift;
	mpc8xxx_spi->get_rx = cs->get_rx;
	mpc8xxx_spi->get_tx = cs->get_tx;

	bits_per_word = bits_per_word - 1;

	/* mask out bits we are going to set */
	cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));

	cs->hw_mode |= CSMODE_LEN(bits_per_word);

	if ((mpc8xxx_spi->spibrg / hz) > 64) {
		cs->hw_mode |= CSMODE_DIV16;
		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;

		WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
			  "Will use %d Hz instead.\n", dev_name(&spi->dev),
			  hz, mpc8xxx_spi->spibrg / 1024);
		if (pm > 16)
			pm = 16;
	} else {
		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
	}
	if (pm)
		pm--;

	cs->hw_mode |= CSMODE_PM(pm);

	fsl_espi_change_mode(spi);
	return 0;
}

static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
		unsigned int len)
{
	u32 word;
	struct fsl_espi_reg *reg_base = mspi->reg_base;

	mspi->count = len;

	/* enable rx ints */
	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);

	/* transmit word */
	word = mspi->get_tx(mspi);
	mpc8xxx_spi_write_reg(&reg_base->transmit, word);

	return 0;
}

static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
	struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
	unsigned int len = t->len;
	u8 bits_per_word;
	int ret;

	bits_per_word = spi->bits_per_word;
	if (t->bits_per_word)
		bits_per_word = t->bits_per_word;

	mpc8xxx_spi->len = t->len;
	len = roundup(len, 4) / 4;

	mpc8xxx_spi->tx = t->tx_buf;
	mpc8xxx_spi->rx = t->rx_buf;

	INIT_COMPLETION(mpc8xxx_spi->done);

	/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
	if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
		dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
				" beyond the SPCOM[TRANLEN] field\n", t->len);
		return -EINVAL;
	}
	mpc8xxx_spi_write_reg(&reg_base->command,
		(SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));

	ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
	if (ret)
		return ret;

	wait_for_completion(&mpc8xxx_spi->done);

	/* disable rx ints */
	mpc8xxx_spi_write_reg(&reg_base->mask, 0);

	return mpc8xxx_spi->count;
}

static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
{
	if (cmd) {
		cmd[1] = (u8)(addr >> 16);
		cmd[2] = (u8)(addr >> 8);
		cmd[3] = (u8)(addr >> 0);
	}
}

static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
{
	if (cmd)
		return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;

	return 0;
}

static void fsl_espi_do_trans(struct spi_message *m,
				struct fsl_espi_transfer *tr)
{
	struct spi_device *spi = m->spi;
	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
	struct fsl_espi_transfer *espi_trans = tr;
	struct spi_message message;
	struct spi_transfer *t, *first, trans;
	int status = 0;

	spi_message_init(&message);
	memset(&trans, 0, sizeof(trans));

	first = list_first_entry(&m->transfers, struct spi_transfer,
			transfer_list);
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if ((first->bits_per_word != t->bits_per_word) ||
			(first->speed_hz != t->speed_hz)) {
			espi_trans->status = -EINVAL;
			dev_err(mspi->dev, "bits_per_word/speed_hz should be"
					" same for the same SPI transfer\n");
			return;
		}

		trans.speed_hz = t->speed_hz;
		trans.bits_per_word = t->bits_per_word;
		trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
	}

	trans.len = espi_trans->len;
	trans.tx_buf = espi_trans->tx_buf;
	trans.rx_buf = espi_trans->rx_buf;
	spi_message_add_tail(&trans, &message);

	list_for_each_entry(t, &message.transfers, transfer_list) {
		if (t->bits_per_word || t->speed_hz) {
			status = -EINVAL;

			status = fsl_espi_setup_transfer(spi, t);
			if (status < 0)
				break;
		}

		if (t->len)
			status = fsl_espi_bufs(spi, t);

		if (status) {
			status = -EMSGSIZE;
			break;
		}

		if (t->delay_usecs)
			udelay(t->delay_usecs);
	}

	espi_trans->status = status;
	fsl_espi_setup_transfer(spi, NULL);
}

static void fsl_espi_cmd_trans(struct spi_message *m,
				struct fsl_espi_transfer *trans, u8 *rx_buff)
{
	struct spi_transfer *t;
	u8 *local_buf;
	int i = 0;
	struct fsl_espi_transfer *espi_trans = trans;

	local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
	if (!local_buf) {
		espi_trans->status = -ENOMEM;
		return;
	}

	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->tx_buf) {
			memcpy(local_buf + i, t->tx_buf, t->len);
			i += t->len;
		}
	}

	espi_trans->tx_buf = local_buf;
	espi_trans->rx_buf = local_buf + espi_trans->n_tx;
	fsl_espi_do_trans(m, espi_trans);

	espi_trans->actual_length = espi_trans->len;
	kfree(local_buf);
}

static void fsl_espi_rw_trans(struct spi_message *m,
				struct fsl_espi_transfer *trans, u8 *rx_buff)
{
	struct fsl_espi_transfer *espi_trans = trans;
	unsigned int n_tx = espi_trans->n_tx;
	unsigned int n_rx = espi_trans->n_rx;
	struct spi_transfer *t;
	u8 *local_buf;
	u8 *rx_buf = rx_buff;
	unsigned int trans_len;
	unsigned int addr;
	int i, pos, loop;

	local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
	if (!local_buf) {
		espi_trans->status = -ENOMEM;
		return;
	}

	for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
		trans_len = n_rx - pos;
		if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
			trans_len = SPCOM_TRANLEN_MAX - n_tx;

		i = 0;
		list_for_each_entry(t, &m->transfers, transfer_list) {
			if (t->tx_buf) {
				memcpy(local_buf + i, t->tx_buf, t->len);
				i += t->len;
			}
		}

		if (pos > 0) {
			addr = fsl_espi_cmd2addr(local_buf);
			addr += pos;
			fsl_espi_addr2cmd(addr, local_buf);
		}

		espi_trans->n_tx = n_tx;
		espi_trans->n_rx = trans_len;
		espi_trans->len = trans_len + n_tx;
		espi_trans->tx_buf = local_buf;
		espi_trans->rx_buf = local_buf + n_tx;
		fsl_espi_do_trans(m, espi_trans);

		memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);

		if (loop > 0)
			espi_trans->actual_length += espi_trans->len - n_tx;
		else
			espi_trans->actual_length += espi_trans->len;
	}

	kfree(local_buf);
}

static void fsl_espi_do_one_msg(struct spi_message *m)
{
	struct spi_transfer *t;
	u8 *rx_buf = NULL;
	unsigned int n_tx = 0;
	unsigned int n_rx = 0;
	struct fsl_espi_transfer espi_trans;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->tx_buf)
			n_tx += t->len;
		if (t->rx_buf) {
			n_rx += t->len;
			rx_buf = t->rx_buf;
		}
	}

	espi_trans.n_tx = n_tx;
	espi_trans.n_rx = n_rx;
	espi_trans.len = n_tx + n_rx;
	espi_trans.actual_length = 0;
	espi_trans.status = 0;

	if (!rx_buf)
		fsl_espi_cmd_trans(m, &espi_trans, NULL);
	else
		fsl_espi_rw_trans(m, &espi_trans, rx_buf);

	m->actual_length = espi_trans.actual_length;
	m->status = espi_trans.status;
	m->complete(m->context);
}

static int fsl_espi_setup(struct spi_device *spi)
{
	struct mpc8xxx_spi *mpc8xxx_spi;
	struct fsl_espi_reg *reg_base;
	int retval;
	u32 hw_mode;
	u32 loop_mode;
	struct spi_mpc8xxx_cs *cs = spi->controller_state;

	if (!spi->max_speed_hz)
		return -EINVAL;

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	mpc8xxx_spi = spi_master_get_devdata(spi->master);
	reg_base = mpc8xxx_spi->reg_base;

	hw_mode = cs->hw_mode; /* Save original settings */
	cs->hw_mode = mpc8xxx_spi_read_reg(
			&reg_base->csmode[spi->chip_select]);
	/* mask out bits we are going to set */
	cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
			 | CSMODE_REV);

	if (spi->mode & SPI_CPHA)
		cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
	if (spi->mode & SPI_CPOL)
		cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
	if (!(spi->mode & SPI_LSB_FIRST))
		cs->hw_mode |= CSMODE_REV;

	/* Handle the loop mode */
	loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
	loop_mode &= ~SPMODE_LOOP;
	if (spi->mode & SPI_LOOP)
		loop_mode |= SPMODE_LOOP;
	mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);

	retval = fsl_espi_setup_transfer(spi, NULL);
	if (retval < 0) {
		cs->hw_mode = hw_mode; /* Restore settings */
		return retval;
	}
	return 0;
}

void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
{
	struct fsl_espi_reg *reg_base = mspi->reg_base;

	/* We need handle RX first */
	if (events & SPIE_NE) {
		u32 rx_data, tmp;
		u8 rx_data_8;

		/* Spin until RX is done */
		while (SPIE_RXCNT(events) < min(4, mspi->len)) {
			cpu_relax();
			events = mpc8xxx_spi_read_reg(&reg_base->event);
		}

		if (mspi->len >= 4) {
			rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
		} else {
			tmp = mspi->len;
			rx_data = 0;
			while (tmp--) {
				rx_data_8 = in_8((u8 *)&reg_base->receive);
				rx_data |= (rx_data_8 << (tmp * 8));
			}

			rx_data <<= (4 - mspi->len) * 8;
		}

		mspi->len -= 4;

		if (mspi->rx)
			mspi->get_rx(rx_data, mspi);
	}

	if (!(events & SPIE_NF)) {
		int ret;

		/* spin until TX is done */
		ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
				&reg_base->event)) & SPIE_NF) == 0, 1000, 0);
		if (!ret) {
			dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
			return;
		}
	}

	/* Clear the events */
	mpc8xxx_spi_write_reg(&reg_base->event, events);

	mspi->count -= 1;
	if (mspi->count) {
		u32 word = mspi->get_tx(mspi);

		mpc8xxx_spi_write_reg(&reg_base->transmit, word);
	} else {
		complete(&mspi->done);
	}
}

static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
{
	struct mpc8xxx_spi *mspi = context_data;
	struct fsl_espi_reg *reg_base = mspi->reg_base;
	irqreturn_t ret = IRQ_NONE;
	u32 events;

	/* Get interrupt events(tx/rx) */
	events = mpc8xxx_spi_read_reg(&reg_base->event);
	if (events)
		ret = IRQ_HANDLED;

	dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);

	fsl_espi_cpu_irq(mspi, events);

	return ret;
}

static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
{
	iounmap(mspi->reg_base);
}

static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
		struct resource *mem, unsigned int irq)
{
	struct fsl_spi_platform_data *pdata = dev->platform_data;
	struct spi_master *master;
	struct mpc8xxx_spi *mpc8xxx_spi;
	struct fsl_espi_reg *reg_base;
	u32 regval;
	int i, ret = 0;

	master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
	if (!master) {
		ret = -ENOMEM;
		goto err;
	}

	dev_set_drvdata(dev, master);

	ret = mpc8xxx_spi_probe(dev, mem, irq);
	if (ret)
		goto err_probe;

	master->setup = fsl_espi_setup;

	mpc8xxx_spi = spi_master_get_devdata(master);
	mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
	mpc8xxx_spi->spi_remove = fsl_espi_remove;

	mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
	if (!mpc8xxx_spi->reg_base) {
		ret = -ENOMEM;
		goto err_probe;
	}

	reg_base = mpc8xxx_spi->reg_base;

	/* Register for SPI Interrupt */
	ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
			  0, "fsl_espi", mpc8xxx_spi);
	if (ret)
		goto free_irq;

	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
		mpc8xxx_spi->rx_shift = 16;
		mpc8xxx_spi->tx_shift = 24;
	}

	/* SPI controller initializations */
	mpc8xxx_spi_write_reg(&reg_base->mode, 0);
	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
	mpc8xxx_spi_write_reg(&reg_base->command, 0);
	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);

	/* Init eSPI CS mode register */
	for (i = 0; i < pdata->max_chipselect; i++)
		mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);

	/* Enable SPI interface */
	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;

	mpc8xxx_spi_write_reg(&reg_base->mode, regval);

	ret = spi_register_master(master);
	if (ret < 0)
		goto unreg_master;

	dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);

	return master;

unreg_master:
	free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
free_irq:
	iounmap(mpc8xxx_spi->reg_base);
err_probe:
	spi_master_put(master);
err:
	return ERR_PTR(ret);
}

static int of_fsl_espi_get_chipselects(struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct fsl_spi_platform_data *pdata = dev->platform_data;
	const u32 *prop;
	int len;

	prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
	if (!prop || len < sizeof(*prop)) {
		dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
		return -EINVAL;
	}

	pdata->max_chipselect = *prop;
	pdata->cs_control = NULL;

	return 0;
}

static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
{
	struct device *dev = &ofdev->dev;
	struct device_node *np = ofdev->dev.of_node;
	struct spi_master *master;
	struct resource mem;
	struct resource irq;
	int ret = -ENOMEM;

	ret = of_mpc8xxx_spi_probe(ofdev);
	if (ret)
		return ret;

	ret = of_fsl_espi_get_chipselects(dev);
	if (ret)
		goto err;

	ret = of_address_to_resource(np, 0, &mem);
	if (ret)
		goto err;

	ret = of_irq_to_resource(np, 0, &irq);
	if (!ret) {
		ret = -EINVAL;
		goto err;
	}

	master = fsl_espi_probe(dev, &mem, irq.start);
	if (IS_ERR(master)) {
		ret = PTR_ERR(master);
		goto err;
	}

	return 0;

err:
	return ret;
}

static int __devexit of_fsl_espi_remove(struct platform_device *dev)
{
	return mpc8xxx_spi_remove(&dev->dev);
}

static const struct of_device_id of_fsl_espi_match[] = {
	{ .compatible = "fsl,mpc8536-espi" },
	{}
};
MODULE_DEVICE_TABLE(of, of_fsl_espi_match);

static struct platform_driver fsl_espi_driver = {
	.driver = {
		.name = "fsl_espi",
		.owner = THIS_MODULE,
		.of_match_table = of_fsl_espi_match,
	},
	.probe		= of_fsl_espi_probe,
	.remove		= __devexit_p(of_fsl_espi_remove),
};

static int __init fsl_espi_init(void)
{
	return platform_driver_register(&fsl_espi_driver);
}
module_init(fsl_espi_init);

static void __exit fsl_espi_exit(void)
{
	platform_driver_unregister(&fsl_espi_driver);
}
module_exit(fsl_espi_exit);

MODULE_AUTHOR("Mingkai Hu");
MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
8b60d6c2 MH	1	/*
	2	* Freescale eSPI controller driver.
	3	*
	4	* Copyright 2010 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11	#include <linux/module.h>
	12	#include <linux/delay.h>
	13	#include <linux/irq.h>
	14	#include <linux/spi/spi.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/fsl_devices.h>
	17	#include <linux/mm.h>
	18	#include <linux/of.h>
	19	#include <linux/of_platform.h>
	20	#include <linux/of_spi.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/err.h>
	23	#include <sysdev/fsl_soc.h>
	24
ca632f55	25	#include "spi-fsl-lib.h"
8b60d6c2 MH	26
	27	/* eSPI Controller registers */
	28	struct fsl_espi_reg {
	29	__be32 mode; /* 0x000 - eSPI mode register */
	30	__be32 event; /* 0x004 - eSPI event register */
	31	__be32 mask; /* 0x008 - eSPI mask register */
	32	__be32 command; /* 0x00c - eSPI command register */
	33	__be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
	34	__be32 receive; /* 0x014 - eSPI receive FIFO access register*/
	35	u8 res[8]; /* 0x018 - 0x01c reserved */
	36	__be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
	37	};
	38
	39	struct fsl_espi_transfer {
	40	const void *tx_buf;
	41	void *rx_buf;
	42	unsigned len;
	43	unsigned n_tx;
	44	unsigned n_rx;
	45	unsigned actual_length;
	46	int status;
	47	};
	48
	49	/* eSPI Controller mode register definitions */
	50	#define SPMODE_ENABLE (1 << 31)
	51	#define SPMODE_LOOP (1 << 30)
	52	#define SPMODE_TXTHR(x) ((x) << 8)
	53	#define SPMODE_RXTHR(x) ((x) << 0)
	54
	55	/* eSPI Controller CS mode register definitions */
	56	#define CSMODE_CI_INACTIVEHIGH (1 << 31)
	57	#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
	58	#define CSMODE_REV (1 << 29)
	59	#define CSMODE_DIV16 (1 << 28)
	60	#define CSMODE_PM(x) ((x) << 24)
	61	#define CSMODE_POL_1 (1 << 20)
	62	#define CSMODE_LEN(x) ((x) << 16)
	63	#define CSMODE_BEF(x) ((x) << 12)
	64	#define CSMODE_AFT(x) ((x) << 8)
	65	#define CSMODE_CG(x) ((x) << 3)
	66
	67	/* Default mode/csmode for eSPI controller */
	68	#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) \| SPMODE_RXTHR(3))
	69	#define CSMODE_INIT_VAL (CSMODE_POL_1 \| CSMODE_BEF(0) \
	70	\| CSMODE_AFT(0) \| CSMODE_CG(1))
	71
	72	/* SPIE register values */
	73	#define SPIE_NE 0x00000200 /* Not empty */
	74	#define SPIE_NF 0x00000100 /* Not full */
	75
	76	/* SPIM register values */
	77	#define SPIM_NE 0x00000200 /* Not empty */
	78	#define SPIM_NF 0x00000100 /* Not full */
	79	#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
	80	#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
	81
	82	/* SPCOM register values */
	83	#define SPCOM_CS(x) ((x) << 30)
	84	#define SPCOM_TRANLEN(x) ((x) << 0)
	85	#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
	86
	87	static void fsl_espi_change_mode(struct spi_device *spi)
	88	{
	89	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
90	struct spi_mpc8xxx_cs *cs = spi->controller_state;
91	struct fsl_espi_reg *reg_base = mspi->reg_base;
92	__be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
93	__be32 __iomem *espi_mode = &reg_base->mode;
94	u32 tmp;
95	unsigned long flags;
96
97	/* Turn off IRQs locally to minimize time that SPI is disabled. */
98	local_irq_save(flags);
99
100	/* Turn off SPI unit prior changing mode */
101	tmp = mpc8xxx_spi_read_reg(espi_mode);
102	mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
103	mpc8xxx_spi_write_reg(mode, cs->hw_mode);
104	mpc8xxx_spi_write_reg(espi_mode, tmp);
105
106	local_irq_restore(flags);
107	}
108
109	static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
110	{
111	u32 data;
112	u16 data_h;
113	u16 data_l;
114	const u32 *tx = mpc8xxx_spi->tx;
115
116	if (!tx)
117	return 0;
118
119	data = *tx++ << mpc8xxx_spi->tx_shift;
120	data_l = data & 0xffff;
121	data_h = (data >> 16) & 0xffff;
122	swab16s(&data_l);
123	swab16s(&data_h);
124	data = data_h \| data_l;
125
126	mpc8xxx_spi->tx = tx;
127	return data;
128	}
129
130	static int fsl_espi_setup_transfer(struct spi_device *spi,
131	struct spi_transfer *t)
132	{
133	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
134	int bits_per_word = 0;
135	u8 pm;
136	u32 hz = 0;
137	struct spi_mpc8xxx_cs *cs = spi->controller_state;
138
139	if (t) {
140	bits_per_word = t->bits_per_word;
141	hz = t->speed_hz;
142	}
143
144	/* spi_transfer level calls that work per-word */
145	if (!bits_per_word)
146	bits_per_word = spi->bits_per_word;
147
148	/* Make sure its a bit width we support [4..16] */
149	if ((bits_per_word < 4) \|\| (bits_per_word > 16))
150	return -EINVAL;
151
152	if (!hz)
153	hz = spi->max_speed_hz;
154
155	cs->rx_shift = 0;
156	cs->tx_shift = 0;
157	cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158	cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159	if (bits_per_word <= 8) {
160	cs->rx_shift = 8 - bits_per_word;
161	} else if (bits_per_word <= 16) {
162	cs->rx_shift = 16 - bits_per_word;
163	if (spi->mode & SPI_LSB_FIRST)
164	cs->get_tx = fsl_espi_tx_buf_lsb;
165	} else {
166	return -EINVAL;
167	}
168
169	mpc8xxx_spi->rx_shift = cs->rx_shift;
170	mpc8xxx_spi->tx_shift = cs->tx_shift;
171	mpc8xxx_spi->get_rx = cs->get_rx;
172	mpc8xxx_spi->get_tx = cs->get_tx;
173
174	bits_per_word = bits_per_word - 1;
175
176	/* mask out bits we are going to set */
177	cs->hw_mode &= ~(CSMODE_LEN(0xF) \| CSMODE_DIV16 \| CSMODE_PM(0xF));
178
179	cs->hw_mode \|= CSMODE_LEN(bits_per_word);
180
181	if ((mpc8xxx_spi->spibrg / hz) > 64) {
182	cs->hw_mode \|= CSMODE_DIV16;
183	pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
184
185	WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
186	"Will use %d Hz instead.\n", dev_name(&spi->dev),
187	hz, mpc8xxx_spi->spibrg / 1024);
188	if (pm > 16)
189	pm = 16;
190	} else {
191	pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
192	}
193	if (pm)
194	pm--;
195
196	cs->hw_mode \|= CSMODE_PM(pm);
197
198	fsl_espi_change_mode(spi);
199	return 0;
200	}
201
202	static int fsl_espi_cpu_bufs(struct mpc8xxx_spi mspi, struct spi_transfer t,
203	unsigned int len)
204	{
205	u32 word;
206	struct fsl_espi_reg *reg_base = mspi->reg_base;
207
208	mspi->count = len;
209
210	/* enable rx ints */
211	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
212
213	/* transmit word */
214	word = mspi->get_tx(mspi);
215	mpc8xxx_spi_write_reg(&reg_base->transmit, word);
216
217	return 0;
218	}
219
220	static int fsl_espi_bufs(struct spi_device spi, struct spi_transfer t)
221	{
222	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
223	struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
224	unsigned int len = t->len;
225	u8 bits_per_word;
226	int ret;
227
228	bits_per_word = spi->bits_per_word;
229	if (t->bits_per_word)
230	bits_per_word = t->bits_per_word;
231
232	mpc8xxx_spi->len = t->len;
233	len = roundup(len, 4) / 4;
234
235	mpc8xxx_spi->tx = t->tx_buf;
236	mpc8xxx_spi->rx = t->rx_buf;
237
238	INIT_COMPLETION(mpc8xxx_spi->done);
239
240	/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
241	if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
242	dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
243	" beyond the SPCOM[TRANLEN] field\n", t->len);
244	return -EINVAL;
245	}
246	mpc8xxx_spi_write_reg(&reg_base->command,
247	(SPCOM_CS(spi->chip_select) \| SPCOM_TRANLEN(t->len - 1)));
248
249	ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
250	if (ret)
251	return ret;
252
253	wait_for_completion(&mpc8xxx_spi->done);
254
255	/* disable rx ints */
256	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
257
258	return mpc8xxx_spi->count;
259	}
260
0dd2c96f	261	static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
8b60d6c2	262	{
0dd2c96f	263	if (cmd) {
8b60d6c2 MH	264	cmd[1] = (u8)(addr >> 16);
	265	cmd[2] = (u8)(addr >> 8);
	266	cmd[3] = (u8)(addr >> 0);
	267	}
	268	}
	269
0dd2c96f	270	static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
8b60d6c2	271	{
0dd2c96f	272	if (cmd)
8b60d6c2 MH	273	return cmd[1] << 16 \| cmd[2] << 8 \| cmd[3] << 0;
	274
	275	return 0;
	276	}
	277
	278	static void fsl_espi_do_trans(struct spi_message *m,
	279	struct fsl_espi_transfer *tr)
	280	{
	281	struct spi_device *spi = m->spi;
	282	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
	283	struct fsl_espi_transfer *espi_trans = tr;
	284	struct spi_message message;
	285	struct spi_transfer t, first, trans;
	286	int status = 0;
	287
	288	spi_message_init(&message);
	289	memset(&trans, 0, sizeof(trans));
	290
	291	first = list_first_entry(&m->transfers, struct spi_transfer,
	292	transfer_list);
	293	list_for_each_entry(t, &m->transfers, transfer_list) {
	294	if ((first->bits_per_word != t->bits_per_word) \|\|
	295	(first->speed_hz != t->speed_hz)) {
	296	espi_trans->status = -EINVAL;
	297	dev_err(mspi->dev, "bits_per_word/speed_hz should be"
	298	" same for the same SPI transfer\n");
	299	return;
	300	}
	301
	302	trans.speed_hz = t->speed_hz;
	303	trans.bits_per_word = t->bits_per_word;
	304	trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
	305	}
	306
	307	trans.len = espi_trans->len;
	308	trans.tx_buf = espi_trans->tx_buf;
	309	trans.rx_buf = espi_trans->rx_buf;
	310	spi_message_add_tail(&trans, &message);
	311
	312	list_for_each_entry(t, &message.transfers, transfer_list) {
	313	if (t->bits_per_word \|\| t->speed_hz) {
	314	status = -EINVAL;
	315
	316	status = fsl_espi_setup_transfer(spi, t);
	317	if (status < 0)
	318	break;
	319	}
	320
	321	if (t->len)
	322	status = fsl_espi_bufs(spi, t);
	323
	324	if (status) {
	325	status = -EMSGSIZE;
	326	break;
	327	}
	328
	329	if (t->delay_usecs)
	330	udelay(t->delay_usecs);
	331	}
	332
	333	espi_trans->status = status;
	334	fsl_espi_setup_transfer(spi, NULL);
	335	}
	336
337	static void fsl_espi_cmd_trans(struct spi_message *m,
338	struct fsl_espi_transfer trans, u8 rx_buff)
339	{
340	struct spi_transfer *t;
341	u8 *local_buf;
342	int i = 0;
343	struct fsl_espi_transfer *espi_trans = trans;
344
345	local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
346	if (!local_buf) {
347	espi_trans->status = -ENOMEM;
348	return;
349	}
350
351	list_for_each_entry(t, &m->transfers, transfer_list) {
352	if (t->tx_buf) {
353	memcpy(local_buf + i, t->tx_buf, t->len);
354	i += t->len;
355	}
356	}
357
358	espi_trans->tx_buf = local_buf;
359	espi_trans->rx_buf = local_buf + espi_trans->n_tx;
360	fsl_espi_do_trans(m, espi_trans);
361
362	espi_trans->actual_length = espi_trans->len;
363	kfree(local_buf);
364	}
365
366	static void fsl_espi_rw_trans(struct spi_message *m,
367	struct fsl_espi_transfer trans, u8 rx_buff)
368	{
369	struct fsl_espi_transfer *espi_trans = trans;
370	unsigned int n_tx = espi_trans->n_tx;
371	unsigned int n_rx = espi_trans->n_rx;
372	struct spi_transfer *t;
373	u8 *local_buf;
374	u8 *rx_buf = rx_buff;
375	unsigned int trans_len;
376	unsigned int addr;
377	int i, pos, loop;
378
379	local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
380	if (!local_buf) {
381	espi_trans->status = -ENOMEM;
382	return;
383	}
384
385	for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
386	trans_len = n_rx - pos;
387	if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
388	trans_len = SPCOM_TRANLEN_MAX - n_tx;
389
390	i = 0;
391	list_for_each_entry(t, &m->transfers, transfer_list) {
392	if (t->tx_buf) {
393	memcpy(local_buf + i, t->tx_buf, t->len);
394	i += t->len;
395	}
396	}
397
0dd2c96f MH	398	if (pos > 0) {
	399	addr = fsl_espi_cmd2addr(local_buf);
	400	addr += pos;
	401	fsl_espi_addr2cmd(addr, local_buf);
	402	}
8b60d6c2 MH	403
	404	espi_trans->n_tx = n_tx;
	405	espi_trans->n_rx = trans_len;
	406	espi_trans->len = trans_len + n_tx;
	407	espi_trans->tx_buf = local_buf;
	408	espi_trans->rx_buf = local_buf + n_tx;
	409	fsl_espi_do_trans(m, espi_trans);
	410
	411	memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
	412
	413	if (loop > 0)
	414	espi_trans->actual_length += espi_trans->len - n_tx;
	415	else
	416	espi_trans->actual_length += espi_trans->len;
	417	}
	418
	419	kfree(local_buf);
	420	}
	421
	422	static void fsl_espi_do_one_msg(struct spi_message *m)
	423	{
	424	struct spi_transfer *t;
	425	u8 *rx_buf = NULL;
	426	unsigned int n_tx = 0;
	427	unsigned int n_rx = 0;
	428	struct fsl_espi_transfer espi_trans;
	429
	430	list_for_each_entry(t, &m->transfers, transfer_list) {
	431	if (t->tx_buf)
	432	n_tx += t->len;
	433	if (t->rx_buf) {
	434	n_rx += t->len;
	435	rx_buf = t->rx_buf;
	436	}
	437	}
	438
	439	espi_trans.n_tx = n_tx;
	440	espi_trans.n_rx = n_rx;
	441	espi_trans.len = n_tx + n_rx;
	442	espi_trans.actual_length = 0;
	443	espi_trans.status = 0;
	444
	445	if (!rx_buf)
	446	fsl_espi_cmd_trans(m, &espi_trans, NULL);
	447	else
	448	fsl_espi_rw_trans(m, &espi_trans, rx_buf);
	449
	450	m->actual_length = espi_trans.actual_length;
	451	m->status = espi_trans.status;
	452	m->complete(m->context);
	453	}
	454
	455	static int fsl_espi_setup(struct spi_device *spi)
	456	{
	457	struct mpc8xxx_spi *mpc8xxx_spi;
	458	struct fsl_espi_reg *reg_base;
	459	int retval;
	460	u32 hw_mode;
	461	u32 loop_mode;
	462	struct spi_mpc8xxx_cs *cs = spi->controller_state;
	463
	464	if (!spi->max_speed_hz)
	465	return -EINVAL;
	466
467	if (!cs) {
468	cs = kzalloc(sizeof *cs, GFP_KERNEL);
469	if (!cs)
470	return -ENOMEM;
471	spi->controller_state = cs;
472	}
473
474	mpc8xxx_spi = spi_master_get_devdata(spi->master);
475	reg_base = mpc8xxx_spi->reg_base;
476
25985edc	477	hw_mode = cs->hw_mode; /* Save original settings */
8b60d6c2 MH	478	cs->hw_mode = mpc8xxx_spi_read_reg(
	479	&reg_base->csmode[spi->chip_select]);
	480	/* mask out bits we are going to set */
	481	cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK \| CSMODE_CI_INACTIVEHIGH
	482	\| CSMODE_REV);
	483
	484	if (spi->mode & SPI_CPHA)
	485	cs->hw_mode \|= CSMODE_CP_BEGIN_EDGECLK;
	486	if (spi->mode & SPI_CPOL)
	487	cs->hw_mode \|= CSMODE_CI_INACTIVEHIGH;
	488	if (!(spi->mode & SPI_LSB_FIRST))
	489	cs->hw_mode \|= CSMODE_REV;
	490
	491	/* Handle the loop mode */
	492	loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
	493	loop_mode &= ~SPMODE_LOOP;
	494	if (spi->mode & SPI_LOOP)
	495	loop_mode \|= SPMODE_LOOP;
	496	mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
	497
	498	retval = fsl_espi_setup_transfer(spi, NULL);
	499	if (retval < 0) {
	500	cs->hw_mode = hw_mode; /* Restore settings */
	501	return retval;
	502	}
	503	return 0;
	504	}
	505
	506	void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
	507	{
	508	struct fsl_espi_reg *reg_base = mspi->reg_base;
	509
	510	/* We need handle RX first */
	511	if (events & SPIE_NE) {
e6289d63 MH	512	u32 rx_data, tmp;
e6289d63 MH	513	u8 rx_data_8;
8b60d6c2 MH	514
	515	/* Spin until RX is done */
	516	while (SPIE_RXCNT(events) < min(4, mspi->len)) {
	517	cpu_relax();
	518	events = mpc8xxx_spi_read_reg(&reg_base->event);
	519	}
8b60d6c2	520
e6289d63 MH	521	if (mspi->len >= 4) {
	522	rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
	523	} else {
	524	tmp = mspi->len;
	525	rx_data = 0;
	526	while (tmp--) {
	527	rx_data_8 = in_8((u8 *)&reg_base->receive);
	528	rx_data \|= (rx_data_8 << (tmp * 8));
	529	}
	530
	531	rx_data <<= (4 - mspi->len) * 8;
	532	}
	533
	534	mspi->len -= 4;
8b60d6c2 MH	535
	536	if (mspi->rx)
	537	mspi->get_rx(rx_data, mspi);
	538	}
	539
	540	if (!(events & SPIE_NF)) {
	541	int ret;
	542
	543	/* spin until TX is done */
	544	ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
	545	&reg_base->event)) & SPIE_NF) == 0, 1000, 0);
	546	if (!ret) {
	547	dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
	548	return;
	549	}
	550	}
	551
	552	/* Clear the events */
	553	mpc8xxx_spi_write_reg(&reg_base->event, events);
	554
	555	mspi->count -= 1;
	556	if (mspi->count) {
	557	u32 word = mspi->get_tx(mspi);
	558
	559	mpc8xxx_spi_write_reg(&reg_base->transmit, word);
	560	} else {
	561	complete(&mspi->done);
	562	}
	563	}
	564
	565	static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
	566	{
	567	struct mpc8xxx_spi *mspi = context_data;
	568	struct fsl_espi_reg *reg_base = mspi->reg_base;
	569	irqreturn_t ret = IRQ_NONE;
	570	u32 events;
	571
	572	/* Get interrupt events(tx/rx) */
	573	events = mpc8xxx_spi_read_reg(&reg_base->event);
	574	if (events)
	575	ret = IRQ_HANDLED;
	576
	577	dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
	578
	579	fsl_espi_cpu_irq(mspi, events);
	580
	581	return ret;
	582	}
	583
	584	static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
	585	{
	586	iounmap(mspi->reg_base);
	587	}
	588
	589	static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
	590	struct resource *mem, unsigned int irq)
	591	{
	592	struct fsl_spi_platform_data *pdata = dev->platform_data;
	593	struct spi_master *master;
	594	struct mpc8xxx_spi *mpc8xxx_spi;
	595	struct fsl_espi_reg *reg_base;
	596	u32 regval;
	597	int i, ret = 0;
	598
599	master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
600	if (!master) {
601	ret = -ENOMEM;
602	goto err;
603	}
604
605	dev_set_drvdata(dev, master);
606
607	ret = mpc8xxx_spi_probe(dev, mem, irq);
608	if (ret)
609	goto err_probe;
610
611	master->setup = fsl_espi_setup;
612
613	mpc8xxx_spi = spi_master_get_devdata(master);
614	mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
615	mpc8xxx_spi->spi_remove = fsl_espi_remove;
616
617	mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
618	if (!mpc8xxx_spi->reg_base) {
619	ret = -ENOMEM;
620	goto err_probe;
621	}
622
623	reg_base = mpc8xxx_spi->reg_base;
624
625	/* Register for SPI Interrupt */
626	ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
627	0, "fsl_espi", mpc8xxx_spi);
628	if (ret)
629	goto free_irq;
630
631	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
632	mpc8xxx_spi->rx_shift = 16;
633	mpc8xxx_spi->tx_shift = 24;
634	}
635
636	/* SPI controller initializations */
637	mpc8xxx_spi_write_reg(&reg_base->mode, 0);
638	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
639	mpc8xxx_spi_write_reg(&reg_base->command, 0);
640	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
641
642	/* Init eSPI CS mode register */
643	for (i = 0; i < pdata->max_chipselect; i++)
644	mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
645
646	/* Enable SPI interface */
647	regval = pdata->initial_spmode \| SPMODE_INIT_VAL \| SPMODE_ENABLE;
648
649	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
650
651	ret = spi_register_master(master);
652	if (ret < 0)
653	goto unreg_master;
654
655	dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
656
657	return master;
658
659	unreg_master:
660	free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
661	free_irq:
662	iounmap(mpc8xxx_spi->reg_base);
663	err_probe:
664	spi_master_put(master);
665	err:
666	return ERR_PTR(ret);
667	}
668
669	static int of_fsl_espi_get_chipselects(struct device *dev)
670	{
671	struct device_node *np = dev->of_node;
672	struct fsl_spi_platform_data *pdata = dev->platform_data;
673	const u32 *prop;
674	int len;
675
676	prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
677	if (!prop \|\| len < sizeof(*prop)) {
678	dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
679	return -EINVAL;
680	}
681
682	pdata->max_chipselect = *prop;
683	pdata->cs_control = NULL;
684
685	return 0;
686	}
687
18d306d1	688	static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
8b60d6c2 MH	689	{
	690	struct device *dev = &ofdev->dev;
	691	struct device_node *np = ofdev->dev.of_node;
	692	struct spi_master *master;
	693	struct resource mem;
	694	struct resource irq;
	695	int ret = -ENOMEM;
	696
18d306d1	697	ret = of_mpc8xxx_spi_probe(ofdev);
8b60d6c2 MH	698	if (ret)
	699	return ret;
	700
	701	ret = of_fsl_espi_get_chipselects(dev);
	702	if (ret)
	703	goto err;
	704
	705	ret = of_address_to_resource(np, 0, &mem);
	706	if (ret)
	707	goto err;
	708
	709	ret = of_irq_to_resource(np, 0, &irq);
	710	if (!ret) {
	711	ret = -EINVAL;
	712	goto err;
	713	}
	714
	715	master = fsl_espi_probe(dev, &mem, irq.start);
	716	if (IS_ERR(master)) {
	717	ret = PTR_ERR(master);
	718	goto err;
	719	}
	720
	721	return 0;
	722
	723	err:
	724	return ret;
	725	}
	726
	727	static int __devexit of_fsl_espi_remove(struct platform_device *dev)
	728	{
	729	return mpc8xxx_spi_remove(&dev->dev);
	730	}
	731
	732	static const struct of_device_id of_fsl_espi_match[] = {
	733	{ .compatible = "fsl,mpc8536-espi" },
	734	{}
	735	};
	736	MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
	737
18d306d1	738	static struct platform_driver fsl_espi_driver = {
8b60d6c2 MH	739	.driver = {
	740	.name = "fsl_espi",
	741	.owner = THIS_MODULE,
	742	.of_match_table = of_fsl_espi_match,
	743	},
	744	.probe = of_fsl_espi_probe,
	745	.remove = __devexit_p(of_fsl_espi_remove),
	746	};
	747
	748	static int __init fsl_espi_init(void)
	749	{
18d306d1	750	return platform_driver_register(&fsl_espi_driver);
8b60d6c2 MH	751	}
	752	module_init(fsl_espi_init);
	753
	754	static void __exit fsl_espi_exit(void)
	755	{
18d306d1	756	platform_driver_unregister(&fsl_espi_driver);
8b60d6c2 MH	757	}
	758	module_exit(fsl_espi_exit);
	759
	760	MODULE_AUTHOR("Mingkai Hu");
	761	MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
	762	MODULE_LICENSE("GPL");