[linux.git] / arch / ppc / mm / 4xx_mmu.c

/*
 * This file contains the routines for initializing the MMU
 * on the 4xx series of chips.
 *  -- paulus
 *
 *  Derived from arch/ppc/mm/init.c:
 *    Copyright (C) 1995-1996 Gary Thomas ([email protected])
 *
 *  Modifications by Paul Mackerras (PowerMac) ([email protected])
 *  and Cort Dougan (PReP) ([email protected])
 *    Copyright (C) 1996 Paul Mackerras
 *  Amiga/APUS changes by Jesper Skov ([email protected]).
 *
 *  Derived from "arch/i386/mm/init.c"
 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */

#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/stddef.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/highmem.h>

#include <asm/pgalloc.h>
#include <asm/prom.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/mmu.h>
#include <asm/uaccess.h>
#include <asm/smp.h>
#include <asm/bootx.h>
#include <asm/machdep.h>
#include <asm/setup.h>
#include "mmu_decl.h"

extern int __map_without_ltlbs;
/*
 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
 */
void __init MMU_init_hw(void)
{
	/*
	 * The Zone Protection Register (ZPR) defines how protection will
	 * be applied to every page which is a member of a given zone. At
	 * present, we utilize only two of the 4xx's zones.
	 * The zone index bits (of ZSEL) in the PTE are used for software
	 * indicators, except the LSB.  For user access, zone 1 is used,
	 * for kernel access, zone 0 is used.  We set all but zone 1
	 * to zero, allowing only kernel access as indicated in the PTE.
	 * For zone 1, we set a 01 binary (a value of 10 will not work)
	 * to allow user access as indicated in the PTE.  This also allows
	 * kernel access as indicated in the PTE.
	 */

        mtspr(SPRN_ZPR, 0x10000000);

	flush_instruction_cache();

	/*
	 * Set up the real-mode cache parameters for the exception vector
	 * handlers (which are run in real-mode).
	 */

        mtspr(SPRN_DCWR, 0x00000000);	/* All caching is write-back */

        /*
	 * Cache instruction and data space where the exception
	 * vectors and the kernel live in real-mode.
	 */

        mtspr(SPRN_DCCR, 0xF0000000);	/* 512 MB of data space at 0x0. */
        mtspr(SPRN_ICCR, 0xF0000000);	/* 512 MB of instr. space at 0x0. */
}

#define LARGE_PAGE_SIZE_16M	(1<<24)
#define LARGE_PAGE_SIZE_4M	(1<<22)

unsigned long __init mmu_mapin_ram(void)
{
	unsigned long v, s;
	phys_addr_t p;

	v = KERNELBASE;
	p = PPC_MEMSTART;
	s = total_lowmem;

	if (__map_without_ltlbs)
		return 0;

	while (s >= LARGE_PAGE_SIZE_16M) {
		pmd_t *pmdp;
		unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;

		pmdp = pmd_offset(pgd_offset_k(v), v);
		pmd_val(*pmdp++) = val;
		pmd_val(*pmdp++) = val;
		pmd_val(*pmdp++) = val;
		pmd_val(*pmdp++) = val;

		v += LARGE_PAGE_SIZE_16M;
		p += LARGE_PAGE_SIZE_16M;
		s -= LARGE_PAGE_SIZE_16M;
	}

	while (s >= LARGE_PAGE_SIZE_4M) {
		pmd_t *pmdp;
		unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;

		pmdp = pmd_offset(pgd_offset_k(v), v);
		pmd_val(*pmdp) = val;

		v += LARGE_PAGE_SIZE_4M;
		p += LARGE_PAGE_SIZE_4M;
		s -= LARGE_PAGE_SIZE_4M;
	}

	return total_lowmem - s;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains the routines for initializing the MMU
	3	* on the 4xx series of chips.
	4	* -- paulus
	5	*
	6	* Derived from arch/ppc/mm/init.c:
	7	* Copyright (C) 1995-1996 Gary Thomas ([email protected])
	8	*
	9	* Modifications by Paul Mackerras (PowerMac) ([email protected])
	10	* and Cort Dougan (PReP) ([email protected])
	11	* Copyright (C) 1996 Paul Mackerras
	12	* Amiga/APUS changes by Jesper Skov ([email protected]).
	13	*
	14	* Derived from "arch/i386/mm/init.c"
	15	* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License
	19	* as published by the Free Software Foundation; either version
	20	* 2 of the License, or (at your option) any later version.
	21	*
	22	*/
	23
1da177e4 LT	24	#include <linux/signal.h>
	25	#include <linux/sched.h>
	26	#include <linux/kernel.h>
	27	#include <linux/errno.h>
	28	#include <linux/string.h>
	29	#include <linux/types.h>
	30	#include <linux/ptrace.h>
	31	#include <linux/mman.h>
	32	#include <linux/mm.h>
	33	#include <linux/swap.h>
	34	#include <linux/stddef.h>
	35	#include <linux/vmalloc.h>
	36	#include <linux/init.h>
	37	#include <linux/delay.h>
1da177e4 LT	38	#include <linux/highmem.h>
	39
	40	#include <asm/pgalloc.h>
	41	#include <asm/prom.h>
	42	#include <asm/io.h>
	43	#include <asm/mmu_context.h>
	44	#include <asm/pgtable.h>
	45	#include <asm/mmu.h>
	46	#include <asm/uaccess.h>
	47	#include <asm/smp.h>
	48	#include <asm/bootx.h>
	49	#include <asm/machdep.h>
	50	#include <asm/setup.h>
	51	#include "mmu_decl.h"
	52
	53	extern int __map_without_ltlbs;
	54	/*
	55	* MMU_init_hw does the chip-specific initialization of the MMU hardware.
	56	*/
	57	void __init MMU_init_hw(void)
	58	{
	59	/*
	60	* The Zone Protection Register (ZPR) defines how protection will
	61	* be applied to every page which is a member of a given zone. At
	62	* present, we utilize only two of the 4xx's zones.
	63	* The zone index bits (of ZSEL) in the PTE are used for software
	64	* indicators, except the LSB. For user access, zone 1 is used,
	65	* for kernel access, zone 0 is used. We set all but zone 1
	66	* to zero, allowing only kernel access as indicated in the PTE.
	67	* For zone 1, we set a 01 binary (a value of 10 will not work)
	68	* to allow user access as indicated in the PTE. This also allows
	69	* kernel access as indicated in the PTE.
	70	*/
	71
	72	mtspr(SPRN_ZPR, 0x10000000);
	73
	74	flush_instruction_cache();
	75
	76	/*
	77	* Set up the real-mode cache parameters for the exception vector
	78	* handlers (which are run in real-mode).
	79	*/
	80
	81	mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
	82
	83	/*
	84	* Cache instruction and data space where the exception
	85	* vectors and the kernel live in real-mode.
	86	*/
	87
	88	mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */
	89	mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */
	90	}
	91
	92	#define LARGE_PAGE_SIZE_16M (1<<24)
	93	#define LARGE_PAGE_SIZE_4M (1<<22)
	94
	95	unsigned long __init mmu_mapin_ram(void)
	96	{
	97	unsigned long v, s;
	98	phys_addr_t p;
	99
	100	v = KERNELBASE;
	101	p = PPC_MEMSTART;
bd942ba3	102	s = total_lowmem;
1da177e4	103
bd942ba3 GL	104	if (__map_without_ltlbs)
bd942ba3 GL	105	return 0;
1da177e4	106
bd942ba3	107	while (s >= LARGE_PAGE_SIZE_16M) {
1da177e4 LT	108	pmd_t *pmdp;
	109	unsigned long val = p \| _PMD_SIZE_16M \| _PAGE_HWEXEC \| _PAGE_HWWRITE;
	110
1da177e4 LT	111	pmdp = pmd_offset(pgd_offset_k(v), v);
	112	pmd_val(*pmdp++) = val;
	113	pmd_val(*pmdp++) = val;
	114	pmd_val(*pmdp++) = val;
	115	pmd_val(*pmdp++) = val;
1da177e4 LT	116
	117	v += LARGE_PAGE_SIZE_16M;
	118	p += LARGE_PAGE_SIZE_16M;
bd942ba3	119	s -= LARGE_PAGE_SIZE_16M;
1da177e4 LT	120	}
1da177e4 LT	121
bd942ba3	122	while (s >= LARGE_PAGE_SIZE_4M) {
1da177e4 LT	123	pmd_t *pmdp;
	124	unsigned long val = p \| _PMD_SIZE_4M \| _PAGE_HWEXEC \| _PAGE_HWWRITE;
	125
1da177e4 LT	126	pmdp = pmd_offset(pgd_offset_k(v), v);
1da177e4 LT	127	pmd_val(*pmdp) = val;
1da177e4 LT	128
	129	v += LARGE_PAGE_SIZE_4M;
	130	p += LARGE_PAGE_SIZE_4M;
bd942ba3	131	s -= LARGE_PAGE_SIZE_4M;
1da177e4 LT	132	}
1da177e4 LT	133
bd942ba3	134	return total_lowmem - s;
1da177e4	135	}