projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 77c9a5da SR |
1 | #ifndef _FIREWIRE_OHCI_H |
| 2 | #define _FIREWIRE_OHCI_H | |
| ed568912 KH |
3 | |
| 4 | /* OHCI register map */ | |
| 5 | ||
| 6 | #define OHCI1394_Version 0x000 | |
| 7 | #define OHCI1394_GUID_ROM 0x004 | |
| 8 | #define OHCI1394_ATRetries 0x008 | |
| 9 | #define OHCI1394_CSRData 0x00C | |
| 10 | #define OHCI1394_CSRCompareData 0x010 | |
| 11 | #define OHCI1394_CSRControl 0x014 | |
| 12 | #define OHCI1394_ConfigROMhdr 0x018 | |
| 13 | #define OHCI1394_BusID 0x01C | |
| 14 | #define OHCI1394_BusOptions 0x020 | |
| 15 | #define OHCI1394_GUIDHi 0x024 | |
| 16 | #define OHCI1394_GUIDLo 0x028 | |
| 17 | #define OHCI1394_ConfigROMmap 0x034 | |
| 18 | #define OHCI1394_PostedWriteAddressLo 0x038 | |
| 19 | #define OHCI1394_PostedWriteAddressHi 0x03C | |
| 20 | #define OHCI1394_VendorID 0x040 | |
| 21 | #define OHCI1394_HCControlSet 0x050 | |
| 22 | #define OHCI1394_HCControlClear 0x054 | |
| 23 | #define OHCI1394_HCControl_BIBimageValid 0x80000000 | |
| 24 | #define OHCI1394_HCControl_noByteSwapData 0x40000000 | |
| 25 | #define OHCI1394_HCControl_programPhyEnable 0x00800000 | |
| 26 | #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000 | |
| 27 | #define OHCI1394_HCControl_LPS 0x00080000 | |
| 28 | #define OHCI1394_HCControl_postedWriteEnable 0x00040000 | |
| 29 | #define OHCI1394_HCControl_linkEnable 0x00020000 | |
| 30 | #define OHCI1394_HCControl_softReset 0x00010000 | |
| 31 | #define OHCI1394_SelfIDBuffer 0x064 | |
| 32 | #define OHCI1394_SelfIDCount 0x068 | |
| c8a9a498 | 33 | #define OHCI1394_SelfIDCount_selfIDError 0x80000000 |
| ed568912 KH |
34 | #define OHCI1394_IRMultiChanMaskHiSet 0x070 |
| 35 | #define OHCI1394_IRMultiChanMaskHiClear 0x074 | |
| 36 | #define OHCI1394_IRMultiChanMaskLoSet 0x078 | |
| 37 | #define OHCI1394_IRMultiChanMaskLoClear 0x07C | |
| 38 | #define OHCI1394_IntEventSet 0x080 | |
| 39 | #define OHCI1394_IntEventClear 0x084 | |
| 40 | #define OHCI1394_IntMaskSet 0x088 | |
| 41 | #define OHCI1394_IntMaskClear 0x08C | |
| 42 | #define OHCI1394_IsoXmitIntEventSet 0x090 | |
| 43 | #define OHCI1394_IsoXmitIntEventClear 0x094 | |
| 44 | #define OHCI1394_IsoXmitIntMaskSet 0x098 | |
| 45 | #define OHCI1394_IsoXmitIntMaskClear 0x09C | |
| 46 | #define OHCI1394_IsoRecvIntEventSet 0x0A0 | |
| 47 | #define OHCI1394_IsoRecvIntEventClear 0x0A4 | |
| 48 | #define OHCI1394_IsoRecvIntMaskSet 0x0A8 | |
| 49 | #define OHCI1394_IsoRecvIntMaskClear 0x0AC | |
| 50 | #define OHCI1394_InitialBandwidthAvailable 0x0B0 | |
| 51 | #define OHCI1394_InitialChannelsAvailableHi 0x0B4 | |
| 52 | #define OHCI1394_InitialChannelsAvailableLo 0x0B8 | |
| 53 | #define OHCI1394_FairnessControl 0x0DC | |
| 54 | #define OHCI1394_LinkControlSet 0x0E0 | |
| 55 | #define OHCI1394_LinkControlClear 0x0E4 | |
| 56 | #define OHCI1394_LinkControl_rcvSelfID (1 << 9) | |
| 57 | #define OHCI1394_LinkControl_rcvPhyPkt (1 << 10) | |
| 58 | #define OHCI1394_LinkControl_cycleTimerEnable (1 << 20) | |
| 59 | #define OHCI1394_LinkControl_cycleMaster (1 << 21) | |
| 60 | #define OHCI1394_LinkControl_cycleSource (1 << 22) | |
| 61 | #define OHCI1394_NodeID 0x0E8 | |
| 62 | #define OHCI1394_NodeID_idValid 0x80000000 | |
| 02ff8f8e SR |
63 | #define OHCI1394_NodeID_nodeNumber 0x0000003f |
| 64 | #define OHCI1394_NodeID_busNumber 0x0000ffc0 | |
| ed568912 KH |
65 | #define OHCI1394_PhyControl 0x0EC |
| 66 | #define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000) | |
| 67 | #define OHCI1394_PhyControl_ReadDone 0x80000000 | |
| 68 | #define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16) | |
| 5e20c282 | 69 | #define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000) |
| ed568912 KH |
70 | #define OHCI1394_PhyControl_WriteDone 0x00004000 |
| 71 | #define OHCI1394_IsochronousCycleTimer 0x0F0 | |
| 72 | #define OHCI1394_AsReqFilterHiSet 0x100 | |
| 73 | #define OHCI1394_AsReqFilterHiClear 0x104 | |
| 74 | #define OHCI1394_AsReqFilterLoSet 0x108 | |
| 75 | #define OHCI1394_AsReqFilterLoClear 0x10C | |
| 76 | #define OHCI1394_PhyReqFilterHiSet 0x110 | |
| 77 | #define OHCI1394_PhyReqFilterHiClear 0x114 | |
| 78 | #define OHCI1394_PhyReqFilterLoSet 0x118 | |
| 79 | #define OHCI1394_PhyReqFilterLoClear 0x11C | |
| 80 | #define OHCI1394_PhyUpperBound 0x120 | |
| 81 | ||
| 82 | #define OHCI1394_AsReqTrContextBase 0x180 | |
| 83 | #define OHCI1394_AsReqTrContextControlSet 0x180 | |
| 84 | #define OHCI1394_AsReqTrContextControlClear 0x184 | |
| 85 | #define OHCI1394_AsReqTrCommandPtr 0x18C | |
| 86 | ||
| 87 | #define OHCI1394_AsRspTrContextBase 0x1A0 | |
| 88 | #define OHCI1394_AsRspTrContextControlSet 0x1A0 | |
| 89 | #define OHCI1394_AsRspTrContextControlClear 0x1A4 | |
| 90 | #define OHCI1394_AsRspTrCommandPtr 0x1AC | |
| 91 | ||
| 92 | #define OHCI1394_AsReqRcvContextBase 0x1C0 | |
| 93 | #define OHCI1394_AsReqRcvContextControlSet 0x1C0 | |
| 94 | #define OHCI1394_AsReqRcvContextControlClear 0x1C4 | |
| 95 | #define OHCI1394_AsReqRcvCommandPtr 0x1CC | |
| 96 | ||
| 97 | #define OHCI1394_AsRspRcvContextBase 0x1E0 | |
| 98 | #define OHCI1394_AsRspRcvContextControlSet 0x1E0 | |
| 99 | #define OHCI1394_AsRspRcvContextControlClear 0x1E4 | |
| 100 | #define OHCI1394_AsRspRcvCommandPtr 0x1EC | |
| 101 | ||
| 102 | /* Isochronous transmit registers */ | |
| 103 | #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n)) | |
| 104 | #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n)) | |
| 105 | #define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n)) | |
| 106 | #define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n)) | |
| 107 | ||
| 108 | /* Isochronous receive registers */ | |
| 295e3feb | 109 | #define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n)) |
| ed568912 KH |
110 | #define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n)) |
| 111 | #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n)) | |
| 112 | #define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n)) | |
| 113 | #define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n)) | |
| 114 | ||
| 115 | /* Interrupts Mask/Events */ | |
| 5e20c282 SR |
116 | #define OHCI1394_reqTxComplete 0x00000001 |
| 117 | #define OHCI1394_respTxComplete 0x00000002 | |
| 118 | #define OHCI1394_ARRQ 0x00000004 | |
| 119 | #define OHCI1394_ARRS 0x00000008 | |
| 120 | #define OHCI1394_RQPkt 0x00000010 | |
| 121 | #define OHCI1394_RSPkt 0x00000020 | |
| 122 | #define OHCI1394_isochTx 0x00000040 | |
| 123 | #define OHCI1394_isochRx 0x00000080 | |
| 124 | #define OHCI1394_postedWriteErr 0x00000100 | |
| 125 | #define OHCI1394_lockRespErr 0x00000200 | |
| 126 | #define OHCI1394_selfIDComplete 0x00010000 | |
| 127 | #define OHCI1394_busReset 0x00020000 | |
| 75f7832e | 128 | #define OHCI1394_regAccessFail 0x00040000 |
| 5e20c282 SR |
129 | #define OHCI1394_phy 0x00080000 |
| 130 | #define OHCI1394_cycleSynch 0x00100000 | |
| 131 | #define OHCI1394_cycle64Seconds 0x00200000 | |
| 132 | #define OHCI1394_cycleLost 0x00400000 | |
| 133 | #define OHCI1394_cycleInconsistent 0x00800000 | |
| 134 | #define OHCI1394_unrecoverableError 0x01000000 | |
| 135 | #define OHCI1394_cycleTooLong 0x02000000 | |
| 136 | #define OHCI1394_phyRegRcvd 0x04000000 | |
| 137 | #define OHCI1394_masterIntEnable 0x80000000 | |
| ed568912 KH |
138 | |
| 139 | #define OHCI1394_evt_no_status 0x0 | |
| 140 | #define OHCI1394_evt_long_packet 0x2 | |
| 141 | #define OHCI1394_evt_missing_ack 0x3 | |
| 142 | #define OHCI1394_evt_underrun 0x4 | |
| 143 | #define OHCI1394_evt_overrun 0x5 | |
| 144 | #define OHCI1394_evt_descriptor_read 0x6 | |
| 145 | #define OHCI1394_evt_data_read 0x7 | |
| 146 | #define OHCI1394_evt_data_write 0x8 | |
| 147 | #define OHCI1394_evt_bus_reset 0x9 | |
| 148 | #define OHCI1394_evt_timeout 0xa | |
| 149 | #define OHCI1394_evt_tcode_err 0xb | |
| 150 | #define OHCI1394_evt_reserved_b 0xc | |
| 151 | #define OHCI1394_evt_reserved_c 0xd | |
| 152 | #define OHCI1394_evt_unknown 0xe | |
| 153 | #define OHCI1394_evt_flushed 0xf | |
| 154 | ||
| 155 | #define OHCI1394_phy_tcode 0xe | |
| 156 | ||
| 77c9a5da | 157 | #endif /* _FIREWIRE_OHCI_H */ |