[linux.git] / drivers / ide / trm290.c

/*
 *  Copyright (c) 1997-1998  Mark Lord
 *  Copyright (c) 2007       MontaVista Software, Inc. <[email protected]>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  June 22, 2004 - get rid of check_region
 *                   - Jesper Juhl
 *
 */

/*
 * This module provides support for the bus-master IDE DMA function
 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
 * including a "Precision Instruments" board.  The TRM290 pre-dates
 * the sff-8038 standard (ide-dma.c) by a few months, and differs
 * significantly enough to warrant separate routines for some functions,
 * while re-using others from ide-dma.c.
 *
 * EXPERIMENTAL!  It works for me (a sample of one).
 *
 * Works reliably for me in DMA mode (READs only),
 * DMA WRITEs are disabled by default (see #define below);
 *
 * DMA is not enabled automatically for this chipset,
 * but can be turned on manually (with "hdparm -d1") at run time.
 *
 * I need volunteers with "spare" drives for further testing
 * and development, and maybe to help figure out the peculiarities.
 * Even knowing the registers (below), some things behave strangely.
 */

#define TRM290_NO_DMA_WRITES	/* DMA writes seem unreliable sometimes */

/*
 * TRM-290 PCI-IDE2 Bus Master Chip
 * ================================
 * The configuration registers are addressed in normal I/O port space
 * and are used as follows:
 *
 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
 *
 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
 *	bit7 must always be written as "1"
 *	bits6-2 undefined
 *	bit1 1=legacy_compatible_mode, 0=native_pci_mode
 *	bit0 1=test_mode, 0=normal(default)
 *
 * trm290_base+2 when READ: status register (byte, read-only)
 *	bits7-2 undefined
 *	bit1 channel0 busmaster interrupt status 0=none, 1=asserted
 *	bit0 channel0 interrupt status 0=none, 1=asserted
 *
 * trm290_base+3 Interrupt mask register
 *	bits7-5 undefined
 *	bit4 legacy_header: 1=present, 0=absent
 *	bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
 *	bit2 channel1 interrupt status 0=none, 1=asserted (read only)
 *	bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
 *	bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
 *
 * trm290_base+1 "CPR" Config Pointer Register (byte)
 *	bit7 1=autoincrement CPR bits 2-0 after each access of CDR
 *	bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
 *	bit5 0=enabled master burst access (default), 1=disable  (write only)
 *	bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
 *	bit3 0=primary IDE channel, 1=secondary IDE channel
 *	bits2-0 register index for accesses through CDR port
 *
 * trm290_base+0 "CDR" Config Data Register (word)
 *	two sets of seven config registers,
 *	selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
 *	each index defined below:
 *
 * Index-0 Base address register for command block (word)
 *	defaults: 0x1f0 for primary, 0x170 for secondary
 *
 * Index-1 general config register (byte)
 *	bit7 1=DMA enable, 0=DMA disable
 *	bit6 1=activate IDE_RESET, 0=no action (default)
 *	bit5 1=enable IORDY, 0=disable IORDY (default)
 *	bit4 0=16-bit data port(default), 1=8-bit (XT) data port
 *	bit3 interrupt polarity: 1=active_low, 0=active_high(default)
 *	bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
 *	bit1 bus_master_mode(?): 1=enable, 0=disable(default)
 *	bit0 enable_io_ports: 1=enable(default), 0=disable
 *
 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
 *	bits7-0 bits7-0 of readahead count
 *
 * Index-3 read-ahead config register (byte, write only)
 *	bit7 1=enable_readahead, 0=disable_readahead(default)
 *	bit6 1=clear_FIFO, 0=no_action
 *	bit5 undefined
 *	bit4 mode4 timing control: 1=enable, 0=disable(default)
 *	bit3 undefined
 *	bit2 undefined
 *	bits1-0 bits9-8 of read-ahead count
 *
 * Index-4 base address register for control block (word)
 *	defaults: 0x3f6 for primary, 0x376 for secondary
 *
 * Index-5 data port timings (shared by both drives) (byte)
 *	standard PCI "clk" (clock) counts, default value = 0xf5
 *
 *	bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
 *	bits5-3 hold time:	000=1clk, 001=2clk, 010=3clk,
 *				011=4clk, 100=5clk, 101=6clk,
 *				110=8clk, 111=12clk
 *	bits2-0 active time:	000=2clk, 001=3clk, 010=4clk,
 *				011=5clk, 100=6clk, 101=8clk,
 *				110=12clk, 111=16clk
 *
 * Index-6 command/control port timings (shared by both drives) (byte)
 *	same layout as Index-5, default value = 0xde
 *
 * Suggested CDR programming for PIO mode0 (600ns):
 *	0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde	; primary
 *	0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde	; secondary
 *
 * Suggested CDR programming for PIO mode3 (180ns):
 *	0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde	; primary
 *	0x0170,0x21,0xff,0x80,0x0376,0x09,0xde	; secondary
 *
 * Suggested CDR programming for PIO mode4 (120ns):
 *	0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde	; primary
 *	0x0170,0x21,0xff,0x80,0x0376,0x00,0xde	; secondary
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "trm290"

static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = drive->hwif;
	u16 reg = 0;
	unsigned long flags;

	/* select PIO or DMA */
	reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);

	local_irq_save(flags);

	if (reg != hwif->select_data) {
		hwif->select_data = reg;
		/* set PIO/DMA */
		outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
		outw(reg & 0xff, hwif->config_data);
	}

	/* enable IRQ if not probing */
	if (drive->dev_flags & IDE_DFLAG_PRESENT) {
		reg = inw(hwif->config_data + 3);
		reg &= 0x13;
		reg &= ~(1 << hwif->channel);
		outw(reg, hwif->config_data + 3);
	}

	local_irq_restore(flags);
}

static void trm290_dev_select(ide_drive_t *drive)
{
	trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA));

	outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
}

static int trm290_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
{
	if (cmd->tf_flags & IDE_TFLAG_WRITE) {
#ifdef TRM290_NO_DMA_WRITES
		/* always use PIO for writes */
		return 1;
#endif
	}
	return 0;
}

static int trm290_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	unsigned int count, rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 1 : 2;

	count = ide_build_dmatable(drive, cmd);
	if (count == 0)
		/* try PIO instead of DMA */
		return 1;

	outl(hwif->dmatable_dma | rw, hwif->dma_base);
	/* start DMA */
	outw(count * 2 - 1, hwif->dma_base + 2);

	return 0;
}

static void trm290_dma_start(ide_drive_t *drive)
{
	trm290_prepare_drive(drive, 1);
}

static int trm290_dma_end(ide_drive_t *drive)
{
	u16 status = inw(drive->hwif->dma_base + 2);

	trm290_prepare_drive(drive, 0);

	return status != 0x00ff;
}

static int trm290_dma_test_irq(ide_drive_t *drive)
{
	u16 status = inw(drive->hwif->dma_base + 2);

	return status == 0x00ff;
}

static void trm290_dma_host_set(ide_drive_t *drive, int on)
{
}

static void init_hwif_trm290(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned int  cfg_base	= pci_resource_start(dev, 4);
	unsigned long flags;
	u8 reg = 0;

	if ((dev->class & 5) && cfg_base)
		printk(KERN_INFO DRV_NAME " %s: chip", pci_name(dev));
	else {
		cfg_base = 0x3df0;
		printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev));
	}
	printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
	hwif->config_data = cfg_base;
	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);

	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx\n",
	       hwif->name, hwif->dma_base, hwif->dma_base + 3);

	if (ide_allocate_dma_engine(hwif))
		return;

	local_irq_save(flags);
	/* put config reg into first byte of hwif->select_data */
	outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
	/* select PIO as default */
	hwif->select_data = 0x21;
	outb(hwif->select_data, hwif->config_data);
	/* get IRQ info */
	reg = inb(hwif->config_data + 3);
	/* mask IRQs for both ports */
	reg = (reg & 0x10) | 0x03;
	outb(reg, hwif->config_data + 3);
	local_irq_restore(flags);

	if (reg & 0x10)
		/* legacy mode */
		hwif->irq = hwif->channel ? 15 : 14;

#if 1
	{
	/*
	 * My trm290-based card doesn't seem to work with all possible values
	 * for the control basereg, so this kludge ensures that we use only
	 * values that are known to work.  Ugh.		-ml
	 */
		u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
		static u16 next_offset = 0;
		u8 old_mask;

		outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
		old = inw(hwif->config_data);
		old &= ~1;
		old_mask = inb(old + 2);
		if (old != compat && old_mask == 0xff) {
			/* leave lower 10 bits untouched */
			compat += (next_offset += 0x400);
			hwif->io_ports.ctl_addr = compat + 2;
			outw(compat | 1, hwif->config_data);
			new = inw(hwif->config_data);
			printk(KERN_INFO "%s: control basereg workaround: "
				"old=0x%04x, new=0x%04x\n",
				hwif->name, old, new & ~1);
		}
	}
#endif
}

static const struct ide_tp_ops trm290_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= trm290_dev_select,
	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static const struct ide_dma_ops trm290_dma_ops = {
	.dma_host_set		= trm290_dma_host_set,
	.dma_setup 		= trm290_dma_setup,
	.dma_start 		= trm290_dma_start,
	.dma_end		= trm290_dma_end,
	.dma_test_irq		= trm290_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_check		= trm290_dma_check,
};

static const struct ide_port_info trm290_chipset = {
	.name		= DRV_NAME,
	.init_hwif	= init_hwif_trm290,
	.tp_ops 	= &trm290_tp_ops,
	.dma_ops	= &trm290_dma_ops,
	.host_flags	= IDE_HFLAG_TRM290 |
			  IDE_HFLAG_NO_ATAPI_DMA |
#if 0 /* play it safe for now */
			  IDE_HFLAG_TRUST_BIOS_FOR_DMA |
#endif
			  IDE_HFLAG_NO_AUTODMA |
			  IDE_HFLAG_NO_LBA48,
};

static int trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &trm290_chipset, NULL);
}

static const struct pci_device_id trm290_pci_tbl[] = {
	{ PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);

static struct pci_driver trm290_pci_driver = {
	.name		= "TRM290_IDE",
	.id_table	= trm290_pci_tbl,
	.probe		= trm290_init_one,
	.remove		= ide_pci_remove,
};

static int __init trm290_ide_init(void)
{
	return ide_pci_register_driver(&trm290_pci_driver);
}

static void __exit trm290_ide_exit(void)
{
	pci_unregister_driver(&trm290_pci_driver);
}

module_init(trm290_ide_init);
module_exit(trm290_ide_exit);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (c) 1997-1998 Mark Lord
93c0b560	3	* Copyright (c) 2007 MontaVista Software, Inc. <[email protected]>
58f189fc	4	*
1da177e4 LT	5	* May be copied or modified under the terms of the GNU General Public License
	6	*
	7	* June 22, 2004 - get rid of check_region
59904159	8	* - Jesper Juhl
1da177e4 LT	9	*
	10	*/
	11
	12	/*
	13	* This module provides support for the bus-master IDE DMA function
	14	* of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
	15	* including a "Precision Instruments" board. The TRM290 pre-dates
	16	* the sff-8038 standard (ide-dma.c) by a few months, and differs
	17	* significantly enough to warrant separate routines for some functions,
	18	* while re-using others from ide-dma.c.
	19	*
	20	* EXPERIMENTAL! It works for me (a sample of one).
	21	*
	22	* Works reliably for me in DMA mode (READs only),
	23	* DMA WRITEs are disabled by default (see #define below);
	24	*
	25	* DMA is not enabled automatically for this chipset,
	26	* but can be turned on manually (with "hdparm -d1") at run time.
	27	*
	28	* I need volunteers with "spare" drives for further testing
	29	* and development, and maybe to help figure out the peculiarities.
	30	* Even knowing the registers (below), some things behave strangely.
	31	*/
	32
	33	#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
	34
	35	/*
	36	* TRM-290 PCI-IDE2 Bus Master Chip
	37	* ================================
	38	* The configuration registers are addressed in normal I/O port space
	39	* and are used as follows:
	40	*
	41	* trm290_base depends on jumper settings, and is probed for by ide-dma.c
	42	*
	43	* trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
	44	* bit7 must always be written as "1"
	45	* bits6-2 undefined
	46	* bit1 1=legacy_compatible_mode, 0=native_pci_mode
	47	* bit0 1=test_mode, 0=normal(default)
	48	*
	49	* trm290_base+2 when READ: status register (byte, read-only)
	50	* bits7-2 undefined
	51	* bit1 channel0 busmaster interrupt status 0=none, 1=asserted
	52	* bit0 channel0 interrupt status 0=none, 1=asserted
	53	*
	54	* trm290_base+3 Interrupt mask register
	55	* bits7-5 undefined
	56	* bit4 legacy_header: 1=present, 0=absent
	57	* bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
	58	* bit2 channel1 interrupt status 0=none, 1=asserted (read only)
	59	* bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
	60	* bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
	61	*
	62	* trm290_base+1 "CPR" Config Pointer Register (byte)
	63	* bit7 1=autoincrement CPR bits 2-0 after each access of CDR
	64	* bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
	65	* bit5 0=enabled master burst access (default), 1=disable (write only)
	66	* bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
	67	* bit3 0=primary IDE channel, 1=secondary IDE channel
	68	* bits2-0 register index for accesses through CDR port
	69	*
	70	* trm290_base+0 "CDR" Config Data Register (word)
	71	* two sets of seven config registers,
	72	* selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
73	* each index defined below:
74	*
75	* Index-0 Base address register for command block (word)
76	* defaults: 0x1f0 for primary, 0x170 for secondary
77	*
78	* Index-1 general config register (byte)
79	* bit7 1=DMA enable, 0=DMA disable
80	* bit6 1=activate IDE_RESET, 0=no action (default)
81	* bit5 1=enable IORDY, 0=disable IORDY (default)
82	* bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83	* bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84	* bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85	* bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86	* bit0 enable_io_ports: 1=enable(default), 0=disable
87	*
88	* Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89	* bits7-0 bits7-0 of readahead count
90	*
91	* Index-3 read-ahead config register (byte, write only)
92	* bit7 1=enable_readahead, 0=disable_readahead(default)
93	* bit6 1=clear_FIFO, 0=no_action
94	* bit5 undefined
95	* bit4 mode4 timing control: 1=enable, 0=disable(default)
96	* bit3 undefined
97	* bit2 undefined
98	* bits1-0 bits9-8 of read-ahead count
99	*
100	* Index-4 base address register for control block (word)
101	* defaults: 0x3f6 for primary, 0x376 for secondary
102	*
103	* Index-5 data port timings (shared by both drives) (byte)
104	* standard PCI "clk" (clock) counts, default value = 0xf5
105	*
106	* bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
107	* bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
108	* 011=4clk, 100=5clk, 101=6clk,
109	* 110=8clk, 111=12clk
110	* bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
111	* 011=5clk, 100=6clk, 101=8clk,
112	* 110=12clk, 111=16clk
113	*
114	* Index-6 command/control port timings (shared by both drives) (byte)
115	* same layout as Index-5, default value = 0xde
116	*
117	* Suggested CDR programming for PIO mode0 (600ns):
118	* 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
119	* 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
120	*
121	* Suggested CDR programming for PIO mode3 (180ns):
122	* 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
123	* 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
124	*
125	* Suggested CDR programming for PIO mode4 (120ns):
126	* 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
127	* 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
128	*
129	*/
130
1da177e4 LT	131	#include <linux/types.h>
	132	#include <linux/module.h>
	133	#include <linux/kernel.h>
1da177e4 LT	134	#include <linux/ioport.h>
	135	#include <linux/interrupt.h>
	136	#include <linux/blkdev.h>
	137	#include <linux/init.h>
1da177e4	138	#include <linux/pci.h>
1da177e4 LT	139	#include <linux/ide.h>
	140
	141	#include <asm/io.h>
	142
ced3ec8a BZ	143	#define DRV_NAME "trm290"
ced3ec8a BZ	144
1da177e4 LT	145	static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
1da177e4 LT	146	{
898ec223	147	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	148	u16 reg = 0;
	149	unsigned long flags;
	150
	151	/* select PIO or DMA */
	152	reg = use_dma ? (0x21 \| 0x82) : (0x21 & ~0x82);
	153
	154	local_irq_save(flags);
	155
	156	if (reg != hwif->select_data) {
	157	hwif->select_data = reg;
	158	/* set PIO/DMA */
0ecdca26 BZ	159	outb(0x51 \| (hwif->channel << 3), hwif->config_data + 1);
0ecdca26 BZ	160	outw(reg & 0xff, hwif->config_data);
1da177e4 LT	161	}
	162
	163	/* enable IRQ if not probing */
97100fc8	164	if (drive->dev_flags & IDE_DFLAG_PRESENT) {
0ecdca26	165	reg = inw(hwif->config_data + 3);
1da177e4 LT	166	reg &= 0x13;
1da177e4 LT	167	reg &= ~(1 << hwif->channel);
0ecdca26	168	outw(reg, hwif->config_data + 3);
1da177e4 LT	169	}
	170
	171	local_irq_restore(flags);
	172	}
	173
abb596b2	174	static void trm290_dev_select(ide_drive_t *drive)
1da177e4	175	{
97100fc8	176	trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
abb596b2 SS	177
abb596b2 SS	178	outb(drive->select \| ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
1da177e4 LT	179	}
1da177e4 LT	180
8a4a5738	181	static int trm290_dma_check(ide_drive_t drive, struct ide_cmd cmd)
1da177e4	182	{
22981694	183	if (cmd->tf_flags & IDE_TFLAG_WRITE) {
1da177e4 LT	184	#ifdef TRM290_NO_DMA_WRITES
1da177e4 LT	185	/* always use PIO for writes */
1da177e4 LT	186	return 1;
1da177e4 LT	187	#endif
8a4a5738 BZ	188	}
	189	return 0;
	190	}
	191
	192	static int trm290_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
	193	{
	194	ide_hwif_t *hwif = drive->hwif;
	195	unsigned int count, rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 1 : 2;
1da177e4	196
22981694	197	count = ide_build_dmatable(drive, cmd);
11998b31	198	if (count == 0)
1da177e4	199	/* try PIO instead of DMA */
1da177e4	200	return 1;
11998b31	201
4e5a68ae	202	outl(hwif->dmatable_dma \| rw, hwif->dma_base);
1da177e4	203	/* start DMA */
4e5a68ae	204	outw(count * 2 - 1, hwif->dma_base + 2);
88b4132e	205
1da177e4 LT	206	return 0;
	207	}
	208
93c0b560	209	static void trm290_dma_start(ide_drive_t *drive)
1da177e4	210	{
7526efaa	211	trm290_prepare_drive(drive, 1);
1da177e4 LT	212	}
1da177e4 LT	213
5e37bdc0	214	static int trm290_dma_end(ide_drive_t *drive)
1da177e4	215	{
88b4132e	216	u16 status = inw(drive->hwif->dma_base + 2);
898ec223	217
7526efaa BZ	218	trm290_prepare_drive(drive, 0);
7526efaa BZ	219
4e5a68ae	220	return status != 0x00ff;
1da177e4 LT	221	}
1da177e4 LT	222
5e37bdc0	223	static int trm290_dma_test_irq(ide_drive_t *drive)
1da177e4	224	{
898ec223	225	u16 status = inw(drive->hwif->dma_base + 2);
1da177e4	226
4e5a68ae	227	return status == 0x00ff;
1da177e4	228	}
1da177e4	229
15ce926a	230	static void trm290_dma_host_set(ide_drive_t *drive, int on)
93c0b560 SS	231	{
	232	}
	233
fe31edc8	234	static void init_hwif_trm290(ide_hwif_t *hwif)
1da177e4	235	{
36501650	236	struct pci_dev *dev = to_pci_dev(hwif->dev);
4e5a68ae	237	unsigned int cfg_base = pci_resource_start(dev, 4);
1da177e4 LT	238	unsigned long flags;
1da177e4 LT	239	u8 reg = 0;
1da177e4	240
4e5a68ae	241	if ((dev->class & 5) && cfg_base)
ced3ec8a	242	printk(KERN_INFO DRV_NAME " %s: chip", pci_name(dev));
4e5a68ae SS	243	else {
4e5a68ae SS	244	cfg_base = 0x3df0;
ced3ec8a	245	printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev));
4e5a68ae SS	246	}
	247	printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
	248	hwif->config_data = cfg_base;
	249	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);
	250
b8e73fba	251	printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
4e5a68ae SS	252	hwif->name, hwif->dma_base, hwif->dma_base + 3);
4e5a68ae SS	253
b8e73fba	254	if (ide_allocate_dma_engine(hwif))
4e5a68ae	255	return;
1da177e4 LT	256
	257	local_irq_save(flags);
	258	/* put config reg into first byte of hwif->select_data */
0ecdca26	259	outb(0x51 \| (hwif->channel << 3), hwif->config_data + 1);
1da177e4 LT	260	/* select PIO as default */
1da177e4 LT	261	hwif->select_data = 0x21;
0ecdca26	262	outb(hwif->select_data, hwif->config_data);
1da177e4	263	/* get IRQ info */
0ecdca26	264	reg = inb(hwif->config_data + 3);
1da177e4 LT	265	/* mask IRQs for both ports */
1da177e4 LT	266	reg = (reg & 0x10) \| 0x03;
0ecdca26	267	outb(reg, hwif->config_data + 3);
1da177e4 LT	268	local_irq_restore(flags);
1da177e4 LT	269
4e5a68ae	270	if (reg & 0x10)
1da177e4 LT	271	/* legacy mode */
1da177e4 LT	272	hwif->irq = hwif->channel ? 15 : 14;
1da177e4	273
1da177e4 LT	274	#if 1
	275	{
	276	/*
	277	* My trm290-based card doesn't seem to work with all possible values
	278	* for the control basereg, so this kludge ensures that we use only
	279	* values that are known to work. Ugh. -ml
	280	*/
	281	u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
	282	static u16 next_offset = 0;
	283	u8 old_mask;
	284
0ecdca26 BZ	285	outb(0x54 \| (hwif->channel << 3), hwif->config_data + 1);
0ecdca26 BZ	286	old = inw(hwif->config_data);
1da177e4	287	old &= ~1;
0ecdca26	288	old_mask = inb(old + 2);
1da177e4 LT	289	if (old != compat && old_mask == 0xff) {
	290	/* leave lower 10 bits untouched */
	291	compat += (next_offset += 0x400);
4c3032d8	292	hwif->io_ports.ctl_addr = compat + 2;
0ecdca26 BZ	293	outw(compat \| 1, hwif->config_data);
0ecdca26 BZ	294	new = inw(hwif->config_data);
1da177e4 LT	295	printk(KERN_INFO "%s: control basereg workaround: "
	296	"old=0x%04x, new=0x%04x\n",
	297	hwif->name, old, new & ~1);
	298	}
	299	}
	300	#endif
	301	}
	302
abb596b2 SS	303	static const struct ide_tp_ops trm290_tp_ops = {
	304	.exec_command = ide_exec_command,
	305	.read_status = ide_read_status,
	306	.read_altstatus = ide_read_altstatus,
	307	.write_devctl = ide_write_devctl,
	308
	309	.dev_select = trm290_dev_select,
	310	.tf_load = ide_tf_load,
	311	.tf_read = ide_tf_read,
	312
	313	.input_data = ide_input_data,
	314	.output_data = ide_output_data,
ac95beed BZ	315	};
ac95beed BZ	316
b5a608fb	317	static const struct ide_dma_ops trm290_dma_ops = {
5e37bdc0 BZ	318	.dma_host_set = trm290_dma_host_set,
5e37bdc0 BZ	319	.dma_setup = trm290_dma_setup,
5e37bdc0 BZ	320	.dma_start = trm290_dma_start,
	321	.dma_end = trm290_dma_end,
	322	.dma_test_irq = trm290_dma_test_irq,
f37afdac	323	.dma_lost_irq = ide_dma_lost_irq,
8a4a5738	324	.dma_check = trm290_dma_check,
5e37bdc0 BZ	325	};
5e37bdc0 BZ	326
fe31edc8	327	static const struct ide_port_info trm290_chipset = {
ced3ec8a	328	.name = DRV_NAME,
1da177e4	329	.init_hwif = init_hwif_trm290,
abb596b2	330	.tp_ops = &trm290_tp_ops,
5e37bdc0	331	.dma_ops = &trm290_dma_ops,
1f66019b BZ	332	.host_flags = IDE_HFLAG_TRM290 \|
1f66019b BZ	333	IDE_HFLAG_NO_ATAPI_DMA \|
9ff6f72f	334	#if 0 /* play it safe for now */
7cab14a7	335	IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
9ff6f72f	336	#endif
47b68788	337	IDE_HFLAG_NO_AUTODMA \|
238e4f14	338	IDE_HFLAG_NO_LBA48,
1da177e4 LT	339	};
1da177e4 LT	340
fe31edc8	341	static int trm290_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	342	{
6cdf6eb3	343	return ide_pci_init_one(dev, &trm290_chipset, NULL);
1da177e4 LT	344	}
1da177e4 LT	345
9cbcc5e3 BZ	346	static const struct pci_device_id trm290_pci_tbl[] = {
9cbcc5e3 BZ	347	{ PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
1da177e4 LT	348	{ 0, },
	349	};
	350	MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
	351
a9ab09e2	352	static struct pci_driver trm290_pci_driver = {
1da177e4 LT	353	.name = "TRM290_IDE",
	354	.id_table = trm290_pci_tbl,
	355	.probe = trm290_init_one,
fc2c32b7	356	.remove = ide_pci_remove,
1da177e4 LT	357	};
1da177e4 LT	358
82ab1eec	359	static int __init trm290_ide_init(void)
1da177e4	360	{
a9ab09e2	361	return ide_pci_register_driver(&trm290_pci_driver);
1da177e4 LT	362	}
1da177e4 LT	363
fc2c32b7 BZ	364	static void __exit trm290_ide_exit(void)
fc2c32b7 BZ	365	{
a9ab09e2	366	pci_unregister_driver(&trm290_pci_driver);
fc2c32b7 BZ	367	}
fc2c32b7 BZ	368
1da177e4	369	module_init(trm290_ide_init);
fc2c32b7	370	module_exit(trm290_ide_exit);
1da177e4 LT	371
	372	MODULE_AUTHOR("Mark Lord");
	373	MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
	374	MODULE_LICENSE("GPL");