[linux.git] / drivers / pci / setup-res.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Support routines for initializing a PCI subsystem
 *
 * Extruded from code written by
 *      Dave Rusling ([email protected])
 *      David Mosberger ([email protected])
 *	David Miller ([email protected])
 *
 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <[email protected]>
 *
 * Nov 2000, Ivan Kokshaysky <[email protected]>
 *	     Resource sorting
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"

static void pci_std_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	bool disable;
	u16 cmd;
	u32 new, check, mask;
	int reg;
	struct resource *res = dev->resource + resno;

	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
	if (dev->is_virtfn)
		return;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	if (res->flags & IORESOURCE_UNSET)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev->bus, &region, res);
	new = region.start;

	if (res->flags & IORESOURCE_IO) {
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
		new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
	} else if (resno == PCI_ROM_RESOURCE) {
		mask = PCI_ROM_ADDRESS_MASK;
	} else {
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
		new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
	}

	if (resno < PCI_ROM_RESOURCE) {
		reg = PCI_BASE_ADDRESS_0 + 4 * resno;
	} else if (resno == PCI_ROM_RESOURCE) {

		/*
		 * Apparently some Matrox devices have ROM BARs that read
		 * as zero when disabled, so don't update ROM BARs unless
		 * they're enabled.  See https://lkml.org/lkml/2005/8/30/138.
		 */
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;

		reg = dev->rom_base_reg;
		new |= PCI_ROM_ADDRESS_ENABLE;
	} else
		return;

	/*
	 * We can't update a 64-bit BAR atomically, so when possible,
	 * disable decoding so that a half-updated BAR won't conflict
	 * with another device.
	 */
	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	if (disable) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		pci_write_config_word(dev, PCI_COMMAND,
				      cmd & ~PCI_COMMAND_MEMORY);
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
				resno, new, check);
		}
	}

	if (disable)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
}

void pci_update_resource(struct pci_dev *dev, int resno)
{
	if (resno <= PCI_ROM_RESOURCE)
		pci_std_update_resource(dev, resno);
#ifdef CONFIG_PCI_IOV
	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		pci_iov_update_resource(dev, resno);
#endif
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	if (res->flags & IORESOURCE_UNSET) {
		pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
			 resource, res);
		return -EINVAL;
	}

	/*
	 * If we have a shadow copy in RAM, the PCI device doesn't respond
	 * to the shadow range, so we don't need to claim it, and upstream
	 * bridges don't need to route the range to the device.
	 */
	if (res->flags & IORESOURCE_ROM_SHADOW)
		return 0;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
			 resource, res);
		res->flags |= IORESOURCE_UNSET;
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
			 resource, res, conflict->name, conflict);
		res->flags |= IORESOURCE_UNSET;
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return -ENOMEM;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;
	res->flags &= ~IORESOURCE_UNSET;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
			 resno, res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		res->flags |= IORESOURCE_UNSET;
		return -EBUSY;
	}
	return 0;
}

/*
 * We don't have to worry about legacy ISA devices, so nothing to do here.
 * This is marked as __weak because multiple architectures define it; it should
 * eventually go away.
 */
resource_size_t __weak pcibios_align_resource(void *data,
					      const struct resource *res,
					      resource_size_t size,
					      resource_size_t align)
{
       return res->start;
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/*
	 * First, try exact prefetching match.  Even if a 64-bit
	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
	 * prefetchable resource in it because pbus_size_mem() assumes a
	 * 64-bit window will contain no 32-bit resources.  If we assign
	 * things differently than they were sized, not everything will fit.
	 */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
				     pcibios_align_resource, dev);
	if (ret == 0)
		return 0;

	/*
	 * If the prefetchable window is only 32 bits wide, we can put
	 * 64-bit prefetchable resources in it.
	 */
	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
		ret = pci_bus_alloc_resource(bus, res, size, align, min,
					     IORESOURCE_PREFETCH,
					     pcibios_align_resource, dev);
		if (ret == 0)
			return 0;
	}

	/*
	 * If we didn't find a better match, we can put any memory resource
	 * in a non-prefetchable window.  If this resource is 32 bits and
	 * non-prefetchable, the first call already tried the only possibility
	 * so we don't need to try again.
	 */
	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);

	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno,
				resource_size_t size, resource_size_t min_align)
{
	struct pci_bus *bus;
	int ret;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	int ret;

	if (res->flags & IORESOURCE_PCI_FIXED)
		return 0;

	res->flags |= IORESOURCE_UNSET;
	align = pci_resource_alignment(dev, res);
	if (!align) {
		pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
			 resno, res);
		return -EINVAL;
	}

	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0) {
		pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
		ret = pci_revert_fw_address(res, dev, resno, size);
	}

	if (ret < 0) {
		pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}
EXPORT_SYMBOL(pci_assign_resource);

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	unsigned long flags;
	resource_size_t new_size;
	int ret;

	if (res->flags & IORESOURCE_PCI_FIXED)
		return 0;

	flags = res->flags;
	res->flags |= IORESOURCE_UNSET;
	if (!res->parent) {
		pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
			 resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (ret) {
		res->flags = flags;
		pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
			 resno, res, (unsigned long long) addsize);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
		 resno, res, (unsigned long long) addsize);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}

void pci_release_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;

	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);

	if (!res->parent)
		return;

	release_resource(res);
	res->end = resource_size(res) - 1;
	res->start = 0;
	res->flags |= IORESOURCE_UNSET;
}
EXPORT_SYMBOL(pci_release_resource);

int pci_resize_resource(struct pci_dev *dev, int resno, int size)
{
	struct resource *res = dev->resource + resno;
	int old, ret;
	u32 sizes;
	u16 cmd;

	/* Make sure the resource isn't assigned before resizing it. */
	if (!(res->flags & IORESOURCE_UNSET))
		return -EBUSY;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_MEMORY)
		return -EBUSY;

	sizes = pci_rebar_get_possible_sizes(dev, resno);
	if (!sizes)
		return -ENOTSUPP;

	if (!(sizes & BIT(size)))
		return -EINVAL;

	old = pci_rebar_get_current_size(dev, resno);
	if (old < 0)
		return old;

	ret = pci_rebar_set_size(dev, resno, size);
	if (ret)
		return ret;

	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;

	/* Check if the new config works by trying to assign everything. */
	ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
	if (ret)
		goto error_resize;

	return 0;

error_resize:
	pci_rebar_set_size(dev, resno, old);
	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
	return ret;
}
EXPORT_SYMBOL(pci_resize_resource);

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (r->flags & IORESOURCE_UNSET) {
			pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
				i, r);
			return -EINVAL;
		}

		if (!r->parent) {
			pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
				i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
df62ab5e	3	* Support routines for initializing a PCI subsystem
1da177e4 LT	4	*
	5	* Extruded from code written by
	6	* Dave Rusling ([email protected])
	7	* David Mosberger ([email protected])
	8	* David Miller ([email protected])
	9	*
df62ab5e BH	10	* Fixed for multiple PCI buses, 1999 Andrea Arcangeli <[email protected]>
df62ab5e BH	11	*
1da177e4 LT	12	* Nov 2000, Ivan Kokshaysky <[email protected]>
	13	* Resource sorting
	14	*/
	15
1da177e4	16	#include <linux/kernel.h>
363c75db	17	#include <linux/export.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/errno.h>
	20	#include <linux/ioport.h>
	21	#include <linux/cache.h>
	22	#include <linux/slab.h>
	23	#include "pci.h"
	24
6ffa2489	25	static void pci_std_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	26	{
1da177e4 LT	27	struct pci_bus_region region;
9aac537e BH	28	bool disable;
9aac537e BH	29	u16 cmd;
1da177e4 LT	30	u32 new, check, mask;
1da177e4 LT	31	int reg;
14add80b	32	struct resource *res = dev->resource + resno;
1da177e4	33
63880b23 BH	34	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
63880b23 BH	35	if (dev->is_virtfn)
70675e0b	36	return;
70675e0b	37
fb0f2b40 RB	38	/*
	39	* Ignore resources for unimplemented BARs and unused resource slots
	40	* for 64 bit BARs.
	41	*/
cf7bee5a IK	42	if (!res->flags)
	43	return;
	44
cd8a4d36 BH	45	if (res->flags & IORESOURCE_UNSET)
	46	return;
	47
fb0f2b40 RB	48	/*
	49	* Ignore non-moveable resources. This might be legacy resources for
	50	* which no functional BAR register exists or another important
80ccba11	51	* system resource we shouldn't move around.
fb0f2b40 RB	52	*/
	53	if (res->flags & IORESOURCE_PCI_FIXED)
	54	return;
	55
fc279850	56	pcibios_resource_to_bus(dev->bus, &region, res);
45d004f4	57	new = region.start;
1da177e4	58
45d004f4	59	if (res->flags & IORESOURCE_IO) {
1da177e4	60	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
45d004f4 BH	61	new \|= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
45d004f4 BH	62	} else if (resno == PCI_ROM_RESOURCE) {
76dc5268	63	mask = PCI_ROM_ADDRESS_MASK;
45d004f4	64	} else {
1da177e4	65	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
45d004f4 BH	66	new \|= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
45d004f4 BH	67	}
1da177e4	68
286c2378 BH	69	if (resno < PCI_ROM_RESOURCE) {
	70	reg = PCI_BASE_ADDRESS_0 + 4 * resno;
	71	} else if (resno == PCI_ROM_RESOURCE) {
0b457dde BH	72
	73	/*
	74	* Apparently some Matrox devices have ROM BARs that read
	75	* as zero when disabled, so don't update ROM BARs unless
	76	* they're enabled. See https://lkml.org/lkml/2005/8/30/138.
	77	*/
755528c8 LT	78	if (!(res->flags & IORESOURCE_ROM_ENABLE))
755528c8 LT	79	return;
286c2378 BH	80
286c2378 BH	81	reg = dev->rom_base_reg;
755528c8	82	new \|= PCI_ROM_ADDRESS_ENABLE;
286c2378 BH	83	} else
286c2378 BH	84	return;
1da177e4	85
9aac537e BH	86	/*
	87	* We can't update a 64-bit BAR atomically, so when possible,
	88	* disable decoding so that a half-updated BAR won't conflict
	89	* with another device.
	90	*/
	91	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	92	if (disable) {
	93	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	94	pci_write_config_word(dev, PCI_COMMAND,
	95	cmd & ~PCI_COMMAND_MEMORY);
	96	}
	97
1da177e4 LT	98	pci_write_config_dword(dev, reg, new);
	99	pci_read_config_dword(dev, reg, &check);
	100
	101	if ((new ^ check) & mask) {
7506dc79	102	pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11	103	resno, new, check);
1da177e4 LT	104	}
1da177e4 LT	105
28c6821a	106	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	107	new = region.start >> 16 >> 16;
1da177e4 LT	108	pci_write_config_dword(dev, reg + 4, new);
	109	pci_read_config_dword(dev, reg + 4, &check);
	110	if (check != new) {
7506dc79	111	pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
227f0647	112	resno, new, check);
1da177e4 LT	113	}
1da177e4 LT	114	}
9aac537e BH	115
	116	if (disable)
	117	pci_write_config_word(dev, PCI_COMMAND, cmd);
1da177e4 LT	118	}
1da177e4 LT	119
6ffa2489 BH	120	void pci_update_resource(struct pci_dev *dev, int resno)
	121	{
	122	if (resno <= PCI_ROM_RESOURCE)
	123	pci_std_update_resource(dev, resno);
	124	#ifdef CONFIG_PCI_IOV
	125	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	126	pci_iov_update_resource(dev, resno);
	127	#endif
	128	}
	129
96bde06a	130	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	131	{
1da177e4 LT	132	struct resource *res = &dev->resource[resource];
966f3a75	133	struct resource root, conflict;
1da177e4	134
29003beb	135	if (res->flags & IORESOURCE_UNSET) {
7506dc79	136	pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
29003beb BH	137	resource, res);
	138	return -EINVAL;
	139	}
	140
16d917b1 BH	141	/*
	142	* If we have a shadow copy in RAM, the PCI device doesn't respond
	143	* to the shadow range, so we don't need to claim it, and upstream
	144	* bridges don't need to route the range to the device.
	145	*/
	146	if (res->flags & IORESOURCE_ROM_SHADOW)
	147	return 0;
	148
cebd78a8	149	root = pci_find_parent_resource(dev, res);
865df576	150	if (!root) {
7506dc79	151	pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
29003beb	152	resource, res);
c770cb4c	153	res->flags \|= IORESOURCE_UNSET;
865df576	154	return -EINVAL;
1da177e4 LT	155	}
1da177e4 LT	156
966f3a75 BH	157	conflict = request_resource_conflict(root, res);
966f3a75 BH	158	if (conflict) {
7506dc79	159	pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
29003beb	160	resource, res, conflict->name, conflict);
c770cb4c	161	res->flags \|= IORESOURCE_UNSET;
966f3a75 BH	162	return -EBUSY;
966f3a75 BH	163	}
865df576	164
966f3a75	165	return 0;
1da177e4	166	}
eaa959df	167	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	168
32a9a682 YS	169	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	170	{
32a9a682 YS	171	/* MMIO Base/Limit */
	172	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	173
	174	/* Prefetchable MMIO Base/Limit */
	175	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	176	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	177	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	178	}
2bbc6942	179
6535943f MS	180	/*
	181	* Generic function that returns a value indicating that the device's
	182	* original BIOS BAR address was not saved and so is not available for
	183	* reinstatement.
	184	*
	185	* Can be over-ridden by architecture specific code that implements
	186	* reinstatement functionality rather than leaving it disabled when
	187	* normal allocation attempts fail.
	188	*/
	189	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	190	{
	191	return 0;
	192	}
	193
f7625980	194	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
2bbc6942 RP	195	int resno, resource_size_t size)
	196	{
	197	struct resource root, conflict;
6535943f	198	resource_size_t fw_addr, start, end;
58c84eda	199
6535943f MS	200	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
6535943f MS	201	if (!fw_addr)
94778835	202	return -ENOMEM;
6535943f	203
2bbc6942 RP	204	start = res->start;
2bbc6942 RP	205	end = res->end;
6535943f	206	res->start = fw_addr;
2bbc6942	207	res->end = res->start + size - 1;
0b26cd69	208	res->flags &= ~IORESOURCE_UNSET;
351fc6d1 MS	209
	210	root = pci_find_parent_resource(dev, res);
	211	if (!root) {
	212	if (res->flags & IORESOURCE_IO)
	213	root = &ioport_resource;
	214	else
	215	root = &iomem_resource;
	216	}
	217
7506dc79	218	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
2bbc6942 RP	219	resno, res);
	220	conflict = request_resource_conflict(root, res);
	221	if (conflict) {
7506dc79	222	pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
94778835	223	resno, res, conflict->name, conflict);
2bbc6942 RP	224	res->start = start;
2bbc6942 RP	225	res->end = end;
0b26cd69	226	res->flags \|= IORESOURCE_UNSET;
94778835	227	return -EBUSY;
2bbc6942	228	}
94778835	229	return 0;
2bbc6942 RP	230	}
2bbc6942 RP	231
ecf677c8 PD	232	/*
	233	* We don't have to worry about legacy ISA devices, so nothing to do here.
	234	* This is marked as __weak because multiple architectures define it; it should
	235	* eventually go away.
	236	*/
	237	resource_size_t __weak pcibios_align_resource(void *data,
	238	const struct resource *res,
	239	resource_size_t size,
	240	resource_size_t align)
	241	{
	242	return res->start;
	243	}
	244
fe6dacdb BH	245	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	246	int resno, resource_size_t size, resource_size_t align)
	247	{
	248	struct resource *res = dev->resource + resno;
	249	resource_size_t min;
	250	int ret;
	251
	252	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	253
67d29b5c BH	254	/*
	255	* First, try exact prefetching match. Even if a 64-bit
	256	* prefetchable bridge window is below 4GB, we can't put a 32-bit
	257	* prefetchable resource in it because pbus_size_mem() assumes a
	258	* 64-bit window will contain no 32-bit resources. If we assign
	259	* things differently than they were sized, not everything will fit.
	260	*/
fe6dacdb	261	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415	262	IORESOURCE_PREFETCH \| IORESOURCE_MEM_64,
fe6dacdb	263	pcibios_align_resource, dev);
d3689df0 BH	264	if (ret == 0)
d3689df0 BH	265	return 0;
fe6dacdb	266
67d29b5c BH	267	/*
	268	* If the prefetchable window is only 32 bits wide, we can put
	269	* 64-bit prefetchable resources in it.
	270	*/
d3689df0	271	if ((res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) ==
5b285415	272	(IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) {
5b285415 YL	273	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415 YL	274	IORESOURCE_PREFETCH,
fe6dacdb	275	pcibios_align_resource, dev);
d3689df0 BH	276	if (ret == 0)
d3689df0 BH	277	return 0;
fe6dacdb	278	}
5b285415	279
67d29b5c BH	280	/*
	281	* If we didn't find a better match, we can put any memory resource
	282	* in a non-prefetchable window. If this resource is 32 bits and
	283	* non-prefetchable, the first call already tried the only possibility
	284	* so we don't need to try again.
	285	*/
	286	if (res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64))
fe6dacdb BH	287	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
fe6dacdb BH	288	pcibios_align_resource, dev);
67d29b5c	289
fe6dacdb BH	290	return ret;
	291	}
	292
d6776e6d NR	293	static int _pci_assign_resource(struct pci_dev *dev, int resno,
d6776e6d NR	294	resource_size_t size, resource_size_t min_align)
2bbc6942	295	{
2bbc6942 RP	296	struct pci_bus *bus;
2bbc6942 RP	297	int ret;
58c84eda	298
2bbc6942 RP	299	bus = dev->bus;
	300	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	301	if (!bus->parent \|\| !bus->self->transparent)
	302	break;
	303	bus = bus->parent;
	304	}
	305
2bbc6942 RP	306	return ret;
	307	}
	308
d09ee968 YL	309	int pci_assign_resource(struct pci_dev *dev, int resno)
	310	{
	311	struct resource *res = dev->resource + resno;
2bbc6942	312	resource_size_t align, size;
d09ee968 YL	313	int ret;
d09ee968 YL	314
2ea4adf7 BH	315	if (res->flags & IORESOURCE_PCI_FIXED)
	316	return 0;
	317
bd064f0a	318	res->flags \|= IORESOURCE_UNSET;
6faf17f6	319	align = pci_resource_alignment(dev, res);
d09ee968	320	if (!align) {
7506dc79	321	pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
227f0647	322	resno, res);
d09ee968 YL	323	return -EINVAL;
	324	}
	325
2bbc6942 RP	326	size = resource_size(res);
2bbc6942 RP	327	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	328
2bbc6942 RP	329	/*
	330	* If we failed to assign anything, let's try the address
	331	* where firmware left it. That at least has a chance of
	332	* working, which is better than just leaving it disabled.
	333	*/
64da465e	334	if (ret < 0) {
7506dc79	335	pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
2bbc6942	336	ret = pci_revert_fw_address(res, dev, resno, size);
64da465e	337	}
d09ee968	338
64da465e	339	if (ret < 0) {
7506dc79	340	pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
28f6dbe2	341	return ret;
64da465e	342	}
28f6dbe2 BH	343
	344	res->flags &= ~IORESOURCE_UNSET;
	345	res->flags &= ~IORESOURCE_STARTALIGN;
7506dc79	346	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
28f6dbe2 BH	347	if (resno < PCI_BRIDGE_RESOURCES)
	348	pci_update_resource(dev, resno);
	349
	350	return 0;
d09ee968	351	}
b7fe9434	352	EXPORT_SYMBOL(pci_assign_resource);
d09ee968	353
fe6dacdb BH	354	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	355	resource_size_t min_align)
	356	{
	357	struct resource *res = dev->resource + resno;
c3337708	358	unsigned long flags;
fe6dacdb BH	359	resource_size_t new_size;
	360	int ret;
	361
2ea4adf7 BH	362	if (res->flags & IORESOURCE_PCI_FIXED)
	363	return 0;
	364
c3337708	365	flags = res->flags;
bd064f0a	366	res->flags \|= IORESOURCE_UNSET;
fe6dacdb	367	if (!res->parent) {
7506dc79	368	pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
227f0647	369	resno, res);
fe6dacdb BH	370	return -EINVAL;
	371	}
	372
	373	/* already aligned with min_align */
	374	new_size = resource_size(res) + addsize;
	375	ret = _pci_assign_resource(dev, resno, new_size, min_align);
28f6dbe2	376	if (ret) {
c3337708	377	res->flags = flags;
7506dc79	378	pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
c3337708	379	resno, res, (unsigned long long) addsize);
28f6dbe2	380	return ret;
fe6dacdb	381	}
c3337708	382
28f6dbe2 BH	383	res->flags &= ~IORESOURCE_UNSET;
28f6dbe2 BH	384	res->flags &= ~IORESOURCE_STARTALIGN;
7506dc79	385	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
64da465e	386	resno, res, (unsigned long long) addsize);
28f6dbe2 BH	387	if (resno < PCI_BRIDGE_RESOURCES)
	388	pci_update_resource(dev, resno);
	389
	390	return 0;
fe6dacdb BH	391	}
fe6dacdb BH	392
8bb705e3 CK	393	void pci_release_resource(struct pci_dev *dev, int resno)
	394	{
	395	struct resource *res = dev->resource + resno;
	396
7506dc79	397	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
c37406e0 CK	398
	399	if (!res->parent)
	400	return;
	401
8bb705e3 CK	402	release_resource(res);
	403	res->end = resource_size(res) - 1;
	404	res->start = 0;
	405	res->flags \|= IORESOURCE_UNSET;
	406	}
	407	EXPORT_SYMBOL(pci_release_resource);
	408
	409	int pci_resize_resource(struct pci_dev *dev, int resno, int size)
	410	{
	411	struct resource *res = dev->resource + resno;
	412	int old, ret;
	413	u32 sizes;
	414	u16 cmd;
	415
	416	/* Make sure the resource isn't assigned before resizing it. */
	417	if (!(res->flags & IORESOURCE_UNSET))
	418	return -EBUSY;
	419
	420	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	421	if (cmd & PCI_COMMAND_MEMORY)
	422	return -EBUSY;
	423
	424	sizes = pci_rebar_get_possible_sizes(dev, resno);
	425	if (!sizes)
	426	return -ENOTSUPP;
	427
	428	if (!(sizes & BIT(size)))
	429	return -EINVAL;
	430
	431	old = pci_rebar_get_current_size(dev, resno);
	432	if (old < 0)
	433	return old;
	434
	435	ret = pci_rebar_set_size(dev, resno, size);
	436	if (ret)
	437	return ret;
	438
	439	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
	440
	441	/* Check if the new config works by trying to assign everything. */
	442	ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
	443	if (ret)
	444	goto error_resize;
	445
	446	return 0;
	447
	448	error_resize:
	449	pci_rebar_set_size(dev, resno, old);
	450	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
	451	return ret;
	452	}
	453	EXPORT_SYMBOL(pci_resize_resource);
	454
842de40d BH	455	int pci_enable_resources(struct pci_dev *dev, int mask)
	456	{
	457	u16 cmd, old_cmd;
	458	int i;
	459	struct resource *r;
	460
	461	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	462	old_cmd = cmd;
	463
	464	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	465	if (!(mask & (1 << i)))
	466	continue;
	467
	468	r = &dev->resource[i];
	469
	470	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	471	continue;
	472	if ((i == PCI_ROM_RESOURCE) &&
	473	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	474	continue;
	475
3cedcc36	476	if (r->flags & IORESOURCE_UNSET) {
7506dc79	477	pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
3cedcc36 BH	478	i, r);
	479	return -EINVAL;
	480	}
	481
842de40d	482	if (!r->parent) {
7506dc79	483	pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
3cedcc36	484	i, r);
842de40d BH	485	return -EINVAL;
	486	}
	487
	488	if (r->flags & IORESOURCE_IO)
	489	cmd \|= PCI_COMMAND_IO;
	490	if (r->flags & IORESOURCE_MEM)
	491	cmd \|= PCI_COMMAND_MEMORY;
	492	}
	493
	494	if (cmd != old_cmd) {
7506dc79	495	pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
842de40d BH	496	pci_write_config_word(dev, PCI_COMMAND, cmd);
	497	}
	498	return 0;
	499	}