[linux.git] / drivers / gpio / gpio-cs5535.c

/*
 * AMD CS5535/CS5536 GPIO driver
 * Copyright (C) 2006  Advanced Micro Devices, Inc.
 * Copyright (C) 2007-2009  Andres Salomon <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/cs5535.h>
#include <asm/msr.h>

#define DRV_NAME "cs5535-gpio"

/*
 * Some GPIO pins
 *  31-29,23 : reserved (always mask out)
 *  28       : Power Button
 *  26       : PME#
 *  22-16    : LPC
 *  14,15    : SMBus
 *  9,8      : UART1
 *  7        : PCI INTB
 *  3,4      : UART2/DDC
 *  2        : IDE_IRQ0
 *  1        : AC_BEEP
 *  0        : PCI INTA
 *
 * If a mask was not specified, allow all except
 * reserved and Power Button
 */
#define GPIO_DEFAULT_MASK 0x0F7FFFFF

static ulong mask = GPIO_DEFAULT_MASK;
module_param_named(mask, mask, ulong, 0444);
MODULE_PARM_DESC(mask, "GPIO channel mask.");

/*
 * FIXME: convert this singleton driver to use the state container
 * design pattern, see Documentation/driver-model/design-patterns.txt
 */
static struct cs5535_gpio_chip {
	struct gpio_chip chip;
	resource_size_t base;

	struct platform_device *pdev;
	spinlock_t lock;
} cs5535_gpio_chip;

/*
 * The CS5535/CS5536 GPIOs support a number of extra features not defined
 * by the gpio_chip API, so these are exported.  For a full list of the
 * registers, see include/linux/cs5535.h.
 */

static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
		unsigned int reg)
{
	unsigned long addr = chip->base + 0x80 + reg;

	/*
	 * According to the CS5536 errata (#36), after suspend
	 * a write to the high bank GPIO register will clear all
	 * non-selected bits; the recommended workaround is a
	 * read-modify-write operation.
	 *
	 * Don't apply this errata to the edge status GPIOs, as writing
	 * to their lower bits will clear them.
	 */
	if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
		if (val & 0xffff)
			val |= (inl(addr) & 0xffff); /* ignore the high bits */
		else
			val |= (inl(addr) ^ (val >> 16));
	}
	outl(val, addr);
}

static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
		unsigned int reg)
{
	if (offset < 16)
		/* low bank register */
		outl(1 << offset, chip->base + reg);
	else
		/* high bank register */
		errata_outl(chip, 1 << (offset - 16), reg);
}

void cs5535_gpio_set(unsigned offset, unsigned int reg)
{
	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	__cs5535_gpio_set(chip, offset, reg);
	spin_unlock_irqrestore(&chip->lock, flags);
}
EXPORT_SYMBOL_GPL(cs5535_gpio_set);

static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
		unsigned int reg)
{
	if (offset < 16)
		/* low bank register */
		outl(1 << (offset + 16), chip->base + reg);
	else
		/* high bank register */
		errata_outl(chip, 1 << offset, reg);
}

void cs5535_gpio_clear(unsigned offset, unsigned int reg)
{
	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	__cs5535_gpio_clear(chip, offset, reg);
	spin_unlock_irqrestore(&chip->lock, flags);
}
EXPORT_SYMBOL_GPL(cs5535_gpio_clear);

int cs5535_gpio_isset(unsigned offset, unsigned int reg)
{
	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	unsigned long flags;
	long val;

	spin_lock_irqsave(&chip->lock, flags);
	if (offset < 16)
		/* low bank register */
		val = inl(chip->base + reg);
	else {
		/* high bank register */
		val = inl(chip->base + 0x80 + reg);
		offset -= 16;
	}
	spin_unlock_irqrestore(&chip->lock, flags);

	return (val & (1 << offset)) ? 1 : 0;
}
EXPORT_SYMBOL_GPL(cs5535_gpio_isset);

int cs5535_gpio_set_irq(unsigned group, unsigned irq)
{
	uint32_t lo, hi;

	if (group > 7 || irq > 15)
		return -EINVAL;

	rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);

	lo &= ~(0xF << (group * 4));
	lo |= (irq & 0xF) << (group * 4);

	wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
	return 0;
}
EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);

void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
{
	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	uint32_t shift = (offset % 8) * 4;
	unsigned long flags;
	uint32_t val;

	if (offset >= 24)
		offset = GPIO_MAP_W;
	else if (offset >= 16)
		offset = GPIO_MAP_Z;
	else if (offset >= 8)
		offset = GPIO_MAP_Y;
	else
		offset = GPIO_MAP_X;

	spin_lock_irqsave(&chip->lock, flags);
	val = inl(chip->base + offset);

	/* Clear whatever was there before */
	val &= ~(0xF << shift);

	/* Set the new value */
	val |= ((pair & 7) << shift);

	/* Set the PME bit if this is a PME event */
	if (pme)
		val |= (1 << (shift + 3));

	outl(val, chip->base + offset);
	spin_unlock_irqrestore(&chip->lock, flags);
}
EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);

/*
 * Generic gpio_chip API support.
 */

static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
{
	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);

	/* check if this pin is available */
	if ((mask & (1 << offset)) == 0) {
		dev_info(&chip->pdev->dev,
			"pin %u is not available (check mask)\n", offset);
		spin_unlock_irqrestore(&chip->lock, flags);
		return -EINVAL;
	}

	/* disable output aux 1 & 2 on this pin */
	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);

	/* disable input aux 1 on this pin */
	__cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return cs5535_gpio_isset(offset, GPIO_READ_BACK);
}

static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	if (val)
		cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
	else
		cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
}

static int chip_direction_input(struct gpio_chip *c, unsigned offset)
{
	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
{
	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);

	__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
	__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
	if (val)
		__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
	else
		__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static const char * const cs5535_gpio_names[] = {
	"GPIO0", "GPIO1", "GPIO2", "GPIO3",
	"GPIO4", "GPIO5", "GPIO6", "GPIO7",
	"GPIO8", "GPIO9", "GPIO10", "GPIO11",
	"GPIO12", "GPIO13", "GPIO14", "GPIO15",
	"GPIO16", "GPIO17", "GPIO18", "GPIO19",
	"GPIO20", "GPIO21", "GPIO22", NULL,
	"GPIO24", "GPIO25", "GPIO26", "GPIO27",
	"GPIO28", NULL, NULL, NULL,
};

static struct cs5535_gpio_chip cs5535_gpio_chip = {
	.chip = {
		.owner = THIS_MODULE,
		.label = DRV_NAME,

		.base = 0,
		.ngpio = 32,
		.names = cs5535_gpio_names,
		.request = chip_gpio_request,

		.get = chip_gpio_get,
		.set = chip_gpio_set,

		.direction_input = chip_direction_input,
		.direction_output = chip_direction_output,
	},
};

static int cs5535_gpio_probe(struct platform_device *pdev)
{
	struct resource *res;
	int err = -EIO;
	ulong mask_orig = mask;

	/* There are two ways to get the GPIO base address; one is by
	 * fetching it from MSR_LBAR_GPIO, the other is by reading the
	 * PCI BAR info.  The latter method is easier (especially across
	 * different architectures), so we'll stick with that for now.  If
	 * it turns out to be unreliable in the face of crappy BIOSes, we
	 * can always go back to using MSRs.. */

	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	if (!res) {
		dev_err(&pdev->dev, "can't fetch device resource info\n");
		return err;
	}

	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
				 pdev->name)) {
		dev_err(&pdev->dev, "can't request region\n");
		return err;
	}

	/* set up the driver-specific struct */
	cs5535_gpio_chip.base = res->start;
	cs5535_gpio_chip.pdev = pdev;
	spin_lock_init(&cs5535_gpio_chip.lock);

	dev_info(&pdev->dev, "reserved resource region %pR\n", res);

	/* mask out reserved pins */
	mask &= 0x1F7FFFFF;

	/* do not allow pin 28, Power Button, as there's special handling
	 * in the PMC needed. (note 12, p. 48) */
	mask &= ~(1 << 28);

	if (mask_orig != mask)
		dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
				mask_orig, mask);

	/* finally, register with the generic GPIO API */
	err = devm_gpiochip_add_data(&pdev->dev, &cs5535_gpio_chip.chip,
				     &cs5535_gpio_chip);
	if (err)
		return err;

	return 0;
}

static struct platform_driver cs5535_gpio_driver = {
	.driver = {
		.name = DRV_NAME,
	},
	.probe = cs5535_gpio_probe,
};

module_platform_driver(cs5535_gpio_driver);

MODULE_AUTHOR("Andres Salomon <[email protected]>");
MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
5f0a96b0 AS	1	/*
	2	* AMD CS5535/CS5536 GPIO driver
	3	* Copyright (C) 2006 Advanced Micro Devices, Inc.
	4	* Copyright (C) 2007-2009 Andres Salomon <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of version 2 of the GNU General Public License
	8	* as published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/spinlock.h>
	13	#include <linux/module.h>
df966694	14	#include <linux/platform_device.h>
326a2926	15	#include <linux/gpio/driver.h>
5f0a96b0 AS	16	#include <linux/io.h>
5f0a96b0 AS	17	#include <linux/cs5535.h>
1b912c1b	18	#include <asm/msr.h>
5f0a96b0 AS	19
5f0a96b0 AS	20	#define DRV_NAME "cs5535-gpio"
5f0a96b0	21
1ea3fa7b TM	22	/*
	23	* Some GPIO pins
	24	* 31-29,23 : reserved (always mask out)
	25	* 28 : Power Button
	26	* 26 : PME#
	27	* 22-16 : LPC
	28	* 14,15 : SMBus
	29	* 9,8 : UART1
	30	* 7 : PCI INTB
	31	* 3,4 : UART2/DDC
	32	* 2 : IDE_IRQ0
	33	* 1 : AC_BEEP
	34	* 0 : PCI INTA
	35	*
	36	* If a mask was not specified, allow all except
	37	* reserved and Power Button
	38	*/
	39	#define GPIO_DEFAULT_MASK 0x0F7FFFFF
	40
	41	static ulong mask = GPIO_DEFAULT_MASK;
	42	module_param_named(mask, mask, ulong, 0444);
	43	MODULE_PARM_DESC(mask, "GPIO channel mask.");
	44
c634fc19 LW	45	/*
	46	* FIXME: convert this singleton driver to use the state container
	47	* design pattern, see Documentation/driver-model/design-patterns.txt
	48	*/
5f0a96b0 AS	49	static struct cs5535_gpio_chip {
	50	struct gpio_chip chip;
	51	resource_size_t base;
	52
df966694	53	struct platform_device *pdev;
5f0a96b0 AS	54	spinlock_t lock;
	55	} cs5535_gpio_chip;
	56
	57	/*
	58	* The CS5535/CS5536 GPIOs support a number of extra features not defined
	59	* by the gpio_chip API, so these are exported. For a full list of the
	60	* registers, see include/linux/cs5535.h.
	61	*/
	62
00185165 AS	63	static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
00185165 AS	64	unsigned int reg)
853ff883	65	{
00185165 AS	66	unsigned long addr = chip->base + 0x80 + reg;
00185165 AS	67
853ff883 AS	68	/*
	69	* According to the CS5536 errata (#36), after suspend
	70	* a write to the high bank GPIO register will clear all
	71	* non-selected bits; the recommended workaround is a
	72	* read-modify-write operation.
00185165 AS	73	*
	74	* Don't apply this errata to the edge status GPIOs, as writing
	75	* to their lower bits will clear them.
853ff883	76	*/
44658a11 AS	77	if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
	78	if (val & 0xffff)
	79	val \|= (inl(addr) & 0xffff); /* ignore the high bits */
	80	else
	81	val \|= (inl(addr) ^ (val >> 16));
	82	}
853ff883 AS	83	outl(val, addr);
	84	}
	85
5f0a96b0 AS	86	static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
	87	unsigned int reg)
	88	{
	89	if (offset < 16)
	90	/* low bank register */
	91	outl(1 << offset, chip->base + reg);
	92	else
	93	/* high bank register */
00185165	94	errata_outl(chip, 1 << (offset - 16), reg);
5f0a96b0 AS	95	}
	96
	97	void cs5535_gpio_set(unsigned offset, unsigned int reg)
	98	{
	99	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	100	unsigned long flags;
	101
	102	spin_lock_irqsave(&chip->lock, flags);
	103	__cs5535_gpio_set(chip, offset, reg);
	104	spin_unlock_irqrestore(&chip->lock, flags);
	105	}
	106	EXPORT_SYMBOL_GPL(cs5535_gpio_set);
	107
	108	static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
	109	unsigned int reg)
	110	{
	111	if (offset < 16)
	112	/* low bank register */
	113	outl(1 << (offset + 16), chip->base + reg);
	114	else
	115	/* high bank register */
00185165	116	errata_outl(chip, 1 << offset, reg);
5f0a96b0 AS	117	}
	118
	119	void cs5535_gpio_clear(unsigned offset, unsigned int reg)
	120	{
	121	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	122	unsigned long flags;
	123
	124	spin_lock_irqsave(&chip->lock, flags);
	125	__cs5535_gpio_clear(chip, offset, reg);
	126	spin_unlock_irqrestore(&chip->lock, flags);
	127	}
	128	EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
	129
	130	int cs5535_gpio_isset(unsigned offset, unsigned int reg)
	131	{
	132	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	133	unsigned long flags;
	134	long val;
	135
	136	spin_lock_irqsave(&chip->lock, flags);
	137	if (offset < 16)
	138	/* low bank register */
	139	val = inl(chip->base + reg);
	140	else {
	141	/* high bank register */
	142	val = inl(chip->base + 0x80 + reg);
	143	offset -= 16;
	144	}
	145	spin_unlock_irqrestore(&chip->lock, flags);
	146
	147	return (val & (1 << offset)) ? 1 : 0;
	148	}
	149	EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
	150
1b912c1b AS	151	int cs5535_gpio_set_irq(unsigned group, unsigned irq)
	152	{
	153	uint32_t lo, hi;
	154
	155	if (group > 7 \|\| irq > 15)
	156	return -EINVAL;
	157
	158	rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
	159
	160	lo &= ~(0xF << (group * 4));
	161	lo \|= (irq & 0xF) << (group * 4);
	162
	163	wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
	164	return 0;
	165	}
	166	EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
	167
	168	void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
	169	{
	170	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
	171	uint32_t shift = (offset % 8) * 4;
	172	unsigned long flags;
	173	uint32_t val;
	174
	175	if (offset >= 24)
	176	offset = GPIO_MAP_W;
	177	else if (offset >= 16)
	178	offset = GPIO_MAP_Z;
	179	else if (offset >= 8)
	180	offset = GPIO_MAP_Y;
	181	else
	182	offset = GPIO_MAP_X;
	183
	184	spin_lock_irqsave(&chip->lock, flags);
	185	val = inl(chip->base + offset);
	186
	187	/* Clear whatever was there before */
	188	val &= ~(0xF << shift);
	189
	190	/* Set the new value */
	191	val \|= ((pair & 7) << shift);
	192
	193	/* Set the PME bit if this is a PME event */
	194	if (pme)
	195	val \|= (1 << (shift + 3));
	196
	197	outl(val, chip->base + offset);
	198	spin_unlock_irqrestore(&chip->lock, flags);
	199	}
	200	EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
	201
5f0a96b0 AS	202	/*
	203	* Generic gpio_chip API support.
	204	*/
	205
1ea3fa7b TM	206	static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
1ea3fa7b TM	207	{
c634fc19	208	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
1ea3fa7b TM	209	unsigned long flags;
	210
	211	spin_lock_irqsave(&chip->lock, flags);
	212
	213	/* check if this pin is available */
	214	if ((mask & (1 << offset)) == 0) {
	215	dev_info(&chip->pdev->dev,
	216	"pin %u is not available (check mask)\n", offset);
	217	spin_unlock_irqrestore(&chip->lock, flags);
	218	return -EINVAL;
	219	}
	220
	221	/* disable output aux 1 & 2 on this pin */
	222	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
	223	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
	224
	225	/* disable input aux 1 on this pin */
	226	__cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
	227
	228	spin_unlock_irqrestore(&chip->lock, flags);
	229
	230	return 0;
	231	}
	232
5f0a96b0 AS	233	static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
5f0a96b0 AS	234	{
a8a5164c	235	return cs5535_gpio_isset(offset, GPIO_READ_BACK);
5f0a96b0 AS	236	}
	237
	238	static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	239	{
	240	if (val)
	241	cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
	242	else
	243	cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
	244	}
	245
	246	static int chip_direction_input(struct gpio_chip *c, unsigned offset)
	247	{
c634fc19	248	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
5f0a96b0 AS	249	unsigned long flags;
	250
	251	spin_lock_irqsave(&chip->lock, flags);
	252	__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
a8a5164c	253	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
5f0a96b0 AS	254	spin_unlock_irqrestore(&chip->lock, flags);
	255
	256	return 0;
	257	}
	258
	259	static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
	260	{
c634fc19	261	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
5f0a96b0 AS	262	unsigned long flags;
	263
	264	spin_lock_irqsave(&chip->lock, flags);
	265
a8a5164c	266	__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
5f0a96b0 AS	267	__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
	268	if (val)
	269	__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
	270	else
	271	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
	272
	273	spin_unlock_irqrestore(&chip->lock, flags);
	274
	275	return 0;
	276	}
	277
62154991	278	static const char * const cs5535_gpio_names[] = {
1ea3fa7b TM	279	"GPIO0", "GPIO1", "GPIO2", "GPIO3",
	280	"GPIO4", "GPIO5", "GPIO6", "GPIO7",
	281	"GPIO8", "GPIO9", "GPIO10", "GPIO11",
	282	"GPIO12", "GPIO13", "GPIO14", "GPIO15",
	283	"GPIO16", "GPIO17", "GPIO18", "GPIO19",
	284	"GPIO20", "GPIO21", "GPIO22", NULL,
	285	"GPIO24", "GPIO25", "GPIO26", "GPIO27",
	286	"GPIO28", NULL, NULL, NULL,
	287	};
	288
5f0a96b0 AS	289	static struct cs5535_gpio_chip cs5535_gpio_chip = {
	290	.chip = {
	291	.owner = THIS_MODULE,
	292	.label = DRV_NAME,
	293
	294	.base = 0,
1ea3fa7b TM	295	.ngpio = 32,
	296	.names = cs5535_gpio_names,
	297	.request = chip_gpio_request,
5f0a96b0 AS	298
	299	.get = chip_gpio_get,
	300	.set = chip_gpio_set,
	301
	302	.direction_input = chip_direction_input,
	303	.direction_output = chip_direction_output,
	304	},
	305	};
	306
3836309d	307	static int cs5535_gpio_probe(struct platform_device *pdev)
5f0a96b0	308	{
df966694 AS	309	struct resource *res;
df966694 AS	310	int err = -EIO;
1ea3fa7b	311	ulong mask_orig = mask;
5f0a96b0 AS	312
	313	/* There are two ways to get the GPIO base address; one is by
	314	* fetching it from MSR_LBAR_GPIO, the other is by reading the
	315	* PCI BAR info. The latter method is easier (especially across
	316	* different architectures), so we'll stick with that for now. If
	317	* it turns out to be unreliable in the face of crappy BIOSes, we
	318	* can always go back to using MSRs.. */
	319
df966694 AS	320	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	321	if (!res) {
	322	dev_err(&pdev->dev, "can't fetch device resource info\n");
85bd84f5	323	return err;
5f0a96b0 AS	324	}
5f0a96b0 AS	325
3eebd613 PG	326	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
3eebd613 PG	327	pdev->name)) {
df966694	328	dev_err(&pdev->dev, "can't request region\n");
85bd84f5	329	return err;
5f0a96b0 AS	330	}
	331
	332	/* set up the driver-specific struct */
df966694	333	cs5535_gpio_chip.base = res->start;
5f0a96b0 AS	334	cs5535_gpio_chip.pdev = pdev;
	335	spin_lock_init(&cs5535_gpio_chip.lock);
	336
1db0b427	337	dev_info(&pdev->dev, "reserved resource region %pR\n", res);
5f0a96b0	338
1ea3fa7b TM	339	/* mask out reserved pins */
	340	mask &= 0x1F7FFFFF;
	341
	342	/* do not allow pin 28, Power Button, as there's special handling
	343	* in the PMC needed. (note 12, p. 48) */
	344	mask &= ~(1 << 28);
	345
	346	if (mask_orig != mask)
	347	dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
	348	mask_orig, mask);
	349
5f0a96b0	350	/* finally, register with the generic GPIO API */
85bd84f5 LD	351	err = devm_gpiochip_add_data(&pdev->dev, &cs5535_gpio_chip.chip,
85bd84f5 LD	352	&cs5535_gpio_chip);
1ea3fa7b	353	if (err)
85bd84f5	354	return err;
5f0a96b0	355
df966694	356	return 0;
5f0a96b0 AS	357	}
5f0a96b0 AS	358
36885ff0	359	static struct platform_driver cs5535_gpio_driver = {
df966694 AS	360	.driver = {
df966694 AS	361	.name = DRV_NAME,
df966694 AS	362	},
df966694 AS	363	.probe = cs5535_gpio_probe,
df966694	364	};
5f0a96b0	365
6f61415e	366	module_platform_driver(cs5535_gpio_driver);
5f0a96b0	367
d45840d9	368	MODULE_AUTHOR("Andres Salomon <[email protected]>");
5f0a96b0 AS	369	MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
5f0a96b0 AS	370	MODULE_LICENSE("GPL");
ec9d0cf5	371	MODULE_ALIAS("platform:" DRV_NAME);