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ASoC: wm_adsp: Simplify kcontrol handling
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
6ab2b7b4 24#include <linux/workqueue.h>
2159ad93
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/jack.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include <linux/mfd/arizona/registers.h>
34
dc91428a 35#include "arizona.h"
2159ad93
MB		 36#include "wm_adsp.h"
37
38#define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40#define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46#define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48
49#define ADSP1_CONTROL_1 0x00
50#define ADSP1_CONTROL_2 0x02
51#define ADSP1_CONTROL_3 0x03
52#define ADSP1_CONTROL_4 0x04
53#define ADSP1_CONTROL_5 0x06
54#define ADSP1_CONTROL_6 0x07
55#define ADSP1_CONTROL_7 0x08
56#define ADSP1_CONTROL_8 0x09
57#define ADSP1_CONTROL_9 0x0A
58#define ADSP1_CONTROL_10 0x0B
59#define ADSP1_CONTROL_11 0x0C
60#define ADSP1_CONTROL_12 0x0D
61#define ADSP1_CONTROL_13 0x0F
62#define ADSP1_CONTROL_14 0x10
63#define ADSP1_CONTROL_15 0x11
64#define ADSP1_CONTROL_16 0x12
65#define ADSP1_CONTROL_17 0x13
66#define ADSP1_CONTROL_18 0x14
67#define ADSP1_CONTROL_19 0x16
68#define ADSP1_CONTROL_20 0x17
69#define ADSP1_CONTROL_21 0x18
70#define ADSP1_CONTROL_22 0x1A
71#define ADSP1_CONTROL_23 0x1B
72#define ADSP1_CONTROL_24 0x1C
73#define ADSP1_CONTROL_25 0x1E
74#define ADSP1_CONTROL_26 0x20
75#define ADSP1_CONTROL_27 0x21
76#define ADSP1_CONTROL_28 0x22
77#define ADSP1_CONTROL_29 0x23
78#define ADSP1_CONTROL_30 0x24
79#define ADSP1_CONTROL_31 0x26
80
81/*
82 * ADSP1 Control 19
83 */
84#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87
88
89/*
90 * ADSP1 Control 30
91 */
92#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
100#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
104#define ADSP1_START 0x0001 /* DSP1_START */
105#define ADSP1_START_MASK 0x0001 /* DSP1_START */
106#define ADSP1_START_SHIFT 0 /* DSP1_START */
107#define ADSP1_START_WIDTH 1 /* DSP1_START */
108
94e205bf
CR		 109/*
110 * ADSP1 Control 31
111 */
112#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
114#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
115
2d30b575
MB		 116#define ADSP2_CONTROL 0x0
117#define ADSP2_CLOCKING 0x1
118#define ADSP2_STATUS1 0x4
119#define ADSP2_WDMA_CONFIG_1 0x30
120#define ADSP2_WDMA_CONFIG_2 0x31
121#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93
MB		 122
123/*
124 * ADSP2 Control
125 */
126
127#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
128#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
129#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
130#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
131#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
132#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
133#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
134#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
135#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
136#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
137#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
138#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
139#define ADSP2_START 0x0001 /* DSP1_START */
140#define ADSP2_START_MASK 0x0001 /* DSP1_START */
141#define ADSP2_START_SHIFT 0 /* DSP1_START */
142#define ADSP2_START_WIDTH 1 /* DSP1_START */
143
973838a0
MB		 144/*
145 * ADSP2 clocking
146 */
147#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
148#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
149#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
150
2159ad93
MB		 151/*
152 * ADSP2 Status 1
153 */
154#define ADSP2_RAM_RDY 0x0001
155#define ADSP2_RAM_RDY_MASK 0x0001
156#define ADSP2_RAM_RDY_SHIFT 0
157#define ADSP2_RAM_RDY_WIDTH 1
158
cf17c83c
MB		 159struct wm_adsp_buf {
160 struct list_head list;
161 void *buf;
162};
163
164static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
165 struct list_head *list)
166{
167 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
168
169 if (buf == NULL)
170 return NULL;
171
172 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
173 if (!buf->buf) {
174 kfree(buf);
175 return NULL;
176 }
177
178 if (list)
179 list_add_tail(&buf->list, list);
180
181 return buf;
182}
183
184static void wm_adsp_buf_free(struct list_head *list)
185{
186 while (!list_empty(list)) {
187 struct wm_adsp_buf *buf = list_first_entry(list,
188 struct wm_adsp_buf,
189 list);
190 list_del(&buf->list);
191 kfree(buf->buf);
192 kfree(buf);
193 }
194}
195
36e8fe99 196#define WM_ADSP_NUM_FW 4
1023dbd9 197
dd84f925
MB		 198#define WM_ADSP_FW_MBC_VSS 0
199#define WM_ADSP_FW_TX 1
200#define WM_ADSP_FW_TX_SPK 2
201#define WM_ADSP_FW_RX_ANC 3
202
1023dbd9 203static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
dd84f925
MB		 204 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
205 [WM_ADSP_FW_TX] = "Tx",
206 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
207 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
1023dbd9
MB		 208};
209
210static struct {
211 const char *file;
212} wm_adsp_fw[WM_ADSP_NUM_FW] = {
dd84f925
MB		 213 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
214 [WM_ADSP_FW_TX] = { .file = "tx" },
215 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
216 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
1023dbd9
MB		 217};
218
6ab2b7b4
DP		 219struct wm_coeff_ctl_ops {
220 int (*xget)(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *ucontrol);
222 int (*xput)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xinfo)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_info *uinfo);
226};
227
6ab2b7b4
DP		 228struct wm_coeff_ctl {
229 const char *name;
81ad93ec 230 struct snd_soc_card *card;
6ab2b7b4
DP		 231 struct wm_adsp_alg_region region;
232 struct wm_coeff_ctl_ops ops;
233 struct wm_adsp *adsp;
234 void *private;
235 unsigned int enabled:1;
236 struct list_head list;
237 void *cache;
238 size_t len;
0c2e3f34 239 unsigned int set:1;
6ab2b7b4
DP		 240 struct snd_kcontrol *kcontrol;
241};
242
1023dbd9
MB		 243static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
244 struct snd_ctl_elem_value *ucontrol)
245{
246 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
247 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
248 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
249
250 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
251
252 return 0;
253}
254
255static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
256 struct snd_ctl_elem_value *ucontrol)
257{
258 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
259 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
260 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
261
262 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
263 return 0;
264
265 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
266 return -EINVAL;
267
268 if (adsp[e->shift_l].running)
269 return -EBUSY;
270
31522764 271 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9
MB		 272
273 return 0;
274}
275
276static const struct soc_enum wm_adsp_fw_enum[] = {
277 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
278 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
279 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
280 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
281};
282
b6ed61cf 283const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
1023dbd9
MB		 284 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
285 wm_adsp_fw_get, wm_adsp_fw_put),
286 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
287 wm_adsp_fw_get, wm_adsp_fw_put),
288 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
289 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf
MB		 290};
291EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
292
293#if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
294static const struct soc_enum wm_adsp2_rate_enum[] = {
dc91428a
MB		 295 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
296 ARIZONA_DSP1_RATE_SHIFT, 0xf,
297 ARIZONA_RATE_ENUM_SIZE,
298 arizona_rate_text, arizona_rate_val),
299 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
300 ARIZONA_DSP1_RATE_SHIFT, 0xf,
301 ARIZONA_RATE_ENUM_SIZE,
302 arizona_rate_text, arizona_rate_val),
303 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
304 ARIZONA_DSP1_RATE_SHIFT, 0xf,
305 ARIZONA_RATE_ENUM_SIZE,
306 arizona_rate_text, arizona_rate_val),
5be9c5b4 307 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
dc91428a
MB		 308 ARIZONA_DSP1_RATE_SHIFT, 0xf,
309 ARIZONA_RATE_ENUM_SIZE,
310 arizona_rate_text, arizona_rate_val),
311};
312
b6ed61cf 313const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
1023dbd9
MB		 314 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
315 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 316 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
1023dbd9
MB		 317 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
318 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 319 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
1023dbd9
MB		 320 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
321 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 322 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
1023dbd9
MB		 323 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
324 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 325 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
1023dbd9 326};
b6ed61cf
MB		 327EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
328#endif
2159ad93
MB		 329
330static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
331 int type)
332{
333 int i;
334
335 for (i = 0; i < dsp->num_mems; i++)
336 if (dsp->mem[i].type == type)
337 return &dsp->mem[i];
338
339 return NULL;
340}
341
45b9ee72
MB		 342static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
343 unsigned int offset)
344{
345 switch (region->type) {
346 case WMFW_ADSP1_PM:
347 return region->base + (offset * 3);
348 case WMFW_ADSP1_DM:
349 return region->base + (offset * 2);
350 case WMFW_ADSP2_XM:
351 return region->base + (offset * 2);
352 case WMFW_ADSP2_YM:
353 return region->base + (offset * 2);
354 case WMFW_ADSP1_ZM:
355 return region->base + (offset * 2);
356 default:
357 WARN_ON(NULL != "Unknown memory region type");
358 return offset;
359 }
360}
361
6ab2b7b4
DP		 362static int wm_coeff_info(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_info *uinfo)
364{
365 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
366
367 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
368 uinfo->count = ctl->len;
369 return 0;
370}
371
372static int wm_coeff_write_control(struct snd_kcontrol *kcontrol,
373 const void *buf, size_t len)
374{
6ab2b7b4
DP		 375 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
376 struct wm_adsp_alg_region *region = &ctl->region;
377 const struct wm_adsp_region *mem;
378 struct wm_adsp *adsp = ctl->adsp;
379 void *scratch;
380 int ret;
381 unsigned int reg;
382
383 mem = wm_adsp_find_region(adsp, region->type);
384 if (!mem) {
385 adsp_err(adsp, "No base for region %x\n",
386 region->type);
387 return -EINVAL;
388 }
389
390 reg = ctl->region.base;
391 reg = wm_adsp_region_to_reg(mem, reg);
392
393 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
394 if (!scratch)
395 return -ENOMEM;
396
81ad93ec 397 ret = regmap_raw_write(adsp->regmap, reg, scratch,
6ab2b7b4
DP		 398 ctl->len);
399 if (ret) {
400 adsp_err(adsp, "Failed to write %zu bytes to %x\n",
401 ctl->len, reg);
402 kfree(scratch);
403 return ret;
404 }
405
406 kfree(scratch);
407
408 return 0;
409}
410
411static int wm_coeff_put(struct snd_kcontrol *kcontrol,
412 struct snd_ctl_elem_value *ucontrol)
413{
414 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
415 char *p = ucontrol->value.bytes.data;
416
417 memcpy(ctl->cache, p, ctl->len);
418
419 if (!ctl->enabled) {
0c2e3f34 420 ctl->set = 1;
6ab2b7b4
DP		 421 return 0;
422 }
423
424 return wm_coeff_write_control(kcontrol, p, ctl->len);
425}
426
427static int wm_coeff_read_control(struct snd_kcontrol *kcontrol,
428 void *buf, size_t len)
429{
6ab2b7b4
DP		 430 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
431 struct wm_adsp_alg_region *region = &ctl->region;
432 const struct wm_adsp_region *mem;
433 struct wm_adsp *adsp = ctl->adsp;
434 void *scratch;
435 int ret;
436 unsigned int reg;
437
438 mem = wm_adsp_find_region(adsp, region->type);
439 if (!mem) {
440 adsp_err(adsp, "No base for region %x\n",
441 region->type);
442 return -EINVAL;
443 }
444
445 reg = ctl->region.base;
446 reg = wm_adsp_region_to_reg(mem, reg);
447
448 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
449 if (!scratch)
450 return -ENOMEM;
451
81ad93ec 452 ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len);
6ab2b7b4
DP		 453 if (ret) {
454 adsp_err(adsp, "Failed to read %zu bytes from %x\n",
455 ctl->len, reg);
456 kfree(scratch);
457 return ret;
458 }
459
460 memcpy(buf, scratch, ctl->len);
461 kfree(scratch);
462
463 return 0;
464}
465
466static int wm_coeff_get(struct snd_kcontrol *kcontrol,
467 struct snd_ctl_elem_value *ucontrol)
468{
469 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
470 char *p = ucontrol->value.bytes.data;
471
472 memcpy(p, ctl->cache, ctl->len);
473 return 0;
474}
475
6ab2b7b4 476struct wmfw_ctl_work {
81ad93ec 477 struct wm_adsp *adsp;
6ab2b7b4
DP		 478 struct wm_coeff_ctl *ctl;
479 struct work_struct work;
480};
481
81ad93ec 482static int wmfw_add_ctl(struct wm_adsp *adsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 483{
484 struct snd_kcontrol_new *kcontrol;
485 int ret;
486
81ad93ec 487 if (!ctl || !ctl->name || !ctl->card)
6ab2b7b4
DP		 488 return -EINVAL;
489
490 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
491 if (!kcontrol)
492 return -ENOMEM;
493 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
494
495 kcontrol->name = ctl->name;
496 kcontrol->info = wm_coeff_info;
497 kcontrol->get = wm_coeff_get;
498 kcontrol->put = wm_coeff_put;
499 kcontrol->private_value = (unsigned long)ctl;
500
81ad93ec
DP		 501 ret = snd_soc_add_card_controls(ctl->card,
502 kcontrol, 1);
6ab2b7b4
DP		 503 if (ret < 0)
504 goto err_kcontrol;
505
506 kfree(kcontrol);
507
81ad93ec
DP		 508 ctl->kcontrol = snd_soc_card_get_kcontrol(ctl->card,
509 ctl->name);
510
511 list_add(&ctl->list, &adsp->ctl_list);
6ab2b7b4
DP		 512 return 0;
513
514err_kcontrol:
515 kfree(kcontrol);
516 return ret;
517}
518
2159ad93
MB		 519static int wm_adsp_load(struct wm_adsp *dsp)
520{
cf17c83c 521 LIST_HEAD(buf_list);
2159ad93
MB		 522 const struct firmware *firmware;
523 struct regmap *regmap = dsp->regmap;
524 unsigned int pos = 0;
525 const struct wmfw_header *header;
526 const struct wmfw_adsp1_sizes *adsp1_sizes;
527 const struct wmfw_adsp2_sizes *adsp2_sizes;
528 const struct wmfw_footer *footer;
529 const struct wmfw_region *region;
530 const struct wm_adsp_region *mem;
531 const char *region_name;
532 char *file, *text;
cf17c83c 533 struct wm_adsp_buf *buf;
2159ad93
MB		 534 unsigned int reg;
535 int regions = 0;
536 int ret, offset, type, sizes;
537
538 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
539 if (file == NULL)
540 return -ENOMEM;
541
1023dbd9
MB		 542 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
543 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 544 file[PAGE_SIZE - 1] = '\0';
545
546 ret = request_firmware(&firmware, file, dsp->dev);
547 if (ret != 0) {
548 adsp_err(dsp, "Failed to request '%s'\n", file);
549 goto out;
550 }
551 ret = -EINVAL;
552
553 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
554 if (pos >= firmware->size) {
555 adsp_err(dsp, "%s: file too short, %zu bytes\n",
556 file, firmware->size);
557 goto out_fw;
558 }
559
560 header = (void*)&firmware->data[0];
561
562 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
563 adsp_err(dsp, "%s: invalid magic\n", file);
564 goto out_fw;
565 }
566
567 if (header->ver != 0) {
568 adsp_err(dsp, "%s: unknown file format %d\n",
569 file, header->ver);
570 goto out_fw;
571 }
572
573 if (header->core != dsp->type) {
574 adsp_err(dsp, "%s: invalid core %d != %d\n",
575 file, header->core, dsp->type);
576 goto out_fw;
577 }
578
579 switch (dsp->type) {
580 case WMFW_ADSP1:
581 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
582 adsp1_sizes = (void *)&(header[1]);
583 footer = (void *)&(adsp1_sizes[1]);
584 sizes = sizeof(*adsp1_sizes);
585
586 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
587 file, le32_to_cpu(adsp1_sizes->dm),
588 le32_to_cpu(adsp1_sizes->pm),
589 le32_to_cpu(adsp1_sizes->zm));
590 break;
591
592 case WMFW_ADSP2:
593 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
594 adsp2_sizes = (void *)&(header[1]);
595 footer = (void *)&(adsp2_sizes[1]);
596 sizes = sizeof(*adsp2_sizes);
597
598 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
599 file, le32_to_cpu(adsp2_sizes->xm),
600 le32_to_cpu(adsp2_sizes->ym),
601 le32_to_cpu(adsp2_sizes->pm),
602 le32_to_cpu(adsp2_sizes->zm));
603 break;
604
605 default:
606 BUG_ON(NULL == "Unknown DSP type");
607 goto out_fw;
608 }
609
610 if (le32_to_cpu(header->len) != sizeof(*header) +
611 sizes + sizeof(*footer)) {
612 adsp_err(dsp, "%s: unexpected header length %d\n",
613 file, le32_to_cpu(header->len));
614 goto out_fw;
615 }
616
617 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
618 le64_to_cpu(footer->timestamp));
619
620 while (pos < firmware->size &&
621 pos - firmware->size > sizeof(*region)) {
622 region = (void *)&(firmware->data[pos]);
623 region_name = "Unknown";
624 reg = 0;
625 text = NULL;
626 offset = le32_to_cpu(region->offset) & 0xffffff;
627 type = be32_to_cpu(region->type) & 0xff;
628 mem = wm_adsp_find_region(dsp, type);
629
630 switch (type) {
631 case WMFW_NAME_TEXT:
632 region_name = "Firmware name";
633 text = kzalloc(le32_to_cpu(region->len) + 1,
634 GFP_KERNEL);
635 break;
636 case WMFW_INFO_TEXT:
637 region_name = "Information";
638 text = kzalloc(le32_to_cpu(region->len) + 1,
639 GFP_KERNEL);
640 break;
641 case WMFW_ABSOLUTE:
642 region_name = "Absolute";
643 reg = offset;
644 break;
645 case WMFW_ADSP1_PM:
646 BUG_ON(!mem);
647 region_name = "PM";
45b9ee72 648 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 649 break;
650 case WMFW_ADSP1_DM:
651 BUG_ON(!mem);
652 region_name = "DM";
45b9ee72 653 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 654 break;
655 case WMFW_ADSP2_XM:
656 BUG_ON(!mem);
657 region_name = "XM";
45b9ee72 658 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 659 break;
660 case WMFW_ADSP2_YM:
661 BUG_ON(!mem);
662 region_name = "YM";
45b9ee72 663 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 664 break;
665 case WMFW_ADSP1_ZM:
666 BUG_ON(!mem);
667 region_name = "ZM";
45b9ee72 668 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 669 break;
670 default:
671 adsp_warn(dsp,
672 "%s.%d: Unknown region type %x at %d(%x)\n",
673 file, regions, type, pos, pos);
674 break;
675 }
676
677 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
678 regions, le32_to_cpu(region->len), offset,
679 region_name);
680
681 if (text) {
682 memcpy(text, region->data, le32_to_cpu(region->len));
683 adsp_info(dsp, "%s: %s\n", file, text);
684 kfree(text);
685 }
686
687 if (reg) {
cf17c83c
MB		 688 buf = wm_adsp_buf_alloc(region->data,
689 le32_to_cpu(region->len),
690 &buf_list);
a76fefab
MB		 691 if (!buf) {
692 adsp_err(dsp, "Out of memory\n");
693 return -ENOMEM;
694 }
695
cf17c83c
MB		 696 ret = regmap_raw_write_async(regmap, reg, buf->buf,
697 le32_to_cpu(region->len));
2159ad93
MB		 698 if (ret != 0) {
699 adsp_err(dsp,
700 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
701 file, regions,
702 le32_to_cpu(region->len), offset,
703 region_name, ret);
704 goto out_fw;
705 }
706 }
707
708 pos += le32_to_cpu(region->len) + sizeof(*region);
709 regions++;
710 }
cf17c83c
MB		 711
712 ret = regmap_async_complete(regmap);
713 if (ret != 0) {
714 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
715 goto out_fw;
716 }
717
2159ad93
MB		 718 if (pos > firmware->size)
719 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
720 file, regions, pos - firmware->size);
721
722out_fw:
cf17c83c
MB		 723 regmap_async_complete(regmap);
724 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 725 release_firmware(firmware);
726out:
727 kfree(file);
728
729 return ret;
730}
731
81ad93ec 732static int wm_coeff_init_control_caches(struct wm_adsp *adsp)
6ab2b7b4
DP		 733{
734 struct wm_coeff_ctl *ctl;
735 int ret;
736
81ad93ec 737 list_for_each_entry(ctl, &adsp->ctl_list, list) {
0c2e3f34 738 if (!ctl->enabled || ctl->set)
6ab2b7b4
DP		 739 continue;
740 ret = wm_coeff_read_control(ctl->kcontrol,
741 ctl->cache,
742 ctl->len);
743 if (ret < 0)
744 return ret;
745 }
746
747 return 0;
748}
749
81ad93ec 750static int wm_coeff_sync_controls(struct wm_adsp *adsp)
6ab2b7b4
DP		 751{
752 struct wm_coeff_ctl *ctl;
753 int ret;
754
81ad93ec 755 list_for_each_entry(ctl, &adsp->ctl_list, list) {
6ab2b7b4
DP		 756 if (!ctl->enabled)
757 continue;
0c2e3f34 758 if (ctl->set) {
6ab2b7b4
DP		 759 ret = wm_coeff_write_control(ctl->kcontrol,
760 ctl->cache,
761 ctl->len);
762 if (ret < 0)
763 return ret;
6ab2b7b4
DP		 764 }
765 }
766
767 return 0;
768}
769
770static void wm_adsp_ctl_work(struct work_struct *work)
771{
772 struct wmfw_ctl_work *ctl_work = container_of(work,
773 struct wmfw_ctl_work,
774 work);
775
81ad93ec 776 wmfw_add_ctl(ctl_work->adsp, ctl_work->ctl);
6ab2b7b4
DP		 777 kfree(ctl_work);
778}
779
780static int wm_adsp_create_control(struct snd_soc_codec *codec,
781 const struct wm_adsp_alg_region *region)
782
783{
784 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
785 struct wm_coeff_ctl *ctl;
786 struct wmfw_ctl_work *ctl_work;
787 char *name;
788 char *region_name;
789 int ret;
790
791 name = kmalloc(PAGE_SIZE, GFP_KERNEL);
792 if (!name)
793 return -ENOMEM;
794
795 switch (region->type) {
796 case WMFW_ADSP1_PM:
797 region_name = "PM";
798 break;
799 case WMFW_ADSP1_DM:
800 region_name = "DM";
801 break;
802 case WMFW_ADSP2_XM:
803 region_name = "XM";
804 break;
805 case WMFW_ADSP2_YM:
806 region_name = "YM";
807 break;
808 case WMFW_ADSP1_ZM:
809 region_name = "ZM";
810 break;
811 default:
9dbce044
DC		 812 ret = -EINVAL;
813 goto err_name;
6ab2b7b4
DP		 814 }
815
816 snprintf(name, PAGE_SIZE, "DSP%d %s %x",
817 dsp->num, region_name, region->alg);
818
81ad93ec 819 list_for_each_entry(ctl, &dsp->ctl_list,
6ab2b7b4
DP		 820 list) {
821 if (!strcmp(ctl->name, name)) {
822 if (!ctl->enabled)
823 ctl->enabled = 1;
9dbce044 824 goto found;
6ab2b7b4
DP		 825 }
826 }
827
828 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
829 if (!ctl) {
830 ret = -ENOMEM;
831 goto err_name;
832 }
833 ctl->region = *region;
834 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
835 if (!ctl->name) {
836 ret = -ENOMEM;
837 goto err_ctl;
838 }
839 ctl->enabled = 1;
0c2e3f34 840 ctl->set = 0;
6ab2b7b4
DP		 841 ctl->ops.xget = wm_coeff_get;
842 ctl->ops.xput = wm_coeff_put;
81ad93ec 843 ctl->card = codec->card;
6ab2b7b4
DP		 844 ctl->adsp = dsp;
845
846 ctl->len = region->len;
847 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
848 if (!ctl->cache) {
849 ret = -ENOMEM;
850 goto err_ctl_name;
851 }
852
853 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
854 if (!ctl_work) {
855 ret = -ENOMEM;
856 goto err_ctl_cache;
857 }
858
81ad93ec 859 ctl_work->adsp = dsp;
6ab2b7b4
DP		 860 ctl_work->ctl = ctl;
861 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
862 schedule_work(&ctl_work->work);
863
9dbce044 864found:
6ab2b7b4
DP		 865 kfree(name);
866
867 return 0;
868
869err_ctl_cache:
870 kfree(ctl->cache);
871err_ctl_name:
872 kfree(ctl->name);
873err_ctl:
874 kfree(ctl);
875err_name:
876 kfree(name);
877 return ret;
878}
879
880static int wm_adsp_setup_algs(struct wm_adsp *dsp, struct snd_soc_codec *codec)
db40517c
MB		 881{
882 struct regmap *regmap = dsp->regmap;
883 struct wmfw_adsp1_id_hdr adsp1_id;
884 struct wmfw_adsp2_id_hdr adsp2_id;
885 struct wmfw_adsp1_alg_hdr *adsp1_alg;
886 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 887 void *alg, *buf;
471f4885 888 struct wm_adsp_alg_region *region;
db40517c
MB		 889 const struct wm_adsp_region *mem;
890 unsigned int pos, term;
d62f4bc6 891 size_t algs, buf_size;
db40517c
MB		 892 __be32 val;
893 int i, ret;
894
895 switch (dsp->type) {
896 case WMFW_ADSP1:
897 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
898 break;
899 case WMFW_ADSP2:
900 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
901 break;
902 default:
903 mem = NULL;
904 break;
905 }
906
907 if (mem == NULL) {
908 BUG_ON(mem != NULL);
909 return -EINVAL;
910 }
911
912 switch (dsp->type) {
913 case WMFW_ADSP1:
914 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
915 sizeof(adsp1_id));
916 if (ret != 0) {
917 adsp_err(dsp, "Failed to read algorithm info: %d\n",
918 ret);
919 return ret;
920 }
921
d62f4bc6
MB		 922 buf = &adsp1_id;
923 buf_size = sizeof(adsp1_id);
924
db40517c 925 algs = be32_to_cpu(adsp1_id.algs);
f395a218 926 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
db40517c 927 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
f395a218 928 dsp->fw_id,
db40517c
MB		 929 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
930 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
931 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
932 algs);
933
ac50009f
MB		 934 region = kzalloc(sizeof(*region), GFP_KERNEL);
935 if (!region)
936 return -ENOMEM;
937 region->type = WMFW_ADSP1_ZM;
938 region->alg = be32_to_cpu(adsp1_id.fw.id);
939 region->base = be32_to_cpu(adsp1_id.zm);
940 list_add_tail(&region->list, &dsp->alg_regions);
941
942 region = kzalloc(sizeof(*region), GFP_KERNEL);
943 if (!region)
944 return -ENOMEM;
945 region->type = WMFW_ADSP1_DM;
946 region->alg = be32_to_cpu(adsp1_id.fw.id);
947 region->base = be32_to_cpu(adsp1_id.dm);
948 list_add_tail(&region->list, &dsp->alg_regions);
949
db40517c
MB		 950 pos = sizeof(adsp1_id) / 2;
951 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
952 break;
953
954 case WMFW_ADSP2:
955 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
956 sizeof(adsp2_id));
957 if (ret != 0) {
958 adsp_err(dsp, "Failed to read algorithm info: %d\n",
959 ret);
960 return ret;
961 }
962
d62f4bc6
MB		 963 buf = &adsp2_id;
964 buf_size = sizeof(adsp2_id);
965
db40517c 966 algs = be32_to_cpu(adsp2_id.algs);
f395a218 967 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
db40517c 968 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
f395a218 969 dsp->fw_id,
db40517c
MB		 970 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
971 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
972 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
973 algs);
974
ac50009f
MB		 975 region = kzalloc(sizeof(*region), GFP_KERNEL);
976 if (!region)
977 return -ENOMEM;
978 region->type = WMFW_ADSP2_XM;
979 region->alg = be32_to_cpu(adsp2_id.fw.id);
980 region->base = be32_to_cpu(adsp2_id.xm);
981 list_add_tail(&region->list, &dsp->alg_regions);
982
983 region = kzalloc(sizeof(*region), GFP_KERNEL);
984 if (!region)
985 return -ENOMEM;
986 region->type = WMFW_ADSP2_YM;
987 region->alg = be32_to_cpu(adsp2_id.fw.id);
988 region->base = be32_to_cpu(adsp2_id.ym);
989 list_add_tail(&region->list, &dsp->alg_regions);
990
991 region = kzalloc(sizeof(*region), GFP_KERNEL);
992 if (!region)
993 return -ENOMEM;
994 region->type = WMFW_ADSP2_ZM;
995 region->alg = be32_to_cpu(adsp2_id.fw.id);
996 region->base = be32_to_cpu(adsp2_id.zm);
997 list_add_tail(&region->list, &dsp->alg_regions);
998
db40517c
MB		 999 pos = sizeof(adsp2_id) / 2;
1000 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
1001 break;
1002
1003 default:
1004 BUG_ON(NULL == "Unknown DSP type");
1005 return -EINVAL;
1006 }
1007
1008 if (algs == 0) {
1009 adsp_err(dsp, "No algorithms\n");
1010 return -EINVAL;
1011 }
1012
d62f4bc6
MB		 1013 if (algs > 1024) {
1014 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
1015 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
1016 buf, buf_size);
1017 return -EINVAL;
1018 }
1019
db40517c
MB		 1020 /* Read the terminator first to validate the length */
1021 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
1022 if (ret != 0) {
1023 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1024 ret);
1025 return ret;
1026 }
1027
1028 if (be32_to_cpu(val) != 0xbedead)
1029 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1030 term, be32_to_cpu(val));
1031
f2a93e2a 1032 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
db40517c
MB		 1033 if (!alg)
1034 return -ENOMEM;
1035
1036 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
1037 if (ret != 0) {
1038 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1039 ret);
1040 goto out;
1041 }
1042
1043 adsp1_alg = alg;
1044 adsp2_alg = alg;
1045
1046 for (i = 0; i < algs; i++) {
1047 switch (dsp->type) {
1048 case WMFW_ADSP1:
471f4885 1049 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
db40517c
MB		 1050 i, be32_to_cpu(adsp1_alg[i].alg.id),
1051 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1052 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 1053 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1054 be32_to_cpu(adsp1_alg[i].dm),
1055 be32_to_cpu(adsp1_alg[i].zm));
1056
7480800e
MB		 1057 region = kzalloc(sizeof(*region), GFP_KERNEL);
1058 if (!region)
1059 return -ENOMEM;
1060 region->type = WMFW_ADSP1_DM;
1061 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1062 region->base = be32_to_cpu(adsp1_alg[i].dm);
6ab2b7b4 1063 region->len = 0;
7480800e 1064 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1065 if (i + 1 < algs) {
1066 region->len = be32_to_cpu(adsp1_alg[i + 1].dm);
1067 region->len -= be32_to_cpu(adsp1_alg[i].dm);
1068 wm_adsp_create_control(codec, region);
1069 } else {
1070 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1071 be32_to_cpu(adsp1_alg[i].alg.id));
1072 }
471f4885 1073
7480800e
MB		 1074 region = kzalloc(sizeof(*region), GFP_KERNEL);
1075 if (!region)
1076 return -ENOMEM;
1077 region->type = WMFW_ADSP1_ZM;
1078 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1079 region->base = be32_to_cpu(adsp1_alg[i].zm);
6ab2b7b4 1080 region->len = 0;
7480800e 1081 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1082 if (i + 1 < algs) {
1083 region->len = be32_to_cpu(adsp1_alg[i + 1].zm);
1084 region->len -= be32_to_cpu(adsp1_alg[i].zm);
1085 wm_adsp_create_control(codec, region);
1086 } else {
1087 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1088 be32_to_cpu(adsp1_alg[i].alg.id));
1089 }
db40517c
MB		 1090 break;
1091
1092 case WMFW_ADSP2:
471f4885
MB		 1093 adsp_info(dsp,
1094 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
db40517c
MB		 1095 i, be32_to_cpu(adsp2_alg[i].alg.id),
1096 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1097 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 1098 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1099 be32_to_cpu(adsp2_alg[i].xm),
1100 be32_to_cpu(adsp2_alg[i].ym),
1101 be32_to_cpu(adsp2_alg[i].zm));
1102
7480800e
MB		 1103 region = kzalloc(sizeof(*region), GFP_KERNEL);
1104 if (!region)
1105 return -ENOMEM;
1106 region->type = WMFW_ADSP2_XM;
1107 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1108 region->base = be32_to_cpu(adsp2_alg[i].xm);
6ab2b7b4 1109 region->len = 0;
7480800e 1110 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1111 if (i + 1 < algs) {
1112 region->len = be32_to_cpu(adsp2_alg[i + 1].xm);
1113 region->len -= be32_to_cpu(adsp2_alg[i].xm);
1114 wm_adsp_create_control(codec, region);
1115 } else {
1116 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1117 be32_to_cpu(adsp2_alg[i].alg.id));
1118 }
471f4885 1119
7480800e
MB		 1120 region = kzalloc(sizeof(*region), GFP_KERNEL);
1121 if (!region)
1122 return -ENOMEM;
1123 region->type = WMFW_ADSP2_YM;
1124 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1125 region->base = be32_to_cpu(adsp2_alg[i].ym);
6ab2b7b4 1126 region->len = 0;
7480800e 1127 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1128 if (i + 1 < algs) {
1129 region->len = be32_to_cpu(adsp2_alg[i + 1].ym);
1130 region->len -= be32_to_cpu(adsp2_alg[i].ym);
1131 wm_adsp_create_control(codec, region);
1132 } else {
1133 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1134 be32_to_cpu(adsp2_alg[i].alg.id));
1135 }
471f4885 1136
7480800e
MB		 1137 region = kzalloc(sizeof(*region), GFP_KERNEL);
1138 if (!region)
1139 return -ENOMEM;
1140 region->type = WMFW_ADSP2_ZM;
1141 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1142 region->base = be32_to_cpu(adsp2_alg[i].zm);
6ab2b7b4 1143 region->len = 0;
7480800e 1144 list_add_tail(&region->list, &dsp->alg_regions);
6ab2b7b4
DP		 1145 if (i + 1 < algs) {
1146 region->len = be32_to_cpu(adsp2_alg[i + 1].zm);
1147 region->len -= be32_to_cpu(adsp2_alg[i].zm);
1148 wm_adsp_create_control(codec, region);
1149 } else {
1150 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1151 be32_to_cpu(adsp2_alg[i].alg.id));
1152 }
db40517c
MB		 1153 break;
1154 }
1155 }
1156
1157out:
1158 kfree(alg);
1159 return ret;
1160}
1161
2159ad93
MB		 1162static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1163{
cf17c83c 1164 LIST_HEAD(buf_list);
2159ad93
MB		 1165 struct regmap *regmap = dsp->regmap;
1166 struct wmfw_coeff_hdr *hdr;
1167 struct wmfw_coeff_item *blk;
1168 const struct firmware *firmware;
471f4885
MB		 1169 const struct wm_adsp_region *mem;
1170 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1171 const char *region_name;
1172 int ret, pos, blocks, type, offset, reg;
1173 char *file;
cf17c83c 1174 struct wm_adsp_buf *buf;
bdaacea3 1175 int tmp;
2159ad93
MB		 1176
1177 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1178 if (file == NULL)
1179 return -ENOMEM;
1180
1023dbd9
MB		 1181 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1182 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1183 file[PAGE_SIZE - 1] = '\0';
1184
1185 ret = request_firmware(&firmware, file, dsp->dev);
1186 if (ret != 0) {
1187 adsp_warn(dsp, "Failed to request '%s'\n", file);
1188 ret = 0;
1189 goto out;
1190 }
1191 ret = -EINVAL;
1192
1193 if (sizeof(*hdr) >= firmware->size) {
1194 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1195 file, firmware->size);
1196 goto out_fw;
1197 }
1198
1199 hdr = (void*)&firmware->data[0];
1200 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1201 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1202 goto out_fw;
2159ad93
MB		 1203 }
1204
c712326d
MB		 1205 switch (be32_to_cpu(hdr->rev) & 0xff) {
1206 case 1:
1207 break;
1208 default:
1209 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1210 file, be32_to_cpu(hdr->rev) & 0xff);
1211 ret = -EINVAL;
1212 goto out_fw;
1213 }
1214
2159ad93
MB		 1215 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1216 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1217 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1218 le32_to_cpu(hdr->ver) & 0xff);
1219
1220 pos = le32_to_cpu(hdr->len);
1221
1222 blocks = 0;
1223 while (pos < firmware->size &&
1224 pos - firmware->size > sizeof(*blk)) {
1225 blk = (void*)(&firmware->data[pos]);
1226
c712326d
MB		 1227 type = le16_to_cpu(blk->type);
1228 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1229
1230 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1231 file, blocks, le32_to_cpu(blk->id),
1232 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1233 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1234 le32_to_cpu(blk->ver) & 0xff);
1235 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1236 file, blocks, le32_to_cpu(blk->len), offset, type);
1237
1238 reg = 0;
1239 region_name = "Unknown";
1240 switch (type) {
c712326d
MB		 1241 case (WMFW_NAME_TEXT << 8):
1242 case (WMFW_INFO_TEXT << 8):
2159ad93 1243 break;
c712326d 1244 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1245 /*
1246 * Old files may use this for global
1247 * coefficients.
1248 */
1249 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1250 offset == 0) {
1251 region_name = "global coefficients";
1252 mem = wm_adsp_find_region(dsp, type);
1253 if (!mem) {
1254 adsp_err(dsp, "No ZM\n");
1255 break;
1256 }
1257 reg = wm_adsp_region_to_reg(mem, 0);
1258
1259 } else {
1260 region_name = "register";
1261 reg = offset;
1262 }
2159ad93 1263 break;
471f4885
MB		 1264
1265 case WMFW_ADSP1_DM:
1266 case WMFW_ADSP1_ZM:
1267 case WMFW_ADSP2_XM:
1268 case WMFW_ADSP2_YM:
1269 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1270 file, blocks, le32_to_cpu(blk->len),
1271 type, le32_to_cpu(blk->id));
1272
1273 mem = wm_adsp_find_region(dsp, type);
1274 if (!mem) {
1275 adsp_err(dsp, "No base for region %x\n", type);
1276 break;
1277 }
1278
1279 reg = 0;
1280 list_for_each_entry(alg_region,
1281 &dsp->alg_regions, list) {
1282 if (le32_to_cpu(blk->id) == alg_region->alg &&
1283 type == alg_region->type) {
338c5188 1284 reg = alg_region->base;
471f4885
MB		 1285 reg = wm_adsp_region_to_reg(mem,
1286 reg);
338c5188 1287 reg += offset;
471f4885
MB		 1288 }
1289 }
1290
1291 if (reg == 0)
1292 adsp_err(dsp, "No %x for algorithm %x\n",
1293 type, le32_to_cpu(blk->id));
1294 break;
1295
2159ad93 1296 default:
25c62f7e
MB		 1297 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1298 file, blocks, type, pos);
2159ad93
MB		 1299 break;
1300 }
1301
1302 if (reg) {
cf17c83c
MB		 1303 buf = wm_adsp_buf_alloc(blk->data,
1304 le32_to_cpu(blk->len),
1305 &buf_list);
a76fefab
MB		 1306 if (!buf) {
1307 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1308 ret = -ENOMEM;
1309 goto out_fw;
a76fefab
MB		 1310 }
1311
20da6d5a
MB		 1312 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1313 file, blocks, le32_to_cpu(blk->len),
1314 reg);
cf17c83c
MB		 1315 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1316 le32_to_cpu(blk->len));
2159ad93
MB		 1317 if (ret != 0) {
1318 adsp_err(dsp,
1319 "%s.%d: Failed to write to %x in %s\n",
1320 file, blocks, reg, region_name);
1321 }
1322 }
1323
bdaacea3
CR		 1324 tmp = le32_to_cpu(blk->len) % 4;
1325 if (tmp)
1326 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
1327 else
1328 pos += le32_to_cpu(blk->len) + sizeof(*blk);
1329
2159ad93
MB		 1330 blocks++;
1331 }
1332
cf17c83c
MB		 1333 ret = regmap_async_complete(regmap);
1334 if (ret != 0)
1335 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1336
2159ad93
MB		 1337 if (pos > firmware->size)
1338 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1339 file, blocks, pos - firmware->size);
1340
1341out_fw:
1342 release_firmware(firmware);
cf17c83c 1343 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1344out:
1345 kfree(file);
f4b82812 1346 return ret;
2159ad93
MB		 1347}
1348
5e7a7a22
MB		 1349int wm_adsp1_init(struct wm_adsp *adsp)
1350{
1351 INIT_LIST_HEAD(&adsp->alg_regions);
1352
1353 return 0;
1354}
1355EXPORT_SYMBOL_GPL(wm_adsp1_init);
1356
2159ad93
MB		 1357int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1358 struct snd_kcontrol *kcontrol,
1359 int event)
1360{
1361 struct snd_soc_codec *codec = w->codec;
1362 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1363 struct wm_adsp *dsp = &dsps[w->shift];
6ab2b7b4 1364 struct wm_coeff_ctl *ctl;
2159ad93 1365 int ret;
94e205bf 1366 int val;
2159ad93
MB		 1367
1368 switch (event) {
1369 case SND_SOC_DAPM_POST_PMU:
1370 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1371 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1372
94e205bf
CR		 1373 /*
1374 * For simplicity set the DSP clock rate to be the
1375 * SYSCLK rate rather than making it configurable.
1376 */
1377 if(dsp->sysclk_reg) {
1378 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1379 if (ret != 0) {
1380 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1381 ret);
1382 return ret;
1383 }
1384
1385 val = (val & dsp->sysclk_mask)
1386 >> dsp->sysclk_shift;
1387
1388 ret = regmap_update_bits(dsp->regmap,
1389 dsp->base + ADSP1_CONTROL_31,
1390 ADSP1_CLK_SEL_MASK, val);
1391 if (ret != 0) {
1392 adsp_err(dsp, "Failed to set clock rate: %d\n",
1393 ret);
1394 return ret;
1395 }
1396 }
1397
2159ad93
MB		 1398 ret = wm_adsp_load(dsp);
1399 if (ret != 0)
1400 goto err;
1401
6ab2b7b4 1402 ret = wm_adsp_setup_algs(dsp, codec);
db40517c
MB		 1403 if (ret != 0)
1404 goto err;
1405
2159ad93
MB		 1406 ret = wm_adsp_load_coeff(dsp);
1407 if (ret != 0)
1408 goto err;
1409
0c2e3f34 1410 /* Initialize caches for enabled and unset controls */
81ad93ec 1411 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4
DP		 1412 if (ret != 0)
1413 goto err;
1414
0c2e3f34 1415 /* Sync set controls */
81ad93ec 1416 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4
DP		 1417 if (ret != 0)
1418 goto err;
1419
2159ad93
MB		 1420 /* Start the core running */
1421 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1422 ADSP1_CORE_ENA | ADSP1_START,
1423 ADSP1_CORE_ENA | ADSP1_START);
1424 break;
1425
1426 case SND_SOC_DAPM_PRE_PMD:
1427 /* Halt the core */
1428 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1429 ADSP1_CORE_ENA | ADSP1_START, 0);
1430
1431 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1432 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1433
1434 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1435 ADSP1_SYS_ENA, 0);
6ab2b7b4 1436
81ad93ec 1437 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 1438 ctl->enabled = 0;
2159ad93
MB		 1439 break;
1440
1441 default:
1442 break;
1443 }
1444
1445 return 0;
1446
1447err:
1448 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1449 ADSP1_SYS_ENA, 0);
1450 return ret;
1451}
1452EXPORT_SYMBOL_GPL(wm_adsp1_event);
1453
1454static int wm_adsp2_ena(struct wm_adsp *dsp)
1455{
1456 unsigned int val;
1457 int ret, count;
1458
1459 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1460 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1461 if (ret != 0)
1462 return ret;
1463
1464 /* Wait for the RAM to start, should be near instantaneous */
1465 count = 0;
1466 do {
1467 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1468 &val);
1469 if (ret != 0)
1470 return ret;
1471 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
1472
1473 if (!(val & ADSP2_RAM_RDY)) {
1474 adsp_err(dsp, "Failed to start DSP RAM\n");
1475 return -EBUSY;
1476 }
1477
1478 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1479 adsp_info(dsp, "RAM ready after %d polls\n", count);
1480
1481 return 0;
1482}
1483
1484int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1485 struct snd_kcontrol *kcontrol, int event)
1486{
1487 struct snd_soc_codec *codec = w->codec;
1488 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1489 struct wm_adsp *dsp = &dsps[w->shift];
471f4885 1490 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 1491 struct wm_coeff_ctl *ctl;
973838a0 1492 unsigned int val;
2159ad93
MB		 1493 int ret;
1494
1495 switch (event) {
1496 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 1497 /*
1498 * For simplicity set the DSP clock rate to be the
1499 * SYSCLK rate rather than making it configurable.
1500 */
1501 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1502 if (ret != 0) {
1503 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1504 ret);
1505 return ret;
1506 }
1507 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1508 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1509
1510 ret = regmap_update_bits(dsp->regmap,
1511 dsp->base + ADSP2_CLOCKING,
1512 ADSP2_CLK_SEL_MASK, val);
1513 if (ret != 0) {
1514 adsp_err(dsp, "Failed to set clock rate: %d\n",
1515 ret);
1516 return ret;
1517 }
1518
973838a0
MB		 1519 if (dsp->dvfs) {
1520 ret = regmap_read(dsp->regmap,
1521 dsp->base + ADSP2_CLOCKING, &val);
1522 if (ret != 0) {
1523 dev_err(dsp->dev,
1524 "Failed to read clocking: %d\n", ret);
1525 return ret;
1526 }
1527
25c6fdb0 1528 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 1529 ret = regulator_enable(dsp->dvfs);
1530 if (ret != 0) {
1531 dev_err(dsp->dev,
1532 "Failed to enable supply: %d\n",
1533 ret);
1534 return ret;
1535 }
1536
1537 ret = regulator_set_voltage(dsp->dvfs,
1538 1800000,
1539 1800000);
1540 if (ret != 0) {
1541 dev_err(dsp->dev,
1542 "Failed to raise supply: %d\n",
1543 ret);
1544 return ret;
1545 }
1546 }
1547 }
1548
2159ad93
MB		 1549 ret = wm_adsp2_ena(dsp);
1550 if (ret != 0)
1551 return ret;
1552
1553 ret = wm_adsp_load(dsp);
1554 if (ret != 0)
1555 goto err;
1556
6ab2b7b4 1557 ret = wm_adsp_setup_algs(dsp, codec);
db40517c
MB		 1558 if (ret != 0)
1559 goto err;
1560
2159ad93
MB		 1561 ret = wm_adsp_load_coeff(dsp);
1562 if (ret != 0)
1563 goto err;
1564
0c2e3f34 1565 /* Initialize caches for enabled and unset controls */
81ad93ec 1566 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4
DP		 1567 if (ret != 0)
1568 goto err;
1569
0c2e3f34 1570 /* Sync set controls */
81ad93ec 1571 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4
DP		 1572 if (ret != 0)
1573 goto err;
1574
2159ad93
MB		 1575 ret = regmap_update_bits(dsp->regmap,
1576 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1577 ADSP2_CORE_ENA | ADSP2_START,
1578 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 1579 if (ret != 0)
1580 goto err;
1023dbd9
MB		 1581
1582 dsp->running = true;
2159ad93
MB		 1583 break;
1584
1585 case SND_SOC_DAPM_PRE_PMD:
1023dbd9
MB		 1586 dsp->running = false;
1587
2159ad93 1588 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1589 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1590 ADSP2_START, 0);
973838a0 1591
2d30b575
MB		 1592 /* Make sure DMAs are quiesced */
1593 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1594 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1595 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1596
973838a0
MB		 1597 if (dsp->dvfs) {
1598 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1599 1800000);
1600 if (ret != 0)
1601 dev_warn(dsp->dev,
1602 "Failed to lower supply: %d\n",
1603 ret);
1604
1605 ret = regulator_disable(dsp->dvfs);
1606 if (ret != 0)
1607 dev_err(dsp->dev,
1608 "Failed to enable supply: %d\n",
1609 ret);
1610 }
471f4885 1611
81ad93ec 1612 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 1613 ctl->enabled = 0;
6ab2b7b4 1614
471f4885
MB		 1615 while (!list_empty(&dsp->alg_regions)) {
1616 alg_region = list_first_entry(&dsp->alg_regions,
1617 struct wm_adsp_alg_region,
1618 list);
1619 list_del(&alg_region->list);
1620 kfree(alg_region);
1621 }
2159ad93
MB		 1622 break;
1623
1624 default:
1625 break;
1626 }
1627
1628 return 0;
1629err:
1630 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 1631 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 1632 return ret;
1633}
1634EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 1635
1636int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1637{
1638 int ret;
1639
10a2b662
MB		 1640 /*
1641 * Disable the DSP memory by default when in reset for a small
1642 * power saving.
1643 */
1644 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1645 ADSP2_MEM_ENA, 0);
1646 if (ret != 0) {
1647 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1648 return ret;
1649 }
1650
471f4885 1651 INIT_LIST_HEAD(&adsp->alg_regions);
81ad93ec 1652 INIT_LIST_HEAD(&adsp->ctl_list);
6ab2b7b4 1653
973838a0
MB		 1654 if (dvfs) {
1655 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1656 if (IS_ERR(adsp->dvfs)) {
1657 ret = PTR_ERR(adsp->dvfs);
1658 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
81ad93ec 1659 return ret;
973838a0
MB		 1660 }
1661
1662 ret = regulator_enable(adsp->dvfs);
1663 if (ret != 0) {
1664 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1665 ret);
81ad93ec 1666 return ret;
973838a0
MB		 1667 }
1668
1669 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1670 if (ret != 0) {
1671 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1672 ret);
81ad93ec 1673 return ret;
973838a0
MB		 1674 }
1675
1676 ret = regulator_disable(adsp->dvfs);
1677 if (ret != 0) {
1678 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1679 ret);
81ad93ec 1680 return ret;
973838a0
MB		 1681 }
1682 }
1683
1684 return 0;
1685}
1686EXPORT_SYMBOL_GPL(wm_adsp2_init);
Empty description
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