[linux.git] / kernel / irq / msi.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2014 Intel Corp.
 * Author: Jiang Liu <[email protected]>
 *
 * This file is licensed under GPLv2.
 *
 * This file contains common code to support Message Signalled Interrupt for
 * PCI compatible and non PCI compatible devices.
 */
#include <linux/types.h>
#include <linux/device.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/msi.h>
#include <linux/slab.h>

#include "internals.h"

/**
 * alloc_msi_entry - Allocate an initialize msi_entry
 * @dev:	Pointer to the device for which this is allocated
 * @nvec:	The number of vectors used in this entry
 * @affinity:	Optional pointer to an affinity mask array size of @nvec
 *
 * If @affinity is not NULL then an affinity array[@nvec] is allocated
 * and the affinity masks and flags from @affinity are copied.
 */
struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
				 const struct irq_affinity_desc *affinity)
{
	struct msi_desc *desc;

	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
	if (!desc)
		return NULL;

	INIT_LIST_HEAD(&desc->list);
	desc->dev = dev;
	desc->nvec_used = nvec;
	if (affinity) {
		desc->affinity = kmemdup(affinity,
			nvec * sizeof(*desc->affinity), GFP_KERNEL);
		if (!desc->affinity) {
			kfree(desc);
			return NULL;
		}
	}

	return desc;
}

void free_msi_entry(struct msi_desc *entry)
{
	kfree(entry->affinity);
	kfree(entry);
}

void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
{
	*msg = entry->msg;
}

void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
{
	struct msi_desc *entry = irq_get_msi_desc(irq);

	__get_cached_msi_msg(entry, msg);
}
EXPORT_SYMBOL_GPL(get_cached_msi_msg);

#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
static inline void irq_chip_write_msi_msg(struct irq_data *data,
					  struct msi_msg *msg)
{
	data->chip->irq_write_msi_msg(data, msg);
}

static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
{
	struct msi_domain_info *info = domain->host_data;

	/*
	 * If the MSI provider has messed with the second message and
	 * not advertized that it is level-capable, signal the breakage.
	 */
	WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
		  (info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
		(msg[1].address_lo || msg[1].address_hi || msg[1].data));
}

/**
 * msi_domain_set_affinity - Generic affinity setter function for MSI domains
 * @irq_data:	The irq data associated to the interrupt
 * @mask:	The affinity mask to set
 * @force:	Flag to enforce setting (disable online checks)
 *
 * Intended to be used by MSI interrupt controllers which are
 * implemented with hierarchical domains.
 */
int msi_domain_set_affinity(struct irq_data *irq_data,
			    const struct cpumask *mask, bool force)
{
	struct irq_data *parent = irq_data->parent_data;
	struct msi_msg msg[2] = { [1] = { }, };
	int ret;

	ret = parent->chip->irq_set_affinity(parent, mask, force);
	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
		BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
		msi_check_level(irq_data->domain, msg);
		irq_chip_write_msi_msg(irq_data, msg);
	}

	return ret;
}

static int msi_domain_activate(struct irq_domain *domain,
			       struct irq_data *irq_data, bool early)
{
	struct msi_msg msg[2] = { [1] = { }, };

	BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
	msi_check_level(irq_data->domain, msg);
	irq_chip_write_msi_msg(irq_data, msg);
	return 0;
}

static void msi_domain_deactivate(struct irq_domain *domain,
				  struct irq_data *irq_data)
{
	struct msi_msg msg[2];

	memset(msg, 0, sizeof(msg));
	irq_chip_write_msi_msg(irq_data, msg);
}

static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
			    unsigned int nr_irqs, void *arg)
{
	struct msi_domain_info *info = domain->host_data;
	struct msi_domain_ops *ops = info->ops;
	irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
	int i, ret;

	if (irq_find_mapping(domain, hwirq) > 0)
		return -EEXIST;

	if (domain->parent) {
		ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
		if (ret < 0)
			return ret;
	}

	for (i = 0; i < nr_irqs; i++) {
		ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
		if (ret < 0) {
			if (ops->msi_free) {
				for (i--; i > 0; i--)
					ops->msi_free(domain, info, virq + i);
			}
			irq_domain_free_irqs_top(domain, virq, nr_irqs);
			return ret;
		}
	}

	return 0;
}

static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
			    unsigned int nr_irqs)
{
	struct msi_domain_info *info = domain->host_data;
	int i;

	if (info->ops->msi_free) {
		for (i = 0; i < nr_irqs; i++)
			info->ops->msi_free(domain, info, virq + i);
	}
	irq_domain_free_irqs_top(domain, virq, nr_irqs);
}

static const struct irq_domain_ops msi_domain_ops = {
	.alloc		= msi_domain_alloc,
	.free		= msi_domain_free,
	.activate	= msi_domain_activate,
	.deactivate	= msi_domain_deactivate,
};

#ifdef GENERIC_MSI_DOMAIN_OPS
static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
						msi_alloc_info_t *arg)
{
	return arg->hwirq;
}

static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
				  int nvec, msi_alloc_info_t *arg)
{
	memset(arg, 0, sizeof(*arg));
	return 0;
}

static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
				    struct msi_desc *desc)
{
	arg->desc = desc;
}
#else
#define msi_domain_ops_get_hwirq	NULL
#define msi_domain_ops_prepare		NULL
#define msi_domain_ops_set_desc		NULL
#endif /* !GENERIC_MSI_DOMAIN_OPS */

static int msi_domain_ops_init(struct irq_domain *domain,
			       struct msi_domain_info *info,
			       unsigned int virq, irq_hw_number_t hwirq,
			       msi_alloc_info_t *arg)
{
	irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
				      info->chip_data);
	if (info->handler && info->handler_name) {
		__irq_set_handler(virq, info->handler, 0, info->handler_name);
		if (info->handler_data)
			irq_set_handler_data(virq, info->handler_data);
	}
	return 0;
}

static int msi_domain_ops_check(struct irq_domain *domain,
				struct msi_domain_info *info,
				struct device *dev)
{
	return 0;
}

static struct msi_domain_ops msi_domain_ops_default = {
	.get_hwirq	= msi_domain_ops_get_hwirq,
	.msi_init	= msi_domain_ops_init,
	.msi_check	= msi_domain_ops_check,
	.msi_prepare	= msi_domain_ops_prepare,
	.set_desc	= msi_domain_ops_set_desc,
};

static void msi_domain_update_dom_ops(struct msi_domain_info *info)
{
	struct msi_domain_ops *ops = info->ops;

	if (ops == NULL) {
		info->ops = &msi_domain_ops_default;
		return;
	}

	if (ops->get_hwirq == NULL)
		ops->get_hwirq = msi_domain_ops_default.get_hwirq;
	if (ops->msi_init == NULL)
		ops->msi_init = msi_domain_ops_default.msi_init;
	if (ops->msi_check == NULL)
		ops->msi_check = msi_domain_ops_default.msi_check;
	if (ops->msi_prepare == NULL)
		ops->msi_prepare = msi_domain_ops_default.msi_prepare;
	if (ops->set_desc == NULL)
		ops->set_desc = msi_domain_ops_default.set_desc;
}

static void msi_domain_update_chip_ops(struct msi_domain_info *info)
{
	struct irq_chip *chip = info->chip;

	BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
	if (!chip->irq_set_affinity)
		chip->irq_set_affinity = msi_domain_set_affinity;
}

/**
 * msi_create_irq_domain - Create a MSI interrupt domain
 * @fwnode:	Optional fwnode of the interrupt controller
 * @info:	MSI domain info
 * @parent:	Parent irq domain
 */
struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
					 struct msi_domain_info *info,
					 struct irq_domain *parent)
{
	struct irq_domain *domain;

	if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
		msi_domain_update_dom_ops(info);
	if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
		msi_domain_update_chip_ops(info);

	domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
					     fwnode, &msi_domain_ops, info);

	if (domain && !domain->name && info->chip)
		domain->name = info->chip->name;

	return domain;
}

int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
			    int nvec, msi_alloc_info_t *arg)
{
	struct msi_domain_info *info = domain->host_data;
	struct msi_domain_ops *ops = info->ops;
	int ret;

	ret = ops->msi_check(domain, info, dev);
	if (ret == 0)
		ret = ops->msi_prepare(domain, dev, nvec, arg);

	return ret;
}

int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
			     int virq, int nvec, msi_alloc_info_t *arg)
{
	struct msi_domain_info *info = domain->host_data;
	struct msi_domain_ops *ops = info->ops;
	struct msi_desc *desc;
	int ret = 0;

	for_each_msi_entry(desc, dev) {
		/* Don't even try the multi-MSI brain damage. */
		if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
			ret = -EINVAL;
			break;
		}

		if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
			continue;

		ops->set_desc(arg, desc);
		/* Assumes the domain mutex is held! */
		ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
						      arg);
		if (ret)
			break;

		irq_set_msi_desc_off(desc->irq, 0, desc);
	}

	if (ret) {
		/* Mop up the damage */
		for_each_msi_entry(desc, dev) {
			if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
				continue;

			irq_domain_free_irqs_common(domain, desc->irq, 1);
		}
	}

	return ret;
}

/*
 * Carefully check whether the device can use reservation mode. If
 * reservation mode is enabled then the early activation will assign a
 * dummy vector to the device. If the PCI/MSI device does not support
 * masking of the entry then this can result in spurious interrupts when
 * the device driver is not absolutely careful. But even then a malfunction
 * of the hardware could result in a spurious interrupt on the dummy vector
 * and render the device unusable. If the entry can be masked then the core
 * logic will prevent the spurious interrupt and reservation mode can be
 * used. For now reservation mode is restricted to PCI/MSI.
 */
static bool msi_check_reservation_mode(struct irq_domain *domain,
				       struct msi_domain_info *info,
				       struct device *dev)
{
	struct msi_desc *desc;

	if (domain->bus_token != DOMAIN_BUS_PCI_MSI)
		return false;

	if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
		return false;

	if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
		return false;

	/*
	 * Checking the first MSI descriptor is sufficient. MSIX supports
	 * masking and MSI does so when the maskbit is set.
	 */
	desc = first_msi_entry(dev);
	return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit;
}

/**
 * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
 * @domain:	The domain to allocate from
 * @dev:	Pointer to device struct of the device for which the interrupts
 *		are allocated
 * @nvec:	The number of interrupts to allocate
 *
 * Returns 0 on success or an error code.
 */
int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
			  int nvec)
{
	struct msi_domain_info *info = domain->host_data;
	struct msi_domain_ops *ops = info->ops;
	struct irq_data *irq_data;
	struct msi_desc *desc;
	msi_alloc_info_t arg;
	int i, ret, virq;
	bool can_reserve;

	ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
	if (ret)
		return ret;

	for_each_msi_entry(desc, dev) {
		ops->set_desc(&arg, desc);

		virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
					       dev_to_node(dev), &arg, false,
					       desc->affinity);
		if (virq < 0) {
			ret = -ENOSPC;
			if (ops->handle_error)
				ret = ops->handle_error(domain, desc, ret);
			if (ops->msi_finish)
				ops->msi_finish(&arg, ret);
			return ret;
		}

		for (i = 0; i < desc->nvec_used; i++) {
			irq_set_msi_desc_off(virq, i, desc);
			irq_debugfs_copy_devname(virq + i, dev);
		}
	}

	if (ops->msi_finish)
		ops->msi_finish(&arg, 0);

	can_reserve = msi_check_reservation_mode(domain, info, dev);

	for_each_msi_entry(desc, dev) {
		virq = desc->irq;
		if (desc->nvec_used == 1)
			dev_dbg(dev, "irq %d for MSI\n", virq);
		else
			dev_dbg(dev, "irq [%d-%d] for MSI\n",
				virq, virq + desc->nvec_used - 1);
		/*
		 * This flag is set by the PCI layer as we need to activate
		 * the MSI entries before the PCI layer enables MSI in the
		 * card. Otherwise the card latches a random msi message.
		 */
		if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
			continue;

		irq_data = irq_domain_get_irq_data(domain, desc->irq);
		if (!can_reserve)
			irqd_clr_can_reserve(irq_data);
		ret = irq_domain_activate_irq(irq_data, can_reserve);
		if (ret)
			goto cleanup;
	}

	/*
	 * If these interrupts use reservation mode, clear the activated bit
	 * so request_irq() will assign the final vector.
	 */
	if (can_reserve) {
		for_each_msi_entry(desc, dev) {
			irq_data = irq_domain_get_irq_data(domain, desc->irq);
			irqd_clr_activated(irq_data);
		}
	}
	return 0;

cleanup:
	for_each_msi_entry(desc, dev) {
		struct irq_data *irqd;

		if (desc->irq == virq)
			break;

		irqd = irq_domain_get_irq_data(domain, desc->irq);
		if (irqd_is_activated(irqd))
			irq_domain_deactivate_irq(irqd);
	}
	msi_domain_free_irqs(domain, dev);
	return ret;
}

/**
 * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
 * @domain:	The domain to managing the interrupts
 * @dev:	Pointer to device struct of the device for which the interrupts
 *		are free
 */
void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
{
	struct msi_desc *desc;

	for_each_msi_entry(desc, dev) {
		/*
		 * We might have failed to allocate an MSI early
		 * enough that there is no IRQ associated to this
		 * entry. If that's the case, don't do anything.
		 */
		if (desc->irq) {
			irq_domain_free_irqs(desc->irq, desc->nvec_used);
			desc->irq = 0;
		}
	}
}

/**
 * msi_get_domain_info - Get the MSI interrupt domain info for @domain
 * @domain:	The interrupt domain to retrieve data from
 *
 * Returns the pointer to the msi_domain_info stored in
 * @domain->host_data.
 */
struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
{
	return (struct msi_domain_info *)domain->host_data;
}

#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
Commit	Line	Data
52a65ff5	1	// SPDX-License-Identifier: GPL-2.0
f3cf8bb0	2	/*
f3cf8bb0 JL	3	* Copyright (C) 2014 Intel Corp.
	4	* Author: Jiang Liu <[email protected]>
	5	*
	6	* This file is licensed under GPLv2.
	7	*
	8	* This file contains common code to support Message Signalled Interrupt for
	9	* PCI compatible and non PCI compatible devices.
	10	*/
aeeb5965 JL	11	#include <linux/types.h>
aeeb5965 JL	12	#include <linux/device.h>
f3cf8bb0 JL	13	#include <linux/irq.h>
	14	#include <linux/irqdomain.h>
	15	#include <linux/msi.h>
4e201566	16	#include <linux/slab.h>
d9109698	17
07557ccb TG	18	#include "internals.h"
07557ccb TG	19
28f4b041 TG	20	/**
	21	* alloc_msi_entry - Allocate an initialize msi_entry
	22	* @dev: Pointer to the device for which this is allocated
	23	* @nvec: The number of vectors used in this entry
	24	* @affinity: Optional pointer to an affinity mask array size of @nvec
	25	*
bec04037 DL	26	* If @affinity is not NULL then an affinity array[@nvec] is allocated
bec04037 DL	27	* and the affinity masks and flags from @affinity are copied.
28f4b041	28	*/
bec04037 DL	29	struct msi_desc alloc_msi_entry(struct device dev, int nvec,
bec04037 DL	30	const struct irq_affinity_desc *affinity)
aa48b6f7	31	{
28f4b041 TG	32	struct msi_desc *desc;
	33
	34	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
aa48b6f7 JL	35	if (!desc)
	36	return NULL;
	37
	38	INIT_LIST_HEAD(&desc->list);
	39	desc->dev = dev;
28f4b041 TG	40	desc->nvec_used = nvec;
	41	if (affinity) {
	42	desc->affinity = kmemdup(affinity,
	43	nvec * sizeof(*desc->affinity), GFP_KERNEL);
	44	if (!desc->affinity) {
	45	kfree(desc);
	46	return NULL;
	47	}
	48	}
aa48b6f7 JL	49
	50	return desc;
	51	}
	52
	53	void free_msi_entry(struct msi_desc *entry)
	54	{
28f4b041	55	kfree(entry->affinity);
aa48b6f7 JL	56	kfree(entry);
	57	}
	58
38b6a1cf JL	59	void __get_cached_msi_msg(struct msi_desc entry, struct msi_msg msg)
	60	{
	61	*msg = entry->msg;
	62	}
	63
	64	void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
	65	{
	66	struct msi_desc *entry = irq_get_msi_desc(irq);
	67
	68	__get_cached_msi_msg(entry, msg);
	69	}
	70	EXPORT_SYMBOL_GPL(get_cached_msi_msg);
	71
f3cf8bb0	72	#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
74faaf7a TG	73	static inline void irq_chip_write_msi_msg(struct irq_data *data,
	74	struct msi_msg *msg)
	75	{
	76	data->chip->irq_write_msi_msg(data, msg);
	77	}
	78
0be8153c MZ	79	static void msi_check_level(struct irq_domain domain, struct msi_msg msg)
	80	{
	81	struct msi_domain_info *info = domain->host_data;
	82
	83	/*
	84	* If the MSI provider has messed with the second message and
	85	* not advertized that it is level-capable, signal the breakage.
	86	*/
	87	WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
	88	(info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
	89	(msg[1].address_lo \|\| msg[1].address_hi \|\| msg[1].data));
	90	}
	91
f3cf8bb0 JL	92	/**
	93	* msi_domain_set_affinity - Generic affinity setter function for MSI domains
	94	* @irq_data: The irq data associated to the interrupt
	95	* @mask: The affinity mask to set
	96	* @force: Flag to enforce setting (disable online checks)
	97	*
	98	* Intended to be used by MSI interrupt controllers which are
	99	* implemented with hierarchical domains.
	100	*/
	101	int msi_domain_set_affinity(struct irq_data *irq_data,
	102	const struct cpumask *mask, bool force)
	103	{
	104	struct irq_data *parent = irq_data->parent_data;
0be8153c	105	struct msi_msg msg[2] = { [1] = { }, };
f3cf8bb0 JL	106	int ret;
	107
	108	ret = parent->chip->irq_set_affinity(parent, mask, force);
	109	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
0be8153c MZ	110	BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
	111	msi_check_level(irq_data->domain, msg);
	112	irq_chip_write_msi_msg(irq_data, msg);
f3cf8bb0 JL	113	}
	114
	115	return ret;
	116	}
	117
72491643 TG	118	static int msi_domain_activate(struct irq_domain *domain,
72491643 TG	119	struct irq_data *irq_data, bool early)
f3cf8bb0	120	{
0be8153c	121	struct msi_msg msg[2] = { [1] = { }, };
f3cf8bb0	122
0be8153c MZ	123	BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
	124	msi_check_level(irq_data->domain, msg);
	125	irq_chip_write_msi_msg(irq_data, msg);
72491643	126	return 0;
f3cf8bb0 JL	127	}
	128
	129	static void msi_domain_deactivate(struct irq_domain *domain,
	130	struct irq_data *irq_data)
	131	{
0be8153c	132	struct msi_msg msg[2];
f3cf8bb0	133
0be8153c MZ	134	memset(msg, 0, sizeof(msg));
0be8153c MZ	135	irq_chip_write_msi_msg(irq_data, msg);
f3cf8bb0 JL	136	}
	137
	138	static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
	139	unsigned int nr_irqs, void *arg)
	140	{
	141	struct msi_domain_info *info = domain->host_data;
	142	struct msi_domain_ops *ops = info->ops;
	143	irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
	144	int i, ret;
	145
	146	if (irq_find_mapping(domain, hwirq) > 0)
	147	return -EEXIST;
	148
bf6f869f LJ	149	if (domain->parent) {
	150	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	151	if (ret < 0)
	152	return ret;
	153	}
f3cf8bb0 JL	154
	155	for (i = 0; i < nr_irqs; i++) {
	156	ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
	157	if (ret < 0) {
	158	if (ops->msi_free) {
	159	for (i--; i > 0; i--)
	160	ops->msi_free(domain, info, virq + i);
	161	}
	162	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	163	return ret;
	164	}
	165	}
	166
	167	return 0;
	168	}
	169
	170	static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
	171	unsigned int nr_irqs)
	172	{
	173	struct msi_domain_info *info = domain->host_data;
	174	int i;
	175
	176	if (info->ops->msi_free) {
	177	for (i = 0; i < nr_irqs; i++)
	178	info->ops->msi_free(domain, info, virq + i);
	179	}
	180	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	181	}
	182
01364028	183	static const struct irq_domain_ops msi_domain_ops = {
f3cf8bb0 JL	184	.alloc = msi_domain_alloc,
	185	.free = msi_domain_free,
	186	.activate = msi_domain_activate,
	187	.deactivate = msi_domain_deactivate,
	188	};
	189
aeeb5965 JL	190	#ifdef GENERIC_MSI_DOMAIN_OPS
	191	static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
	192	msi_alloc_info_t *arg)
	193	{
	194	return arg->hwirq;
	195	}
	196
	197	static int msi_domain_ops_prepare(struct irq_domain domain, struct device dev,
	198	int nvec, msi_alloc_info_t *arg)
	199	{
	200	memset(arg, 0, sizeof(*arg));
	201	return 0;
	202	}
	203
	204	static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
	205	struct msi_desc *desc)
	206	{
	207	arg->desc = desc;
	208	}
	209	#else
	210	#define msi_domain_ops_get_hwirq NULL
	211	#define msi_domain_ops_prepare NULL
	212	#define msi_domain_ops_set_desc NULL
	213	#endif /* !GENERIC_MSI_DOMAIN_OPS */
	214
	215	static int msi_domain_ops_init(struct irq_domain *domain,
	216	struct msi_domain_info *info,
	217	unsigned int virq, irq_hw_number_t hwirq,
	218	msi_alloc_info_t *arg)
	219	{
	220	irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
	221	info->chip_data);
	222	if (info->handler && info->handler_name) {
	223	__irq_set_handler(virq, info->handler, 0, info->handler_name);
	224	if (info->handler_data)
	225	irq_set_handler_data(virq, info->handler_data);
	226	}
	227	return 0;
	228	}
	229
	230	static int msi_domain_ops_check(struct irq_domain *domain,
	231	struct msi_domain_info *info,
	232	struct device *dev)
	233	{
	234	return 0;
	235	}
	236
	237	static struct msi_domain_ops msi_domain_ops_default = {
	238	.get_hwirq = msi_domain_ops_get_hwirq,
	239	.msi_init = msi_domain_ops_init,
	240	.msi_check = msi_domain_ops_check,
	241	.msi_prepare = msi_domain_ops_prepare,
	242	.set_desc = msi_domain_ops_set_desc,
	243	};
	244
	245	static void msi_domain_update_dom_ops(struct msi_domain_info *info)
	246	{
	247	struct msi_domain_ops *ops = info->ops;
	248
	249	if (ops == NULL) {
	250	info->ops = &msi_domain_ops_default;
	251	return;
	252	}
	253
254	if (ops->get_hwirq == NULL)
255	ops->get_hwirq = msi_domain_ops_default.get_hwirq;
256	if (ops->msi_init == NULL)
257	ops->msi_init = msi_domain_ops_default.msi_init;
258	if (ops->msi_check == NULL)
259	ops->msi_check = msi_domain_ops_default.msi_check;
260	if (ops->msi_prepare == NULL)
261	ops->msi_prepare = msi_domain_ops_default.msi_prepare;
262	if (ops->set_desc == NULL)
263	ops->set_desc = msi_domain_ops_default.set_desc;
264	}
265
266	static void msi_domain_update_chip_ops(struct msi_domain_info *info)
267	{
268	struct irq_chip *chip = info->chip;
269
0701c53e	270	BUG_ON(!chip \|\| !chip->irq_mask \|\| !chip->irq_unmask);
aeeb5965 JL	271	if (!chip->irq_set_affinity)
	272	chip->irq_set_affinity = msi_domain_set_affinity;
	273	}
	274
f3cf8bb0 JL	275	/**
f3cf8bb0 JL	276	* msi_create_irq_domain - Create a MSI interrupt domain
be5436c8	277	* @fwnode: Optional fwnode of the interrupt controller
f3cf8bb0 JL	278	* @info: MSI domain info
	279	* @parent: Parent irq domain
	280	*/
be5436c8	281	struct irq_domain msi_create_irq_domain(struct fwnode_handle fwnode,
f3cf8bb0 JL	282	struct msi_domain_info *info,
	283	struct irq_domain *parent)
	284	{
a97b852b MZ	285	struct irq_domain *domain;
a97b852b MZ	286
aeeb5965 JL	287	if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
	288	msi_domain_update_dom_ops(info);
	289	if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
	290	msi_domain_update_chip_ops(info);
f3cf8bb0	291
a97b852b MZ	292	domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
a97b852b MZ	293	fwnode, &msi_domain_ops, info);
0165308a TG	294
0165308a TG	295	if (domain && !domain->name && info->chip)
a97b852b MZ	296	domain->name = info->chip->name;
	297
	298	return domain;
f3cf8bb0 JL	299	}
f3cf8bb0 JL	300
b2eba39b MZ	301	int msi_domain_prepare_irqs(struct irq_domain domain, struct device dev,
	302	int nvec, msi_alloc_info_t *arg)
	303	{
	304	struct msi_domain_info *info = domain->host_data;
	305	struct msi_domain_ops *ops = info->ops;
	306	int ret;
	307
	308	ret = ops->msi_check(domain, info, dev);
	309	if (ret == 0)
	310	ret = ops->msi_prepare(domain, dev, nvec, arg);
	311
	312	return ret;
	313	}
	314
2145ac93 MZ	315	int msi_domain_populate_irqs(struct irq_domain domain, struct device dev,
	316	int virq, int nvec, msi_alloc_info_t *arg)
	317	{
	318	struct msi_domain_info *info = domain->host_data;
	319	struct msi_domain_ops *ops = info->ops;
	320	struct msi_desc *desc;
	321	int ret = 0;
	322
	323	for_each_msi_entry(desc, dev) {
	324	/* Don't even try the multi-MSI brain damage. */
	325	if (WARN_ON(!desc->irq \|\| desc->nvec_used != 1)) {
	326	ret = -EINVAL;
	327	break;
	328	}
	329
	330	if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
	331	continue;
	332
	333	ops->set_desc(arg, desc);
	334	/* Assumes the domain mutex is held! */
596a7a1d JK	335	ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
596a7a1d JK	336	arg);
2145ac93 MZ	337	if (ret)
	338	break;
	339
596a7a1d	340	irq_set_msi_desc_off(desc->irq, 0, desc);
2145ac93 MZ	341	}
	342
	343	if (ret) {
	344	/* Mop up the damage */
	345	for_each_msi_entry(desc, dev) {
	346	if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
	347	continue;
	348
	349	irq_domain_free_irqs_common(domain, desc->irq, 1);
	350	}
	351	}
	352
	353	return ret;
	354	}
	355
bc976233 TG	356	/*
	357	* Carefully check whether the device can use reservation mode. If
	358	* reservation mode is enabled then the early activation will assign a
	359	* dummy vector to the device. If the PCI/MSI device does not support
	360	* masking of the entry then this can result in spurious interrupts when
	361	* the device driver is not absolutely careful. But even then a malfunction
	362	* of the hardware could result in a spurious interrupt on the dummy vector
	363	* and render the device unusable. If the entry can be masked then the core
	364	* logic will prevent the spurious interrupt and reservation mode can be
	365	* used. For now reservation mode is restricted to PCI/MSI.
	366	*/
	367	static bool msi_check_reservation_mode(struct irq_domain *domain,
	368	struct msi_domain_info *info,
	369	struct device *dev)
da5dd9e8	370	{
bc976233 TG	371	struct msi_desc *desc;
	372
	373	if (domain->bus_token != DOMAIN_BUS_PCI_MSI)
	374	return false;
	375
da5dd9e8 TG	376	if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
da5dd9e8 TG	377	return false;
bc976233 TG	378
	379	if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
	380	return false;
	381
	382	/*
	383	* Checking the first MSI descriptor is sufficient. MSIX supports
	384	* masking and MSI does so when the maskbit is set.
	385	*/
	386	desc = first_msi_entry(dev);
	387	return desc->msi_attrib.is_msix \|\| desc->msi_attrib.maskbit;
da5dd9e8 TG	388	}
da5dd9e8 TG	389
d9109698 JL	390	/**
	391	* msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
	392	* @domain: The domain to allocate from
	393	* @dev: Pointer to device struct of the device for which the interrupts
	394	* are allocated
	395	* @nvec: The number of interrupts to allocate
	396	*
	397	* Returns 0 on success or an error code.
	398	*/
	399	int msi_domain_alloc_irqs(struct irq_domain domain, struct device dev,
	400	int nvec)
	401	{
	402	struct msi_domain_info *info = domain->host_data;
	403	struct msi_domain_ops *ops = info->ops;
da5dd9e8	404	struct irq_data *irq_data;
d9109698	405	struct msi_desc *desc;
da5dd9e8	406	msi_alloc_info_t arg;
b6140914	407	int i, ret, virq;
da5dd9e8	408	bool can_reserve;
d9109698	409
b2eba39b	410	ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
d9109698 JL	411	if (ret)
	412	return ret;
	413
	414	for_each_msi_entry(desc, dev) {
	415	ops->set_desc(&arg, desc);
	416
b6140914	417	virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
06ee6d57	418	dev_to_node(dev), &arg, false,
0972fa57	419	desc->affinity);
d9109698 JL	420	if (virq < 0) {
	421	ret = -ENOSPC;
	422	if (ops->handle_error)
	423	ret = ops->handle_error(domain, desc, ret);
	424	if (ops->msi_finish)
	425	ops->msi_finish(&arg, ret);
	426	return ret;
	427	}
	428
07557ccb	429	for (i = 0; i < desc->nvec_used; i++) {
d9109698	430	irq_set_msi_desc_off(virq, i, desc);
07557ccb TG	431	irq_debugfs_copy_devname(virq + i, dev);
07557ccb TG	432	}
d9109698 JL	433	}
	434
	435	if (ops->msi_finish)
	436	ops->msi_finish(&arg, 0);
	437
bc976233	438	can_reserve = msi_check_reservation_mode(domain, info, dev);
da5dd9e8	439
d9109698	440	for_each_msi_entry(desc, dev) {
4364e1a2	441	virq = desc->irq;
d9109698 JL	442	if (desc->nvec_used == 1)
	443	dev_dbg(dev, "irq %d for MSI\n", virq);
	444	else
	445	dev_dbg(dev, "irq [%d-%d] for MSI\n",
	446	virq, virq + desc->nvec_used - 1);
f3b0946d MZ	447	/*
	448	* This flag is set by the PCI layer as we need to activate
	449	* the MSI entries before the PCI layer enables MSI in the
	450	* card. Otherwise the card latches a random msi message.
	451	*/
da5dd9e8 TG	452	if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
da5dd9e8 TG	453	continue;
f3b0946d	454
da5dd9e8	455	irq_data = irq_domain_get_irq_data(domain, desc->irq);
bc976233 TG	456	if (!can_reserve)
	457	irqd_clr_can_reserve(irq_data);
	458	ret = irq_domain_activate_irq(irq_data, can_reserve);
da5dd9e8 TG	459	if (ret)
	460	goto cleanup;
	461	}
	462
	463	/*
	464	* If these interrupts use reservation mode, clear the activated bit
	465	* so request_irq() will assign the final vector.
	466	*/
	467	if (can_reserve) {
	468	for_each_msi_entry(desc, dev) {
f3b0946d	469	irq_data = irq_domain_get_irq_data(domain, desc->irq);
da5dd9e8	470	irqd_clr_activated(irq_data);
f3b0946d	471	}
d9109698	472	}
d9109698	473	return 0;
bb9b428a TG	474
	475	cleanup:
	476	for_each_msi_entry(desc, dev) {
	477	struct irq_data *irqd;
	478
	479	if (desc->irq == virq)
	480	break;
	481
	482	irqd = irq_domain_get_irq_data(domain, desc->irq);
	483	if (irqd_is_activated(irqd))
	484	irq_domain_deactivate_irq(irqd);
	485	}
	486	msi_domain_free_irqs(domain, dev);
	487	return ret;
d9109698 JL	488	}
	489
	490	/**
	491	* msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
	492	* @domain: The domain to managing the interrupts
	493	* @dev: Pointer to device struct of the device for which the interrupts
	494	* are free
	495	*/
	496	void msi_domain_free_irqs(struct irq_domain domain, struct device dev)
	497	{
	498	struct msi_desc *desc;
	499
	500	for_each_msi_entry(desc, dev) {
fe0c52fc MZ	501	/*
	502	* We might have failed to allocate an MSI early
	503	* enough that there is no IRQ associated to this
	504	* entry. If that's the case, don't do anything.
	505	*/
	506	if (desc->irq) {
	507	irq_domain_free_irqs(desc->irq, desc->nvec_used);
	508	desc->irq = 0;
	509	}
d9109698 JL	510	}
	511	}
	512
f3cf8bb0 JL	513	/**
	514	* msi_get_domain_info - Get the MSI interrupt domain info for @domain
	515	* @domain: The interrupt domain to retrieve data from
	516	*
	517	* Returns the pointer to the msi_domain_info stored in
	518	* @domain->host_data.
	519	*/
	520	struct msi_domain_info msi_get_domain_info(struct irq_domain domain)
	521	{
	522	return (struct msi_domain_info *)domain->host_data;
	523	}
	524
	525	#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */