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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <[email protected]> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, [email protected] |
10 | * or [email protected]: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <[email protected]> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 | 15 | * Author: MontaVista Software, Inc. |
ec7eabdd | 16 | * [email protected] or [email protected] |
1da177e4 LT |
17 | * |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
30 | * with this program; if not, write to the Free Software Foundation, Inc., | |
31 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
32 | * | |
33 | * ######################################################################## | |
34 | * | |
6aa20a22 | 35 | * |
1da177e4 | 36 | */ |
215e17be FF |
37 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
38 | ||
bc36b428 | 39 | #include <linux/capability.h> |
d791c2bd | 40 | #include <linux/dma-mapping.h> |
1da177e4 LT |
41 | #include <linux/module.h> |
42 | #include <linux/kernel.h> | |
1da177e4 LT |
43 | #include <linux/string.h> |
44 | #include <linux/timer.h> | |
45 | #include <linux/errno.h> | |
46 | #include <linux/in.h> | |
47 | #include <linux/ioport.h> | |
48 | #include <linux/bitops.h> | |
49 | #include <linux/slab.h> | |
50 | #include <linux/interrupt.h> | |
1da177e4 LT |
51 | #include <linux/init.h> |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/etherdevice.h> | |
54 | #include <linux/ethtool.h> | |
55 | #include <linux/mii.h> | |
56 | #include <linux/skbuff.h> | |
57 | #include <linux/delay.h> | |
8cd35da0 | 58 | #include <linux/crc32.h> |
0638dec0 | 59 | #include <linux/phy.h> |
bd2302c2 | 60 | #include <linux/platform_device.h> |
49a42c08 FF |
61 | #include <linux/cpu.h> |
62 | #include <linux/io.h> | |
25b31cb1 | 63 | |
1da177e4 LT |
64 | #include <asm/mipsregs.h> |
65 | #include <asm/irq.h> | |
1da177e4 LT |
66 | #include <asm/processor.h> |
67 | ||
25b31cb1 | 68 | #include <au1000.h> |
bd2302c2 | 69 | #include <au1xxx_eth.h> |
25b31cb1 YY |
70 | #include <prom.h> |
71 | ||
1da177e4 LT |
72 | #include "au1000_eth.h" |
73 | ||
74 | #ifdef AU1000_ETH_DEBUG | |
75 | static int au1000_debug = 5; | |
76 | #else | |
77 | static int au1000_debug = 3; | |
78 | #endif | |
79 | ||
7cd2e6e3 FF |
80 | #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
81 | NETIF_MSG_PROBE | \ | |
82 | NETIF_MSG_LINK) | |
83 | ||
89be0501 | 84 | #define DRV_NAME "au1000_eth" |
8020eb82 | 85 | #define DRV_VERSION "1.7" |
1da177e4 LT |
86 | #define DRV_AUTHOR "Pete Popov <[email protected]>" |
87 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
88 | ||
89 | MODULE_AUTHOR(DRV_AUTHOR); | |
90 | MODULE_DESCRIPTION(DRV_DESC); | |
91 | MODULE_LICENSE("GPL"); | |
13130c7a | 92 | MODULE_VERSION(DRV_VERSION); |
1da177e4 | 93 | |
1da177e4 LT |
94 | /* |
95 | * Theory of operation | |
96 | * | |
6aa20a22 JG |
97 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
98 | * There are four receive and four transmit descriptors. These | |
99 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
100 | * hardware registers. |
101 | * | |
102 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 103 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
104 | * hardware registers, however, are still mapped at KSEG1 to |
105 | * make sure there's no out-of-order writes, and that all writes | |
106 | * complete immediately. | |
107 | */ | |
108 | ||
0638dec0 HVR |
109 | /* |
110 | * board-specific configurations | |
111 | * | |
112 | * PHY detection algorithm | |
113 | * | |
bd2302c2 | 114 | * If phy_static_config is undefined, the PHY setup is |
0638dec0 HVR |
115 | * autodetected: |
116 | * | |
117 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
bd2302c2 | 118 | * selecting the first (or last, if phy_search_highest_addr is |
0638dec0 HVR |
119 | * defined) PHY address not already claimed by another netdev. |
120 | * | |
121 | * If nothing was found that way when searching for the 2nd ethernet | |
bd2302c2 | 122 | * controller's PHY and phy1_search_mac0 is defined, then |
0638dec0 HVR |
123 | * the first MII bus is searched as well for an unclaimed PHY; this is |
124 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
125 | * bus. | |
126 | * | |
127 | * Finally, if no PHY is found, then the corresponding ethernet | |
128 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
129 | */ |
130 | ||
bd2302c2 | 131 | /* autodetection defaults: phy1_search_mac0 */ |
1da177e4 | 132 | |
0638dec0 HVR |
133 | /* static PHY setup |
134 | * | |
135 | * most boards PHY setup should be detectable properly with the | |
136 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
137 | * you have a switch attached, or want to use the PHY's interrupt | |
138 | * notification capabilities) you can provide a static PHY | |
139 | * configuration here | |
140 | * | |
141 | * IRQs may only be set, if a PHY address was configured | |
142 | * If a PHY address is given, also a bus id is required to be set | |
143 | * | |
144 | * ps: make sure the used irqs are configured properly in the board | |
145 | * specific irq-map | |
146 | */ | |
1da177e4 | 147 | |
eb049630 | 148 | static void au1000_enable_mac(struct net_device *dev, int force_reset) |
5ef3041e FF |
149 | { |
150 | unsigned long flags; | |
151 | struct au1000_private *aup = netdev_priv(dev); | |
152 | ||
153 | spin_lock_irqsave(&aup->lock, flags); | |
154 | ||
ec7eabdd | 155 | if (force_reset || (!aup->mac_enabled)) { |
462ca99c | 156 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
5ef3041e | 157 | au_sync_delay(2); |
d0e7cb5d | 158 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
462ca99c | 159 | | MAC_EN_CLOCK_ENABLE), aup->enable); |
5ef3041e FF |
160 | au_sync_delay(2); |
161 | ||
162 | aup->mac_enabled = 1; | |
163 | } | |
164 | ||
165 | spin_unlock_irqrestore(&aup->lock, flags); | |
166 | } | |
167 | ||
0638dec0 HVR |
168 | /* |
169 | * MII operations | |
170 | */ | |
1210dde7 | 171 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 172 | { |
454d7c9b | 173 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
174 | u32 *const mii_control_reg = &aup->mac->mii_control; |
175 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
176 | u32 timedout = 20; |
177 | u32 mii_control; | |
178 | ||
d0e7cb5d | 179 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
180 | mdelay(1); |
181 | if (--timedout == 0) { | |
5368c726 | 182 | netdev_err(dev, "read_MII busy timeout!!\n"); |
1da177e4 LT |
183 | return -1; |
184 | } | |
185 | } | |
186 | ||
6aa20a22 | 187 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 188 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 | 189 | |
d0e7cb5d | 190 | writel(mii_control, mii_control_reg); |
1da177e4 LT |
191 | |
192 | timedout = 20; | |
d0e7cb5d | 193 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
194 | mdelay(1); |
195 | if (--timedout == 0) { | |
5368c726 | 196 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
1da177e4 LT |
197 | return -1; |
198 | } | |
199 | } | |
d0e7cb5d | 200 | return readl(mii_data_reg); |
1da177e4 LT |
201 | } |
202 | ||
1210dde7 AB |
203 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
204 | int reg, u16 value) | |
1da177e4 | 205 | { |
454d7c9b | 206 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
207 | u32 *const mii_control_reg = &aup->mac->mii_control; |
208 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
209 | u32 timedout = 20; |
210 | u32 mii_control; | |
211 | ||
d0e7cb5d | 212 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
213 | mdelay(1); |
214 | if (--timedout == 0) { | |
5368c726 | 215 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
1da177e4 LT |
216 | return; |
217 | } | |
218 | } | |
219 | ||
6aa20a22 | 220 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 221 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 | 222 | |
d0e7cb5d FF |
223 | writel(value, mii_data_reg); |
224 | writel(mii_control, mii_control_reg); | |
1da177e4 LT |
225 | } |
226 | ||
1210dde7 | 227 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
228 | { |
229 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
dc99839c FF |
230 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) |
231 | */ | |
0638dec0 HVR |
232 | struct net_device *const dev = bus->priv; |
233 | ||
dc99839c FF |
234 | /* make sure the MAC associated with this |
235 | * mii_bus is enabled | |
236 | */ | |
237 | au1000_enable_mac(dev, 0); | |
238 | ||
1210dde7 | 239 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 240 | } |
1da177e4 | 241 | |
1210dde7 AB |
242 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
243 | u16 value) | |
1da177e4 | 244 | { |
0638dec0 | 245 | struct net_device *const dev = bus->priv; |
1da177e4 | 246 | |
dc99839c FF |
247 | /* make sure the MAC associated with this |
248 | * mii_bus is enabled | |
249 | */ | |
250 | au1000_enable_mac(dev, 0); | |
251 | ||
1210dde7 | 252 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 253 | return 0; |
1da177e4 LT |
254 | } |
255 | ||
1210dde7 | 256 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 257 | { |
0638dec0 | 258 | struct net_device *const dev = bus->priv; |
1da177e4 | 259 | |
dc99839c FF |
260 | /* make sure the MAC associated with this |
261 | * mii_bus is enabled | |
262 | */ | |
263 | au1000_enable_mac(dev, 0); | |
264 | ||
0638dec0 HVR |
265 | return 0; |
266 | } | |
1da177e4 | 267 | |
eb049630 | 268 | static void au1000_hard_stop(struct net_device *dev) |
5ef3041e FF |
269 | { |
270 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 271 | u32 reg; |
5ef3041e | 272 | |
5368c726 | 273 | netif_dbg(aup, drv, dev, "hard stop\n"); |
5ef3041e | 274 | |
d0e7cb5d FF |
275 | reg = readl(&aup->mac->control); |
276 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
277 | writel(reg, &aup->mac->control); | |
5ef3041e FF |
278 | au_sync_delay(10); |
279 | } | |
280 | ||
eb049630 | 281 | static void au1000_enable_rx_tx(struct net_device *dev) |
5ef3041e FF |
282 | { |
283 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 284 | u32 reg; |
5ef3041e | 285 | |
5368c726 | 286 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
5ef3041e | 287 | |
d0e7cb5d FF |
288 | reg = readl(&aup->mac->control); |
289 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
290 | writel(reg, &aup->mac->control); | |
5ef3041e FF |
291 | au_sync_delay(10); |
292 | } | |
293 | ||
294 | static void | |
295 | au1000_adjust_link(struct net_device *dev) | |
296 | { | |
297 | struct au1000_private *aup = netdev_priv(dev); | |
298 | struct phy_device *phydev = aup->phy_dev; | |
299 | unsigned long flags; | |
d0e7cb5d | 300 | u32 reg; |
5ef3041e FF |
301 | |
302 | int status_change = 0; | |
303 | ||
304 | BUG_ON(!aup->phy_dev); | |
305 | ||
306 | spin_lock_irqsave(&aup->lock, flags); | |
307 | ||
308 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
2cc3c6b1 | 309 | /* speed changed */ |
5ef3041e | 310 | |
2cc3c6b1 | 311 | switch (phydev->speed) { |
5ef3041e FF |
312 | case SPEED_10: |
313 | case SPEED_100: | |
314 | break; | |
315 | default: | |
5368c726 FF |
316 | netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", |
317 | phydev->speed); | |
5ef3041e FF |
318 | break; |
319 | } | |
320 | ||
321 | aup->old_speed = phydev->speed; | |
322 | ||
323 | status_change = 1; | |
324 | } | |
325 | ||
326 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
2cc3c6b1 | 327 | /* duplex mode changed */ |
5ef3041e FF |
328 | |
329 | /* switching duplex mode requires to disable rx and tx! */ | |
eb049630 | 330 | au1000_hard_stop(dev); |
5ef3041e | 331 | |
d0e7cb5d FF |
332 | reg = readl(&aup->mac->control); |
333 | if (DUPLEX_FULL == phydev->duplex) { | |
334 | reg |= MAC_FULL_DUPLEX; | |
335 | reg &= ~MAC_DISABLE_RX_OWN; | |
336 | } else { | |
337 | reg &= ~MAC_FULL_DUPLEX; | |
338 | reg |= MAC_DISABLE_RX_OWN; | |
339 | } | |
340 | writel(reg, &aup->mac->control); | |
5ef3041e FF |
341 | au_sync_delay(1); |
342 | ||
eb049630 | 343 | au1000_enable_rx_tx(dev); |
5ef3041e FF |
344 | aup->old_duplex = phydev->duplex; |
345 | ||
346 | status_change = 1; | |
347 | } | |
348 | ||
2cc3c6b1 FF |
349 | if (phydev->link != aup->old_link) { |
350 | /* link state changed */ | |
5ef3041e FF |
351 | |
352 | if (!phydev->link) { | |
353 | /* link went down */ | |
354 | aup->old_speed = 0; | |
355 | aup->old_duplex = -1; | |
356 | } | |
357 | ||
358 | aup->old_link = phydev->link; | |
359 | status_change = 1; | |
360 | } | |
361 | ||
362 | spin_unlock_irqrestore(&aup->lock, flags); | |
363 | ||
364 | if (status_change) { | |
365 | if (phydev->link) | |
5368c726 FF |
366 | netdev_info(dev, "link up (%d/%s)\n", |
367 | phydev->speed, | |
5ef3041e FF |
368 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); |
369 | else | |
5368c726 | 370 | netdev_info(dev, "link down\n"); |
5ef3041e FF |
371 | } |
372 | } | |
373 | ||
ec7eabdd | 374 | static int au1000_mii_probe(struct net_device *dev) |
0638dec0 | 375 | { |
454d7c9b | 376 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 | 377 | struct phy_device *phydev = NULL; |
18b8e15b | 378 | int phy_addr; |
0638dec0 | 379 | |
bd2302c2 FF |
380 | if (aup->phy_static_config) { |
381 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
0638dec0 | 382 | |
bd2302c2 FF |
383 | if (aup->phy_addr) |
384 | phydev = aup->mii_bus->phy_map[aup->phy_addr]; | |
385 | else | |
5368c726 | 386 | netdev_info(dev, "using PHY-less setup\n"); |
0638dec0 | 387 | return 0; |
18b8e15b | 388 | } |
0638dec0 | 389 | |
18b8e15b | 390 | /* find the first (lowest address) PHY |
dc99839c FF |
391 | * on the current MAC's MII bus |
392 | */ | |
18b8e15b FF |
393 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) |
394 | if (aup->mii_bus->phy_map[phy_addr]) { | |
395 | phydev = aup->mii_bus->phy_map[phy_addr]; | |
396 | if (!aup->phy_search_highest_addr) | |
397 | /* break out with first one found */ | |
398 | break; | |
399 | } | |
0638dec0 | 400 | |
18b8e15b FF |
401 | if (aup->phy1_search_mac0) { |
402 | /* try harder to find a PHY */ | |
403 | if (!phydev && (aup->mac_id == 1)) { | |
404 | /* no PHY found, maybe we have a dual PHY? */ | |
405 | dev_info(&dev->dev, ": no PHY found on MAC1, " | |
406 | "let's see if it's attached to MAC0...\n"); | |
407 | ||
408 | /* find the first (lowest address) non-attached | |
409 | * PHY on the MAC0 MII bus | |
410 | */ | |
411 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
412 | struct phy_device *const tmp_phydev = | |
413 | aup->mii_bus->phy_map[phy_addr]; | |
414 | ||
415 | if (aup->mac_id == 1) | |
416 | break; | |
417 | ||
418 | /* no PHY here... */ | |
419 | if (!tmp_phydev) | |
420 | continue; | |
421 | ||
422 | /* already claimed by MAC0 */ | |
423 | if (tmp_phydev->attached_dev) | |
424 | continue; | |
425 | ||
426 | phydev = tmp_phydev; | |
427 | break; /* found it */ | |
bd2302c2 | 428 | } |
1da177e4 LT |
429 | } |
430 | } | |
1da177e4 | 431 | |
0638dec0 | 432 | if (!phydev) { |
5368c726 | 433 | netdev_err(dev, "no PHY found\n"); |
1da177e4 LT |
434 | return -1; |
435 | } | |
436 | ||
0638dec0 | 437 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
438 | BUG_ON(phydev->attached_dev); |
439 | ||
db1d7bf7 KS |
440 | phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link, |
441 | 0, PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
442 | |
443 | if (IS_ERR(phydev)) { | |
5368c726 | 444 | netdev_err(dev, "Could not attach to PHY\n"); |
0638dec0 HVR |
445 | return PTR_ERR(phydev); |
446 | } | |
447 | ||
448 | /* mask with MAC supported features */ | |
449 | phydev->supported &= (SUPPORTED_10baseT_Half | |
450 | | SUPPORTED_10baseT_Full | |
451 | | SUPPORTED_100baseT_Half | |
452 | | SUPPORTED_100baseT_Full | |
453 | | SUPPORTED_Autoneg | |
454 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
455 | | SUPPORTED_MII | |
456 | | SUPPORTED_TP); | |
457 | ||
458 | phydev->advertising = phydev->supported; | |
459 | ||
460 | aup->old_link = 0; | |
461 | aup->old_speed = 0; | |
462 | aup->old_duplex = -1; | |
463 | aup->phy_dev = phydev; | |
464 | ||
5368c726 FF |
465 | netdev_info(dev, "attached PHY driver [%s] " |
466 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
db1d7bf7 | 467 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); |
1da177e4 LT |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
472 | ||
473 | /* | |
474 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 475 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
476 | * both, receive and transmit operations. |
477 | */ | |
3441592b | 478 | static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) |
1da177e4 | 479 | { |
3441592b | 480 | struct db_dest *pDB; |
1da177e4 LT |
481 | pDB = aup->pDBfree; |
482 | ||
ec7eabdd | 483 | if (pDB) |
1da177e4 | 484 | aup->pDBfree = pDB->pnext; |
ec7eabdd | 485 | |
1da177e4 LT |
486 | return pDB; |
487 | } | |
488 | ||
3441592b | 489 | void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) |
1da177e4 | 490 | { |
3441592b | 491 | struct db_dest *pDBfree = aup->pDBfree; |
1da177e4 LT |
492 | if (pDBfree) |
493 | pDBfree->pnext = pDB; | |
494 | aup->pDBfree = pDB; | |
495 | } | |
496 | ||
eb049630 | 497 | static void au1000_reset_mac_unlocked(struct net_device *dev) |
0638dec0 | 498 | { |
454d7c9b | 499 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
500 | int i; |
501 | ||
eb049630 | 502 | au1000_hard_stop(dev); |
0638dec0 | 503 | |
462ca99c | 504 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
0638dec0 | 505 | au_sync_delay(2); |
462ca99c | 506 | writel(0, aup->enable); |
0638dec0 HVR |
507 | au_sync_delay(2); |
508 | ||
1da177e4 LT |
509 | aup->tx_full = 0; |
510 | for (i = 0; i < NUM_RX_DMA; i++) { | |
511 | /* reset control bits */ | |
512 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
513 | } | |
514 | for (i = 0; i < NUM_TX_DMA; i++) { | |
515 | /* reset control bits */ | |
516 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
517 | } | |
0638dec0 HVR |
518 | |
519 | aup->mac_enabled = 0; | |
520 | ||
1da177e4 LT |
521 | } |
522 | ||
eb049630 | 523 | static void au1000_reset_mac(struct net_device *dev) |
0638dec0 | 524 | { |
454d7c9b | 525 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
526 | unsigned long flags; |
527 | ||
5368c726 FF |
528 | netif_dbg(aup, hw, dev, "reset mac, aup %x\n", |
529 | (unsigned)aup); | |
0638dec0 HVR |
530 | |
531 | spin_lock_irqsave(&aup->lock, flags); | |
532 | ||
ec7eabdd | 533 | au1000_reset_mac_unlocked(dev); |
0638dec0 HVR |
534 | |
535 | spin_unlock_irqrestore(&aup->lock, flags); | |
536 | } | |
1da177e4 | 537 | |
6aa20a22 | 538 | /* |
1da177e4 LT |
539 | * Setup the receive and transmit "rings". These pointers are the addresses |
540 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
541 | * these are not descriptors sitting in memory. | |
542 | */ | |
6aa20a22 | 543 | static void |
eb049630 | 544 | au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) |
1da177e4 LT |
545 | { |
546 | int i; | |
547 | ||
548 | for (i = 0; i < NUM_RX_DMA; i++) { | |
6aa20a22 | 549 | aup->rx_dma_ring[i] = |
d0e7cb5d | 550 | (struct rx_dma *) |
18b8e15b | 551 | (rx_base + sizeof(struct rx_dma)*i); |
1da177e4 LT |
552 | } |
553 | for (i = 0; i < NUM_TX_DMA; i++) { | |
6aa20a22 | 554 | aup->tx_dma_ring[i] = |
d0e7cb5d | 555 | (struct tx_dma *) |
18b8e15b | 556 | (tx_base + sizeof(struct tx_dma)*i); |
1da177e4 LT |
557 | } |
558 | } | |
559 | ||
0638dec0 HVR |
560 | /* |
561 | * ethtool operations | |
562 | */ | |
1da177e4 | 563 | |
0638dec0 | 564 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 565 | { |
454d7c9b | 566 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 567 | |
0638dec0 HVR |
568 | if (aup->phy_dev) |
569 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 570 | |
0638dec0 | 571 | return -EINVAL; |
1da177e4 LT |
572 | } |
573 | ||
0638dec0 | 574 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 575 | { |
454d7c9b | 576 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 577 | |
0638dec0 HVR |
578 | if (!capable(CAP_NET_ADMIN)) |
579 | return -EPERM; | |
1da177e4 | 580 | |
0638dec0 HVR |
581 | if (aup->phy_dev) |
582 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 583 | |
0638dec0 | 584 | return -EINVAL; |
1da177e4 LT |
585 | } |
586 | ||
587 | static void | |
588 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
589 | { | |
454d7c9b | 590 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
591 | |
592 | strcpy(info->driver, DRV_NAME); | |
593 | strcpy(info->version, DRV_VERSION); | |
594 | info->fw_version[0] = '\0'; | |
595 | sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id); | |
596 | info->regdump_len = 0; | |
597 | } | |
598 | ||
7cd2e6e3 FF |
599 | static void au1000_set_msglevel(struct net_device *dev, u32 value) |
600 | { | |
601 | struct au1000_private *aup = netdev_priv(dev); | |
602 | aup->msg_enable = value; | |
603 | } | |
604 | ||
605 | static u32 au1000_get_msglevel(struct net_device *dev) | |
606 | { | |
607 | struct au1000_private *aup = netdev_priv(dev); | |
608 | return aup->msg_enable; | |
609 | } | |
610 | ||
7282d491 | 611 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
612 | .get_settings = au1000_get_settings, |
613 | .set_settings = au1000_set_settings, | |
614 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 615 | .get_link = ethtool_op_get_link, |
7cd2e6e3 FF |
616 | .get_msglevel = au1000_get_msglevel, |
617 | .set_msglevel = au1000_set_msglevel, | |
1da177e4 LT |
618 | }; |
619 | ||
5ef3041e FF |
620 | |
621 | /* | |
622 | * Initialize the interface. | |
623 | * | |
624 | * When the device powers up, the clocks are disabled and the | |
625 | * mac is in reset state. When the interface is closed, we | |
626 | * do the same -- reset the device and disable the clocks to | |
627 | * conserve power. Thus, whenever au1000_init() is called, | |
628 | * the device should already be in reset state. | |
629 | */ | |
630 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 631 | { |
5ef3041e FF |
632 | struct au1000_private *aup = netdev_priv(dev); |
633 | unsigned long flags; | |
634 | int i; | |
635 | u32 control; | |
89be0501 | 636 | |
5368c726 | 637 | netif_dbg(aup, hw, dev, "au1000_init\n"); |
1da177e4 | 638 | |
5ef3041e | 639 | /* bring the device out of reset */ |
eb049630 | 640 | au1000_enable_mac(dev, 1); |
89be0501 | 641 | |
5ef3041e | 642 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 643 | |
d0e7cb5d | 644 | writel(0, &aup->mac->control); |
5ef3041e FF |
645 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; |
646 | aup->tx_tail = aup->tx_head; | |
647 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 648 | |
d0e7cb5d FF |
649 | writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], |
650 | &aup->mac->mac_addr_high); | |
651 | writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
652 | dev->dev_addr[1]<<8 | dev->dev_addr[0], | |
653 | &aup->mac->mac_addr_low); | |
5ef3041e | 654 | |
18b8e15b | 655 | |
ec7eabdd | 656 | for (i = 0; i < NUM_RX_DMA; i++) |
5ef3041e | 657 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; |
ec7eabdd | 658 | |
5ef3041e | 659 | au_sync(); |
1da177e4 | 660 | |
5ef3041e FF |
661 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
662 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
663 | control |= MAC_BIG_ENDIAN; | |
664 | #endif | |
665 | if (aup->phy_dev) { | |
666 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
667 | control |= MAC_FULL_DUPLEX; | |
668 | else | |
669 | control |= MAC_DISABLE_RX_OWN; | |
670 | } else { /* PHY-less op, assume full-duplex */ | |
671 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
672 | } |
673 | ||
d0e7cb5d FF |
674 | writel(control, &aup->mac->control); |
675 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ | |
5ef3041e | 676 | au_sync(); |
1da177e4 | 677 | |
5ef3041e FF |
678 | spin_unlock_irqrestore(&aup->lock, flags); |
679 | return 0; | |
680 | } | |
1da177e4 | 681 | |
eb049630 | 682 | static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) |
5ef3041e | 683 | { |
5ef3041e | 684 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 685 | |
5ef3041e FF |
686 | ps->rx_packets++; |
687 | if (status & RX_MCAST_FRAME) | |
688 | ps->multicast++; | |
1da177e4 | 689 | |
5ef3041e FF |
690 | if (status & RX_ERROR) { |
691 | ps->rx_errors++; | |
692 | if (status & RX_MISSED_FRAME) | |
693 | ps->rx_missed_errors++; | |
4989ccb2 | 694 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
695 | ps->rx_length_errors++; |
696 | if (status & RX_CRC_ERROR) | |
697 | ps->rx_crc_errors++; | |
698 | if (status & RX_COLL) | |
699 | ps->collisions++; | |
2cc3c6b1 | 700 | } else |
5ef3041e | 701 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
298cf9be | 702 | |
1da177e4 LT |
703 | } |
704 | ||
6aa20a22 | 705 | /* |
5ef3041e | 706 | * Au1000 receive routine. |
1da177e4 | 707 | */ |
5ef3041e | 708 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 709 | { |
454d7c9b | 710 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 711 | struct sk_buff *skb; |
d0e7cb5d | 712 | struct rx_dma *prxd; |
5ef3041e | 713 | u32 buff_stat, status; |
3441592b | 714 | struct db_dest *pDB; |
5ef3041e | 715 | u32 frmlen; |
1da177e4 | 716 | |
5368c726 | 717 | netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); |
1da177e4 | 718 | |
5ef3041e FF |
719 | prxd = aup->rx_dma_ring[aup->rx_head]; |
720 | buff_stat = prxd->buff_stat; | |
721 | while (buff_stat & RX_T_DONE) { | |
722 | status = prxd->status; | |
723 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
eb049630 | 724 | au1000_update_rx_stats(dev, status); |
5ef3041e | 725 | if (!(status & RX_ERROR)) { |
1da177e4 | 726 | |
5ef3041e FF |
727 | /* good frame */ |
728 | frmlen = (status & RX_FRAME_LEN_MASK); | |
729 | frmlen -= 4; /* Remove FCS */ | |
730 | skb = dev_alloc_skb(frmlen + 2); | |
731 | if (skb == NULL) { | |
5368c726 | 732 | netdev_err(dev, "Memory squeeze, dropping packet.\n"); |
5ef3041e FF |
733 | dev->stats.rx_dropped++; |
734 | continue; | |
735 | } | |
736 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
737 | skb_copy_to_linear_data(skb, | |
738 | (unsigned char *)pDB->vaddr, frmlen); | |
739 | skb_put(skb, frmlen); | |
740 | skb->protocol = eth_type_trans(skb, dev); | |
741 | netif_rx(skb); /* pass the packet to upper layers */ | |
2cc3c6b1 | 742 | } else { |
5ef3041e | 743 | if (au1000_debug > 4) { |
215e17be | 744 | pr_err("rx_error(s):"); |
5ef3041e | 745 | if (status & RX_MISSED_FRAME) |
215e17be | 746 | pr_cont(" miss"); |
5ef3041e | 747 | if (status & RX_WDOG_TIMER) |
215e17be | 748 | pr_cont(" wdog"); |
5ef3041e | 749 | if (status & RX_RUNT) |
215e17be | 750 | pr_cont(" runt"); |
5ef3041e | 751 | if (status & RX_OVERLEN) |
215e17be | 752 | pr_cont(" overlen"); |
5ef3041e | 753 | if (status & RX_COLL) |
215e17be | 754 | pr_cont(" coll"); |
5ef3041e | 755 | if (status & RX_MII_ERROR) |
215e17be | 756 | pr_cont(" mii error"); |
5ef3041e | 757 | if (status & RX_CRC_ERROR) |
215e17be | 758 | pr_cont(" crc error"); |
5ef3041e | 759 | if (status & RX_LEN_ERROR) |
215e17be | 760 | pr_cont(" len error"); |
5ef3041e | 761 | if (status & RX_U_CNTRL_FRAME) |
215e17be FF |
762 | pr_cont(" u control frame"); |
763 | pr_cont("\n"); | |
5ef3041e FF |
764 | } |
765 | } | |
766 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
767 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
768 | au_sync(); | |
1da177e4 | 769 | |
5ef3041e FF |
770 | /* next descriptor */ |
771 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
772 | buff_stat = prxd->buff_stat; | |
1da177e4 | 773 | } |
1da177e4 LT |
774 | return 0; |
775 | } | |
776 | ||
eb049630 | 777 | static void au1000_update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 778 | { |
454d7c9b | 779 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 780 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 781 | |
5ef3041e FF |
782 | if (status & TX_FRAME_ABORTED) { |
783 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
784 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
785 | /* any other tx errors are only valid | |
dc99839c FF |
786 | * in half duplex mode |
787 | */ | |
5ef3041e FF |
788 | ps->tx_errors++; |
789 | ps->tx_aborted_errors++; | |
790 | } | |
2cc3c6b1 | 791 | } else { |
5ef3041e FF |
792 | ps->tx_errors++; |
793 | ps->tx_aborted_errors++; | |
794 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
795 | ps->tx_carrier_errors++; | |
796 | } | |
797 | } | |
798 | } | |
0638dec0 | 799 | |
5ef3041e FF |
800 | /* |
801 | * Called from the interrupt service routine to acknowledge | |
802 | * the TX DONE bits. This is a must if the irq is setup as | |
803 | * edge triggered. | |
804 | */ | |
805 | static void au1000_tx_ack(struct net_device *dev) | |
806 | { | |
807 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 808 | struct tx_dma *ptxd; |
0638dec0 | 809 | |
5ef3041e | 810 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 811 | |
5ef3041e | 812 | while (ptxd->buff_stat & TX_T_DONE) { |
eb049630 | 813 | au1000_update_tx_stats(dev, ptxd->status); |
5ef3041e FF |
814 | ptxd->buff_stat &= ~TX_T_DONE; |
815 | ptxd->len = 0; | |
816 | au_sync(); | |
0638dec0 | 817 | |
5ef3041e FF |
818 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
819 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 820 | |
5ef3041e FF |
821 | if (aup->tx_full) { |
822 | aup->tx_full = 0; | |
823 | netif_wake_queue(dev); | |
824 | } | |
1da177e4 | 825 | } |
5ef3041e | 826 | } |
1da177e4 | 827 | |
5ef3041e FF |
828 | /* |
829 | * Au1000 interrupt service routine. | |
830 | */ | |
831 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
832 | { | |
833 | struct net_device *dev = dev_id; | |
1da177e4 | 834 | |
5ef3041e FF |
835 | /* Handle RX interrupts first to minimize chance of overrun */ |
836 | ||
837 | au1000_rx(dev); | |
838 | au1000_tx_ack(dev); | |
839 | return IRQ_RETVAL(1); | |
1da177e4 LT |
840 | } |
841 | ||
842 | static int au1000_open(struct net_device *dev) | |
843 | { | |
844 | int retval; | |
454d7c9b | 845 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 846 | |
5368c726 | 847 | netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); |
1da177e4 | 848 | |
2cc3c6b1 FF |
849 | retval = request_irq(dev->irq, au1000_interrupt, 0, |
850 | dev->name, dev); | |
851 | if (retval) { | |
5368c726 | 852 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
0638dec0 HVR |
853 | return retval; |
854 | } | |
855 | ||
2cc3c6b1 FF |
856 | retval = au1000_init(dev); |
857 | if (retval) { | |
5368c726 | 858 | netdev_err(dev, "error in au1000_init\n"); |
1da177e4 LT |
859 | free_irq(dev->irq, dev); |
860 | return retval; | |
861 | } | |
1da177e4 | 862 | |
0638dec0 HVR |
863 | if (aup->phy_dev) { |
864 | /* cause the PHY state machine to schedule a link state check */ | |
865 | aup->phy_dev->state = PHY_CHANGELINK; | |
866 | phy_start(aup->phy_dev); | |
1da177e4 LT |
867 | } |
868 | ||
0638dec0 | 869 | netif_start_queue(dev); |
1da177e4 | 870 | |
5368c726 | 871 | netif_dbg(aup, drv, dev, "open: Initialization done.\n"); |
1da177e4 LT |
872 | |
873 | return 0; | |
874 | } | |
875 | ||
876 | static int au1000_close(struct net_device *dev) | |
877 | { | |
0638dec0 | 878 | unsigned long flags; |
454d7c9b | 879 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 | 880 | |
5368c726 | 881 | netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); |
1da177e4 | 882 | |
0638dec0 HVR |
883 | if (aup->phy_dev) |
884 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
885 | |
886 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 | 887 | |
ec7eabdd | 888 | au1000_reset_mac_unlocked(dev); |
0638dec0 | 889 | |
1da177e4 LT |
890 | /* stop the device */ |
891 | netif_stop_queue(dev); | |
892 | ||
893 | /* disable the interrupt */ | |
894 | free_irq(dev->irq, dev); | |
895 | spin_unlock_irqrestore(&aup->lock, flags); | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
1da177e4 LT |
900 | /* |
901 | * Au1000 transmit routine. | |
902 | */ | |
61357325 | 903 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 904 | { |
454d7c9b | 905 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 906 | struct net_device_stats *ps = &dev->stats; |
d0e7cb5d | 907 | struct tx_dma *ptxd; |
1da177e4 | 908 | u32 buff_stat; |
3441592b | 909 | struct db_dest *pDB; |
1da177e4 LT |
910 | int i; |
911 | ||
5368c726 FF |
912 | netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", |
913 | (unsigned)aup, skb->len, | |
1da177e4 LT |
914 | skb->data, aup->tx_head); |
915 | ||
916 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
917 | buff_stat = ptxd->buff_stat; | |
918 | if (buff_stat & TX_DMA_ENABLE) { | |
919 | /* We've wrapped around and the transmitter is still busy */ | |
920 | netif_stop_queue(dev); | |
921 | aup->tx_full = 1; | |
5b548140 | 922 | return NETDEV_TX_BUSY; |
2cc3c6b1 | 923 | } else if (buff_stat & TX_T_DONE) { |
eb049630 | 924 | au1000_update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
925 | ptxd->len = 0; |
926 | } | |
927 | ||
928 | if (aup->tx_full) { | |
929 | aup->tx_full = 0; | |
930 | netif_wake_queue(dev); | |
931 | } | |
932 | ||
933 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
bd2302c2 | 934 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 | 935 | if (skb->len < ETH_ZLEN) { |
ec7eabdd | 936 | for (i = skb->len; i < ETH_ZLEN; i++) |
1da177e4 | 937 | ((char *)pDB->vaddr)[i] = 0; |
ec7eabdd | 938 | |
1da177e4 | 939 | ptxd->len = ETH_ZLEN; |
2cc3c6b1 | 940 | } else |
5ef3041e | 941 | ptxd->len = skb->len; |
1da177e4 | 942 | |
5ef3041e FF |
943 | ps->tx_packets++; |
944 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 945 | |
5ef3041e FF |
946 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
947 | au_sync(); | |
948 | dev_kfree_skb(skb); | |
949 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
6ed10654 | 950 | return NETDEV_TX_OK; |
1da177e4 LT |
951 | } |
952 | ||
1da177e4 LT |
953 | /* |
954 | * The Tx ring has been full longer than the watchdog timeout | |
955 | * value. The transmitter must be hung? | |
956 | */ | |
957 | static void au1000_tx_timeout(struct net_device *dev) | |
958 | { | |
5368c726 | 959 | netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); |
eb049630 | 960 | au1000_reset_mac(dev); |
1da177e4 | 961 | au1000_init(dev); |
1ae5dc34 | 962 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
963 | netif_wake_queue(dev); |
964 | } | |
965 | ||
d9a92cee | 966 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 967 | { |
454d7c9b | 968 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d | 969 | u32 reg; |
1da177e4 | 970 | |
18b8e15b | 971 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); |
d0e7cb5d | 972 | reg = readl(&aup->mac->control); |
1da177e4 | 973 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
d0e7cb5d | 974 | reg |= MAC_PROMISCUOUS; |
1da177e4 | 975 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 976 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
d0e7cb5d FF |
977 | reg |= MAC_PASS_ALL_MULTI; |
978 | reg &= ~MAC_PROMISCUOUS; | |
5368c726 | 979 | netdev_info(dev, "Pass all multicast\n"); |
1da177e4 | 980 | } else { |
22bedad3 | 981 | struct netdev_hw_addr *ha; |
1da177e4 LT |
982 | u32 mc_filter[2]; /* Multicast hash filter */ |
983 | ||
984 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
985 | netdev_for_each_mc_addr(ha, dev) |
986 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | |
1da177e4 | 987 | (long *)mc_filter); |
d0e7cb5d FF |
988 | writel(mc_filter[1], &aup->mac->multi_hash_high); |
989 | writel(mc_filter[0], &aup->mac->multi_hash_low); | |
990 | reg &= ~MAC_PROMISCUOUS; | |
991 | reg |= MAC_HASH_MODE; | |
1da177e4 | 992 | } |
d0e7cb5d | 993 | writel(reg, &aup->mac->control); |
1da177e4 LT |
994 | } |
995 | ||
1da177e4 LT |
996 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
997 | { | |
454d7c9b | 998 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 999 | |
2cc3c6b1 FF |
1000 | if (!netif_running(dev)) |
1001 | return -EINVAL; | |
1da177e4 | 1002 | |
2cc3c6b1 FF |
1003 | if (!aup->phy_dev) |
1004 | return -EINVAL; /* PHY not controllable */ | |
1da177e4 | 1005 | |
28b04113 | 1006 | return phy_mii_ioctl(aup->phy_dev, rq, cmd); |
1da177e4 LT |
1007 | } |
1008 | ||
d9a92cee AB |
1009 | static const struct net_device_ops au1000_netdev_ops = { |
1010 | .ndo_open = au1000_open, | |
1011 | .ndo_stop = au1000_close, | |
1012 | .ndo_start_xmit = au1000_tx, | |
1013 | .ndo_set_multicast_list = au1000_multicast_list, | |
1014 | .ndo_do_ioctl = au1000_ioctl, | |
1015 | .ndo_tx_timeout = au1000_tx_timeout, | |
1016 | .ndo_set_mac_address = eth_mac_addr, | |
1017 | .ndo_validate_addr = eth_validate_addr, | |
1018 | .ndo_change_mtu = eth_change_mtu, | |
1019 | }; | |
1020 | ||
bd2302c2 | 1021 | static int __devinit au1000_probe(struct platform_device *pdev) |
5ef3041e | 1022 | { |
2cc3c6b1 | 1023 | static unsigned version_printed; |
5ef3041e | 1024 | struct au1000_private *aup = NULL; |
bd2302c2 | 1025 | struct au1000_eth_platform_data *pd; |
5ef3041e | 1026 | struct net_device *dev = NULL; |
3441592b | 1027 | struct db_dest *pDB, *pDBfree; |
bd2302c2 FF |
1028 | int irq, i, err = 0; |
1029 | struct resource *base, *macen; | |
5ef3041e | 1030 | |
bd2302c2 FF |
1031 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1032 | if (!base) { | |
5368c726 | 1033 | dev_err(&pdev->dev, "failed to retrieve base register\n"); |
bd2302c2 FF |
1034 | err = -ENODEV; |
1035 | goto out; | |
1036 | } | |
5ef3041e | 1037 | |
bd2302c2 FF |
1038 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1039 | if (!macen) { | |
5368c726 | 1040 | dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); |
bd2302c2 FF |
1041 | err = -ENODEV; |
1042 | goto out; | |
1043 | } | |
5ef3041e | 1044 | |
bd2302c2 FF |
1045 | irq = platform_get_irq(pdev, 0); |
1046 | if (irq < 0) { | |
5368c726 | 1047 | dev_err(&pdev->dev, "failed to retrieve IRQ\n"); |
bd2302c2 FF |
1048 | err = -ENODEV; |
1049 | goto out; | |
1050 | } | |
5ef3041e | 1051 | |
18b8e15b FF |
1052 | if (!request_mem_region(base->start, resource_size(base), |
1053 | pdev->name)) { | |
5368c726 | 1054 | dev_err(&pdev->dev, "failed to request memory region for base registers\n"); |
bd2302c2 FF |
1055 | err = -ENXIO; |
1056 | goto out; | |
1057 | } | |
1058 | ||
18b8e15b FF |
1059 | if (!request_mem_region(macen->start, resource_size(macen), |
1060 | pdev->name)) { | |
5368c726 | 1061 | dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); |
bd2302c2 FF |
1062 | err = -ENXIO; |
1063 | goto err_request; | |
1064 | } | |
5ef3041e FF |
1065 | |
1066 | dev = alloc_etherdev(sizeof(struct au1000_private)); | |
1067 | if (!dev) { | |
5368c726 | 1068 | dev_err(&pdev->dev, "alloc_etherdev failed\n"); |
bd2302c2 FF |
1069 | err = -ENOMEM; |
1070 | goto err_alloc; | |
5ef3041e FF |
1071 | } |
1072 | ||
bd2302c2 FF |
1073 | SET_NETDEV_DEV(dev, &pdev->dev); |
1074 | platform_set_drvdata(pdev, dev); | |
5ef3041e FF |
1075 | aup = netdev_priv(dev); |
1076 | ||
1077 | spin_lock_init(&aup->lock); | |
18b8e15b FF |
1078 | aup->msg_enable = (au1000_debug < 4 ? |
1079 | AU1000_DEF_MSG_ENABLE : au1000_debug); | |
5ef3041e | 1080 | |
dc99839c FF |
1081 | /* Allocate the data buffers |
1082 | * Snooping works fine with eth on all au1xxx | |
1083 | */ | |
5ef3041e FF |
1084 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * |
1085 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1086 | &aup->dma_addr, 0); | |
1087 | if (!aup->vaddr) { | |
5368c726 | 1088 | dev_err(&pdev->dev, "failed to allocate data buffers\n"); |
bd2302c2 FF |
1089 | err = -ENOMEM; |
1090 | goto err_vaddr; | |
5ef3041e FF |
1091 | } |
1092 | ||
1093 | /* aup->mac is the base address of the MAC's registers */ | |
d0e7cb5d | 1094 | aup->mac = (struct mac_reg *) |
18b8e15b | 1095 | ioremap_nocache(base->start, resource_size(base)); |
bd2302c2 | 1096 | if (!aup->mac) { |
5368c726 | 1097 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
bd2302c2 FF |
1098 | err = -ENXIO; |
1099 | goto err_remap1; | |
1100 | } | |
5ef3041e | 1101 | |
ec7eabdd | 1102 | /* Setup some variables for quick register address access */ |
d0e7cb5d | 1103 | aup->enable = (u32 *)ioremap_nocache(macen->start, |
18b8e15b | 1104 | resource_size(macen)); |
bd2302c2 | 1105 | if (!aup->enable) { |
5368c726 | 1106 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
bd2302c2 FF |
1107 | err = -ENXIO; |
1108 | goto err_remap2; | |
1109 | } | |
1110 | aup->mac_id = pdev->id; | |
5ef3041e | 1111 | |
f6673653 | 1112 | if (pdev->id == 0) |
eb049630 | 1113 | au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); |
f6673653 | 1114 | else if (pdev->id == 1) |
eb049630 | 1115 | au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); |
5ef3041e | 1116 | |
f6673653 ML |
1117 | /* set a random MAC now in case platform_data doesn't provide one */ |
1118 | random_ether_addr(dev->dev_addr); | |
5ef3041e | 1119 | |
462ca99c | 1120 | writel(0, aup->enable); |
5ef3041e FF |
1121 | aup->mac_enabled = 0; |
1122 | ||
bd2302c2 FF |
1123 | pd = pdev->dev.platform_data; |
1124 | if (!pd) { | |
18b8e15b FF |
1125 | dev_info(&pdev->dev, "no platform_data passed," |
1126 | " PHY search on MAC0\n"); | |
bd2302c2 FF |
1127 | aup->phy1_search_mac0 = 1; |
1128 | } else { | |
f6673653 ML |
1129 | if (is_valid_ether_addr(pd->mac)) |
1130 | memcpy(dev->dev_addr, pd->mac, 6); | |
1131 | ||
bd2302c2 FF |
1132 | aup->phy_static_config = pd->phy_static_config; |
1133 | aup->phy_search_highest_addr = pd->phy_search_highest_addr; | |
1134 | aup->phy1_search_mac0 = pd->phy1_search_mac0; | |
1135 | aup->phy_addr = pd->phy_addr; | |
1136 | aup->phy_busid = pd->phy_busid; | |
1137 | aup->phy_irq = pd->phy_irq; | |
1138 | } | |
1139 | ||
1140 | if (aup->phy_busid && aup->phy_busid > 0) { | |
18b8e15b | 1141 | dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); |
bd2302c2 FF |
1142 | err = -ENODEV; |
1143 | goto err_mdiobus_alloc; | |
1144 | } | |
1145 | ||
5ef3041e | 1146 | aup->mii_bus = mdiobus_alloc(); |
bd2302c2 | 1147 | if (aup->mii_bus == NULL) { |
5368c726 | 1148 | dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); |
bd2302c2 FF |
1149 | err = -ENOMEM; |
1150 | goto err_mdiobus_alloc; | |
1151 | } | |
5ef3041e FF |
1152 | |
1153 | aup->mii_bus->priv = dev; | |
1154 | aup->mii_bus->read = au1000_mdiobus_read; | |
1155 | aup->mii_bus->write = au1000_mdiobus_write; | |
1156 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1157 | aup->mii_bus->name = "au1000_eth_mii"; | |
1158 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id); | |
1159 | aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
dcbfef82 | 1160 | if (aup->mii_bus->irq == NULL) |
1161 | goto err_out; | |
1162 | ||
2cc3c6b1 | 1163 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
5ef3041e | 1164 | aup->mii_bus->irq[i] = PHY_POLL; |
5ef3041e | 1165 | /* if known, set corresponding PHY IRQs */ |
bd2302c2 FF |
1166 | if (aup->phy_static_config) |
1167 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) | |
1168 | aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; | |
1169 | ||
1170 | err = mdiobus_register(aup->mii_bus); | |
1171 | if (err) { | |
5368c726 | 1172 | dev_err(&pdev->dev, "failed to register MDIO bus\n"); |
bd2302c2 FF |
1173 | goto err_mdiobus_reg; |
1174 | } | |
5ef3041e | 1175 | |
eb049630 | 1176 | if (au1000_mii_probe(dev) != 0) |
5ef3041e | 1177 | goto err_out; |
5ef3041e FF |
1178 | |
1179 | pDBfree = NULL; | |
1180 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1181 | pDB = aup->db; | |
1182 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1183 | pDB->pnext = pDBfree; | |
1184 | pDBfree = pDB; | |
1185 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1186 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1187 | pDB++; | |
1188 | } | |
1189 | aup->pDBfree = pDBfree; | |
1190 | ||
1191 | for (i = 0; i < NUM_RX_DMA; i++) { | |
eb049630 | 1192 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1193 | if (!pDB) |
5ef3041e | 1194 | goto err_out; |
ec7eabdd | 1195 | |
5ef3041e FF |
1196 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1197 | aup->rx_db_inuse[i] = pDB; | |
1198 | } | |
1199 | for (i = 0; i < NUM_TX_DMA; i++) { | |
eb049630 | 1200 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1201 | if (!pDB) |
5ef3041e | 1202 | goto err_out; |
ec7eabdd | 1203 | |
5ef3041e FF |
1204 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1205 | aup->tx_dma_ring[i]->len = 0; | |
1206 | aup->tx_db_inuse[i] = pDB; | |
1207 | } | |
1208 | ||
bd2302c2 FF |
1209 | dev->base_addr = base->start; |
1210 | dev->irq = irq; | |
1211 | dev->netdev_ops = &au1000_netdev_ops; | |
1212 | SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); | |
1213 | dev->watchdog_timeo = ETH_TX_TIMEOUT; | |
1214 | ||
5ef3041e FF |
1215 | /* |
1216 | * The boot code uses the ethernet controller, so reset it to start | |
1217 | * fresh. au1000_init() expects that the device is in reset state. | |
1218 | */ | |
eb049630 | 1219 | au1000_reset_mac(dev); |
5ef3041e | 1220 | |
bd2302c2 FF |
1221 | err = register_netdev(dev); |
1222 | if (err) { | |
5368c726 | 1223 | netdev_err(dev, "Cannot register net device, aborting.\n"); |
bd2302c2 FF |
1224 | goto err_out; |
1225 | } | |
1226 | ||
5368c726 FF |
1227 | netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", |
1228 | (unsigned long)base->start, irq); | |
bd2302c2 | 1229 | if (version_printed++ == 0) |
215e17be FF |
1230 | pr_info("%s version %s %s\n", |
1231 | DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
bd2302c2 FF |
1232 | |
1233 | return 0; | |
5ef3041e FF |
1234 | |
1235 | err_out: | |
bd2302c2 | 1236 | if (aup->mii_bus != NULL) |
5ef3041e | 1237 | mdiobus_unregister(aup->mii_bus); |
5ef3041e FF |
1238 | |
1239 | /* here we should have a valid dev plus aup-> register addresses | |
dc99839c FF |
1240 | * so we can reset the mac properly. |
1241 | */ | |
eb049630 | 1242 | au1000_reset_mac(dev); |
5ef3041e FF |
1243 | |
1244 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1245 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1246 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
5ef3041e FF |
1247 | } |
1248 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1249 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1250 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
5ef3041e | 1251 | } |
bd2302c2 FF |
1252 | err_mdiobus_reg: |
1253 | mdiobus_free(aup->mii_bus); | |
1254 | err_mdiobus_alloc: | |
1255 | iounmap(aup->enable); | |
1256 | err_remap2: | |
1257 | iounmap(aup->mac); | |
1258 | err_remap1: | |
5ef3041e FF |
1259 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
1260 | (void *)aup->vaddr, aup->dma_addr); | |
bd2302c2 | 1261 | err_vaddr: |
5ef3041e | 1262 | free_netdev(dev); |
bd2302c2 FF |
1263 | err_alloc: |
1264 | release_mem_region(macen->start, resource_size(macen)); | |
1265 | err_request: | |
1266 | release_mem_region(base->start, resource_size(base)); | |
1267 | out: | |
1268 | return err; | |
5ef3041e FF |
1269 | } |
1270 | ||
bd2302c2 | 1271 | static int __devexit au1000_remove(struct platform_device *pdev) |
5ef3041e | 1272 | { |
bd2302c2 FF |
1273 | struct net_device *dev = platform_get_drvdata(pdev); |
1274 | struct au1000_private *aup = netdev_priv(dev); | |
1275 | int i; | |
1276 | struct resource *base, *macen; | |
5ef3041e | 1277 | |
bd2302c2 FF |
1278 | platform_set_drvdata(pdev, NULL); |
1279 | ||
1280 | unregister_netdev(dev); | |
1281 | mdiobus_unregister(aup->mii_bus); | |
1282 | mdiobus_free(aup->mii_bus); | |
1283 | ||
1284 | for (i = 0; i < NUM_RX_DMA; i++) | |
1285 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1286 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
bd2302c2 FF |
1287 | |
1288 | for (i = 0; i < NUM_TX_DMA; i++) | |
1289 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1290 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
bd2302c2 FF |
1291 | |
1292 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1293 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1294 | (void *)aup->vaddr, aup->dma_addr); | |
1295 | ||
1296 | iounmap(aup->mac); | |
1297 | iounmap(aup->enable); | |
1298 | ||
1299 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1300 | release_mem_region(base->start, resource_size(base)); | |
1301 | ||
1302 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1303 | release_mem_region(macen->start, resource_size(macen)); | |
1304 | ||
1305 | free_netdev(dev); | |
5ef3041e | 1306 | |
5ef3041e FF |
1307 | return 0; |
1308 | } | |
1309 | ||
bd2302c2 FF |
1310 | static struct platform_driver au1000_eth_driver = { |
1311 | .probe = au1000_probe, | |
1312 | .remove = __devexit_p(au1000_remove), | |
1313 | .driver = { | |
1314 | .name = "au1000-eth", | |
1315 | .owner = THIS_MODULE, | |
1316 | }, | |
1317 | }; | |
1318 | MODULE_ALIAS("platform:au1000-eth"); | |
1319 | ||
1320 | ||
1321 | static int __init au1000_init_module(void) | |
1322 | { | |
1323 | return platform_driver_register(&au1000_eth_driver); | |
1324 | } | |
1325 | ||
1326 | static void __exit au1000_exit_module(void) | |
5ef3041e | 1327 | { |
bd2302c2 | 1328 | platform_driver_unregister(&au1000_eth_driver); |
5ef3041e FF |
1329 | } |
1330 | ||
1da177e4 | 1331 | module_init(au1000_init_module); |
bd2302c2 | 1332 | module_exit(au1000_exit_module); |