[linux.git] / drivers / video / cg14.c

/* cg14.c: CGFOURTEEN frame buffer driver
 *
 * Copyright (C) 2003, 2006 David S. Miller ([email protected])
 * Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
 * Copyright (C) 1995 Miguel de Icaza ([email protected])
 *
 * Driver layout based loosely on tgafb.c, see that file for credits.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/uaccess.h>
#include <linux/of_device.h>

#include <asm/io.h>
#include <asm/fbio.h>

#include "sbuslib.h"

/*
 * Local functions.
 */

static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
			 unsigned, struct fb_info *);

static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);

/*
 *  Frame buffer operations
 */

static struct fb_ops cg14_ops = {
	.owner			= THIS_MODULE,
	.fb_setcolreg		= cg14_setcolreg,
	.fb_pan_display		= cg14_pan_display,
	.fb_fillrect		= cfb_fillrect,
	.fb_copyarea		= cfb_copyarea,
	.fb_imageblit		= cfb_imageblit,
	.fb_mmap		= cg14_mmap,
	.fb_ioctl		= cg14_ioctl,
#ifdef CONFIG_COMPAT
	.fb_compat_ioctl	= sbusfb_compat_ioctl,
#endif
};

#define CG14_MCR_INTENABLE_SHIFT	7
#define CG14_MCR_INTENABLE_MASK		0x80
#define CG14_MCR_VIDENABLE_SHIFT	6
#define CG14_MCR_VIDENABLE_MASK		0x40
#define CG14_MCR_PIXMODE_SHIFT		4
#define CG14_MCR_PIXMODE_MASK		0x30
#define CG14_MCR_TMR_SHIFT		2
#define CG14_MCR_TMR_MASK		0x0c
#define CG14_MCR_TMENABLE_SHIFT		1
#define CG14_MCR_TMENABLE_MASK		0x02
#define CG14_MCR_RESET_SHIFT		0
#define CG14_MCR_RESET_MASK		0x01
#define CG14_REV_REVISION_SHIFT		4
#define CG14_REV_REVISION_MASK		0xf0
#define CG14_REV_IMPL_SHIFT		0
#define CG14_REV_IMPL_MASK		0x0f
#define CG14_VBR_FRAMEBASE_SHIFT	12
#define CG14_VBR_FRAMEBASE_MASK		0x00fff000
#define CG14_VMCR1_SETUP_SHIFT		0
#define CG14_VMCR1_SETUP_MASK		0x000001ff
#define CG14_VMCR1_VCONFIG_SHIFT	9
#define CG14_VMCR1_VCONFIG_MASK		0x00000e00
#define CG14_VMCR2_REFRESH_SHIFT	0
#define CG14_VMCR2_REFRESH_MASK		0x00000001
#define CG14_VMCR2_TESTROWCNT_SHIFT	1
#define CG14_VMCR2_TESTROWCNT_MASK	0x00000002
#define CG14_VMCR2_FBCONFIG_SHIFT	2
#define CG14_VMCR2_FBCONFIG_MASK	0x0000000c
#define CG14_VCR_REFRESHREQ_SHIFT	0
#define CG14_VCR_REFRESHREQ_MASK	0x000003ff
#define CG14_VCR1_REFRESHENA_SHIFT	10
#define CG14_VCR1_REFRESHENA_MASK	0x00000400
#define CG14_VCA_CAD_SHIFT		0
#define CG14_VCA_CAD_MASK		0x000003ff
#define CG14_VCA_VERS_SHIFT		10
#define CG14_VCA_VERS_MASK		0x00000c00
#define CG14_VCA_RAMSPEED_SHIFT		12
#define CG14_VCA_RAMSPEED_MASK		0x00001000
#define CG14_VCA_8MB_SHIFT		13
#define CG14_VCA_8MB_MASK		0x00002000

#define CG14_MCR_PIXMODE_8		0
#define CG14_MCR_PIXMODE_16		2
#define CG14_MCR_PIXMODE_32		3

struct cg14_regs{
	u8 mcr;	/* Master Control Reg */
	u8 ppr;	/* Packed Pixel Reg */
	u8 tms[2];	/* Test Mode Status Regs */
	u8 msr;	/* Master Status Reg */
	u8 fsr;	/* Fault Status Reg */
	u8 rev;	/* Revision & Impl */
	u8 ccr;	/* Clock Control Reg */
	u32 tmr;	/* Test Mode Read Back */
	u8 mod;	/* Monitor Operation Data Reg */
	u8 acr;	/* Aux Control */
	u8 xxx0[6];
	u16 hct;	/* Hor Counter */
	u16 vct;	/* Vert Counter */
	u16 hbs;	/* Hor Blank Start */
	u16 hbc;	/* Hor Blank Clear */
	u16 hss;	/* Hor Sync Start */
	u16 hsc;	/* Hor Sync Clear */
	u16 csc;	/* Composite Sync Clear */
	u16 vbs;	/* Vert Blank Start */
	u16 vbc;	/* Vert Blank Clear */
	u16 vss;	/* Vert Sync Start */
	u16 vsc;	/* Vert Sync Clear */
	u16 xcs;
	u16 xcc;
	u16 fsa;	/* Fault Status Address */
	u16 adr;	/* Address Registers */
	u8 xxx1[0xce];
	u8 pcg[0x100]; /* Pixel Clock Generator */
	u32 vbr;	/* Frame Base Row */
	u32 vmcr;	/* VBC Master Control */
	u32 vcr;	/* VBC refresh */
	u32 vca;	/* VBC Config */
};

#define CG14_CCR_ENABLE	0x04
#define CG14_CCR_SELECT 0x02	/* HW/Full screen */

struct cg14_cursor {
	u32 cpl0[32];	/* Enable plane 0 */
	u32 cpl1[32];  /* Color selection plane */
	u8 ccr;	/* Cursor Control Reg */
	u8 xxx0[3];
	u16 cursx;	/* Cursor x,y position */
	u16 cursy;	/* Cursor x,y position */
	u32 color0;
	u32 color1;
	u32 xxx1[0x1bc];
	u32 cpl0i[32];	/* Enable plane 0 autoinc */
	u32 cpl1i[32]; /* Color selection autoinc */
};

struct cg14_dac {
	u8 addr;	/* Address Register */
	u8 xxx0[255];
	u8 glut;	/* Gamma table */
	u8 xxx1[255];
	u8 select;	/* Register Select */
	u8 xxx2[255];
	u8 mode;	/* Mode Register */
};

struct cg14_xlut{
	u8 x_xlut [256];
	u8 x_xlutd [256];
	u8 xxx0[0x600];
	u8 x_xlut_inc [256];
	u8 x_xlutd_inc [256];
};

/* Color look up table (clut) */
/* Each one of these arrays hold the color lookup table (for 256
 * colors) for each MDI page (I assume then there should be 4 MDI
 * pages, I still wonder what they are.  I have seen NeXTStep split
 * the screen in four parts, while operating in 24 bits mode.  Each
 * integer holds 4 values: alpha value (transparency channel, thanks
 * go to John Stone ([email protected]) from OpenBSD), red, green and blue
 *
 * I currently use the clut instead of the Xlut
 */
struct cg14_clut {
	u32 c_clut [256];
	u32 c_clutd [256];    /* i wonder what the 'd' is for */
	u32 c_clut_inc [256];
	u32 c_clutd_inc [256];
};

#define CG14_MMAP_ENTRIES	16

struct cg14_par {
	spinlock_t		lock;
	struct cg14_regs	__iomem *regs;
	struct cg14_clut	__iomem *clut;
	struct cg14_cursor	__iomem *cursor;

	u32			flags;
#define CG14_FLAG_BLANKED	0x00000001

	unsigned long		iospace;

	struct sbus_mmap_map	mmap_map[CG14_MMAP_ENTRIES];

	int			mode;
	int			ramsize;
};

static void __cg14_reset(struct cg14_par *par)
{
	struct cg14_regs __iomem *regs = par->regs;
	u8 val;

	val = sbus_readb(&regs->mcr);
	val &= ~(CG14_MCR_PIXMODE_MASK);
	sbus_writeb(val, &regs->mcr);
}

static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
	struct cg14_par *par = (struct cg14_par *) info->par;
	unsigned long flags;

	/* We just use this to catch switches out of
	 * graphics mode.
	 */
	spin_lock_irqsave(&par->lock, flags);
	__cg14_reset(par);
	spin_unlock_irqrestore(&par->lock, flags);

	if (var->xoffset || var->yoffset || var->vmode)
		return -EINVAL;
	return 0;
}

/**
 *      cg14_setcolreg - Optional function. Sets a color register.
 *      @regno: boolean, 0 copy local, 1 get_user() function
 *      @red: frame buffer colormap structure
 *      @green: The green value which can be up to 16 bits wide
 *      @blue:  The blue value which can be up to 16 bits wide.
 *      @transp: If supported the alpha value which can be up to 16 bits wide.
 *      @info: frame buffer info structure
 */
static int cg14_setcolreg(unsigned regno,
			  unsigned red, unsigned green, unsigned blue,
			  unsigned transp, struct fb_info *info)
{
	struct cg14_par *par = (struct cg14_par *) info->par;
	struct cg14_clut __iomem *clut = par->clut;
	unsigned long flags;
	u32 val;

	if (regno >= 256)
		return 1;

	red >>= 8;
	green >>= 8;
	blue >>= 8;
	val = (red | (green << 8) | (blue << 16));

	spin_lock_irqsave(&par->lock, flags);
	sbus_writel(val, &clut->c_clut[regno]);
	spin_unlock_irqrestore(&par->lock, flags);

	return 0;
}

static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
	struct cg14_par *par = (struct cg14_par *) info->par;

	return sbusfb_mmap_helper(par->mmap_map,
				  info->fix.smem_start, info->fix.smem_len,
				  par->iospace, vma);
}

static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
	struct cg14_par *par = (struct cg14_par *) info->par;
	struct cg14_regs __iomem *regs = par->regs;
	struct mdi_cfginfo kmdi, __user *mdii;
	unsigned long flags;
	int cur_mode, mode, ret = 0;

	switch (cmd) {
	case MDI_RESET:
		spin_lock_irqsave(&par->lock, flags);
		__cg14_reset(par);
		spin_unlock_irqrestore(&par->lock, flags);
		break;

	case MDI_GET_CFGINFO:
		memset(&kmdi, 0, sizeof(kmdi));

		spin_lock_irqsave(&par->lock, flags);
		kmdi.mdi_type = FBTYPE_MDICOLOR;
		kmdi.mdi_height = info->var.yres;
		kmdi.mdi_width = info->var.xres;
		kmdi.mdi_mode = par->mode;
		kmdi.mdi_pixfreq = 72; /* FIXME */
		kmdi.mdi_size = par->ramsize;
		spin_unlock_irqrestore(&par->lock, flags);

		mdii = (struct mdi_cfginfo __user *) arg;
		if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
			ret = -EFAULT;
		break;

	case MDI_SET_PIXELMODE:
		if (get_user(mode, (int __user *) arg)) {
			ret = -EFAULT;
			break;
		}

		spin_lock_irqsave(&par->lock, flags);
		cur_mode = sbus_readb(&regs->mcr);
		cur_mode &= ~CG14_MCR_PIXMODE_MASK;
		switch(mode) {
		case MDI_32_PIX:
			cur_mode |= (CG14_MCR_PIXMODE_32 <<
				     CG14_MCR_PIXMODE_SHIFT);
			break;

		case MDI_16_PIX:
			cur_mode |= (CG14_MCR_PIXMODE_16 <<
				     CG14_MCR_PIXMODE_SHIFT);
			break;

		case MDI_8_PIX:
			break;

		default:
			ret = -ENOSYS;
			break;
		};
		if (!ret) {
			sbus_writeb(cur_mode, &regs->mcr);
			par->mode = mode;
		}
		spin_unlock_irqrestore(&par->lock, flags);
		break;

	default:
		ret = sbusfb_ioctl_helper(cmd, arg, info,
					  FBTYPE_MDICOLOR, 8,
					  info->fix.smem_len);
		break;
	};

	return ret;
}

/*
 *  Initialisation
 */

static void cg14_init_fix(struct fb_info *info, int linebytes,
			  struct device_node *dp)
{
	const char *name = dp->name;

	strlcpy(info->fix.id, name, sizeof(info->fix.id));

	info->fix.type = FB_TYPE_PACKED_PIXELS;
	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

	info->fix.line_length = linebytes;

	info->fix.accel = FB_ACCEL_SUN_CG14;
}

static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
	{
		.voff	= CG14_REGS,
		.poff	= 0x80000000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_XLUT,
		.poff	= 0x80003000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_CLUT1,
		.poff	= 0x80004000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_CLUT2,
		.poff	= 0x80005000,
		.size	= 0x1000
	},
	{
		.voff	= CG14_CLUT3,
		.poff	= 0x80006000,
		.size	= 0x1000
	},
	{
		.voff	= CG3_MMAP_OFFSET - 0x7000,
		.poff	= 0x80000000,
		.size	= 0x7000
	},
	{
		.voff	= CG3_MMAP_OFFSET,
		.poff	= 0x00000000,
		.size	= SBUS_MMAP_FBSIZE(1)
	},
	{
		.voff	= MDI_CURSOR_MAP,
		.poff	= 0x80001000,
		.size	= 0x1000
	},
	{
		.voff	= MDI_CHUNKY_BGR_MAP,
		.poff	= 0x01000000,
		.size	= 0x400000
	},
	{
		.voff	= MDI_PLANAR_X16_MAP,
		.poff	= 0x02000000,
		.size	= 0x200000
	},
	{
		.voff	= MDI_PLANAR_C16_MAP,
		.poff	= 0x02800000,
		.size	= 0x200000
	},
	{
		.voff	= MDI_PLANAR_X32_MAP,
		.poff	= 0x03000000,
		.size	= 0x100000
	},
	{
		.voff	= MDI_PLANAR_B32_MAP,
		.poff	= 0x03400000,
		.size	= 0x100000
	},
	{
		.voff	= MDI_PLANAR_G32_MAP,
		.poff	= 0x03800000,
		.size	= 0x100000
	},
	{
		.voff	= MDI_PLANAR_R32_MAP,
		.poff	= 0x03c00000,
		.size	= 0x100000
	},
	{ .size = 0 }
};

static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info,
			    struct cg14_par *par)
{
	if (par->regs)
		of_iounmap(&op->resource[0],
			   par->regs, sizeof(struct cg14_regs));
	if (par->clut)
		of_iounmap(&op->resource[0],
			   par->clut, sizeof(struct cg14_clut));
	if (par->cursor)
		of_iounmap(&op->resource[0],
			   par->cursor, sizeof(struct cg14_cursor));
	if (info->screen_base)
		of_iounmap(&op->resource[1],
			   info->screen_base, info->fix.smem_len);
}

static int cg14_probe(struct platform_device *op)
{
	struct device_node *dp = op->dev.of_node;
	struct fb_info *info;
	struct cg14_par *par;
	int is_8mb, linebytes, i, err;

	info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);

	err = -ENOMEM;
	if (!info)
		goto out_err;
	par = info->par;

	spin_lock_init(&par->lock);

	sbusfb_fill_var(&info->var, dp, 8);
	info->var.red.length = 8;
	info->var.green.length = 8;
	info->var.blue.length = 8;

	linebytes = of_getintprop_default(dp, "linebytes",
					  info->var.xres);
	info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);

	if (!strcmp(dp->parent->name, "sbus") ||
	    !strcmp(dp->parent->name, "sbi")) {
		info->fix.smem_start = op->resource[0].start;
		par->iospace = op->resource[0].flags & IORESOURCE_BITS;
	} else {
		info->fix.smem_start = op->resource[1].start;
		par->iospace = op->resource[0].flags & IORESOURCE_BITS;
	}

	par->regs = of_ioremap(&op->resource[0], 0,
			       sizeof(struct cg14_regs), "cg14 regs");
	par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
			       sizeof(struct cg14_clut), "cg14 clut");
	par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
				 sizeof(struct cg14_cursor), "cg14 cursor");

	info->screen_base = of_ioremap(&op->resource[1], 0,
				       info->fix.smem_len, "cg14 ram");

	if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
		goto out_unmap_regs;

	is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
		  (8 * 1024 * 1024));

	BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
		
	memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));

	for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
		struct sbus_mmap_map *map = &par->mmap_map[i];

		if (!map->size)
			break;
		if (map->poff & 0x80000000)
			map->poff = (map->poff & 0x7fffffff) +
				(op->resource[0].start -
				 op->resource[1].start);
		if (is_8mb &&
		    map->size >= 0x100000 &&
		    map->size <= 0x400000)
			map->size *= 2;
	}

	par->mode = MDI_8_PIX;
	par->ramsize = (is_8mb ? 0x800000 : 0x400000);

	info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
	info->fbops = &cg14_ops;

	__cg14_reset(par);

	if (fb_alloc_cmap(&info->cmap, 256, 0))
		goto out_unmap_regs;

	fb_set_cmap(&info->cmap, info);

	cg14_init_fix(info, linebytes, dp);

	err = register_framebuffer(info);
	if (err < 0)
		goto out_dealloc_cmap;

	dev_set_drvdata(&op->dev, info);

	printk(KERN_INFO "%s: cgfourteen at %lx:%lx, %dMB\n",
	       dp->full_name,
	       par->iospace, info->fix.smem_start,
	       par->ramsize >> 20);

	return 0;

out_dealloc_cmap:
	fb_dealloc_cmap(&info->cmap);

out_unmap_regs:
	cg14_unmap_regs(op, info, par);
	framebuffer_release(info);

out_err:
	return err;
}

static int cg14_remove(struct platform_device *op)
{
	struct fb_info *info = dev_get_drvdata(&op->dev);
	struct cg14_par *par = info->par;

	unregister_framebuffer(info);
	fb_dealloc_cmap(&info->cmap);

	cg14_unmap_regs(op, info, par);

	framebuffer_release(info);

	dev_set_drvdata(&op->dev, NULL);

	return 0;
}

static const struct of_device_id cg14_match[] = {
	{
		.name = "cgfourteen",
	},
	{},
};
MODULE_DEVICE_TABLE(of, cg14_match);

static struct platform_driver cg14_driver = {
	.driver = {
		.name = "cg14",
		.owner = THIS_MODULE,
		.of_match_table = cg14_match,
	},
	.probe		= cg14_probe,
	.remove		= cg14_remove,
};

static int __init cg14_init(void)
{
	if (fb_get_options("cg14fb", NULL))
		return -ENODEV;

	return platform_driver_register(&cg14_driver);
}

static void __exit cg14_exit(void)
{
	platform_driver_unregister(&cg14_driver);
}

module_init(cg14_init);
module_exit(cg14_exit);

MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/* cg14.c: CGFOURTEEN frame buffer driver
1da177e4 LT	2	*
50312ce9	3	* Copyright (C) 2003, 2006 David S. Miller ([email protected])
1da177e4 LT	4	* Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
	5	* Copyright (C) 1995 Miguel de Icaza ([email protected])
	6	*
	7	* Driver layout based loosely on tgafb.c, see that file for credits.
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/errno.h>
	13	#include <linux/string.h>
1da177e4 LT	14	#include <linux/delay.h>
	15	#include <linux/init.h>
	16	#include <linux/fb.h>
	17	#include <linux/mm.h>
631a9dca	18	#include <linux/uaccess.h>
6cd5a86b	19	#include <linux/of_device.h>
1da177e4 LT	20
1da177e4 LT	21	#include <asm/io.h>
1da177e4 LT	22	#include <asm/fbio.h>
	23
	24	#include "sbuslib.h"
	25
	26	/*
	27	* Local functions.
	28	*/
	29
	30	static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
	31	unsigned, struct fb_info *);
	32
216d526c	33	static int cg14_mmap(struct fb_info , struct vm_area_struct );
67a6680d	34	static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
1da177e4 LT	35	static int cg14_pan_display(struct fb_var_screeninfo , struct fb_info );
	36
	37	/*
	38	* Frame buffer operations
	39	*/
	40
	41	static struct fb_ops cg14_ops = {
	42	.owner = THIS_MODULE,
	43	.fb_setcolreg = cg14_setcolreg,
	44	.fb_pan_display = cg14_pan_display,
	45	.fb_fillrect = cfb_fillrect,
	46	.fb_copyarea = cfb_copyarea,
	47	.fb_imageblit = cfb_imageblit,
	48	.fb_mmap = cg14_mmap,
	49	.fb_ioctl = cg14_ioctl,
9ffb83bc CH	50	#ifdef CONFIG_COMPAT
	51	.fb_compat_ioctl = sbusfb_compat_ioctl,
	52	#endif
1da177e4 LT	53	};
	54
	55	#define CG14_MCR_INTENABLE_SHIFT 7
	56	#define CG14_MCR_INTENABLE_MASK 0x80
	57	#define CG14_MCR_VIDENABLE_SHIFT 6
	58	#define CG14_MCR_VIDENABLE_MASK 0x40
	59	#define CG14_MCR_PIXMODE_SHIFT 4
	60	#define CG14_MCR_PIXMODE_MASK 0x30
	61	#define CG14_MCR_TMR_SHIFT 2
	62	#define CG14_MCR_TMR_MASK 0x0c
	63	#define CG14_MCR_TMENABLE_SHIFT 1
	64	#define CG14_MCR_TMENABLE_MASK 0x02
	65	#define CG14_MCR_RESET_SHIFT 0
	66	#define CG14_MCR_RESET_MASK 0x01
	67	#define CG14_REV_REVISION_SHIFT 4
	68	#define CG14_REV_REVISION_MASK 0xf0
	69	#define CG14_REV_IMPL_SHIFT 0
	70	#define CG14_REV_IMPL_MASK 0x0f
	71	#define CG14_VBR_FRAMEBASE_SHIFT 12
	72	#define CG14_VBR_FRAMEBASE_MASK 0x00fff000
	73	#define CG14_VMCR1_SETUP_SHIFT 0
	74	#define CG14_VMCR1_SETUP_MASK 0x000001ff
	75	#define CG14_VMCR1_VCONFIG_SHIFT 9
	76	#define CG14_VMCR1_VCONFIG_MASK 0x00000e00
	77	#define CG14_VMCR2_REFRESH_SHIFT 0
	78	#define CG14_VMCR2_REFRESH_MASK 0x00000001
	79	#define CG14_VMCR2_TESTROWCNT_SHIFT 1
	80	#define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
	81	#define CG14_VMCR2_FBCONFIG_SHIFT 2
	82	#define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
	83	#define CG14_VCR_REFRESHREQ_SHIFT 0
	84	#define CG14_VCR_REFRESHREQ_MASK 0x000003ff
	85	#define CG14_VCR1_REFRESHENA_SHIFT 10
	86	#define CG14_VCR1_REFRESHENA_MASK 0x00000400
	87	#define CG14_VCA_CAD_SHIFT 0
	88	#define CG14_VCA_CAD_MASK 0x000003ff
	89	#define CG14_VCA_VERS_SHIFT 10
	90	#define CG14_VCA_VERS_MASK 0x00000c00
	91	#define CG14_VCA_RAMSPEED_SHIFT 12
	92	#define CG14_VCA_RAMSPEED_MASK 0x00001000
	93	#define CG14_VCA_8MB_SHIFT 13
	94	#define CG14_VCA_8MB_MASK 0x00002000
	95
	96	#define CG14_MCR_PIXMODE_8 0
	97	#define CG14_MCR_PIXMODE_16 2
	98	#define CG14_MCR_PIXMODE_32 3
	99
	100	struct cg14_regs{
50312ce9 DM	101	u8 mcr; /* Master Control Reg */
	102	u8 ppr; /* Packed Pixel Reg */
	103	u8 tms[2]; /* Test Mode Status Regs */
	104	u8 msr; /* Master Status Reg */
	105	u8 fsr; /* Fault Status Reg */
	106	u8 rev; /* Revision & Impl */
	107	u8 ccr; /* Clock Control Reg */
	108	u32 tmr; /* Test Mode Read Back */
	109	u8 mod; /* Monitor Operation Data Reg */
	110	u8 acr; /* Aux Control */
1da177e4	111	u8 xxx0[6];
50312ce9 DM	112	u16 hct; /* Hor Counter */
	113	u16 vct; /* Vert Counter */
	114	u16 hbs; /* Hor Blank Start */
	115	u16 hbc; /* Hor Blank Clear */
	116	u16 hss; /* Hor Sync Start */
	117	u16 hsc; /* Hor Sync Clear */
	118	u16 csc; /* Composite Sync Clear */
	119	u16 vbs; /* Vert Blank Start */
	120	u16 vbc; /* Vert Blank Clear */
	121	u16 vss; /* Vert Sync Start */
	122	u16 vsc; /* Vert Sync Clear */
	123	u16 xcs;
	124	u16 xcc;
	125	u16 fsa; /* Fault Status Address */
	126	u16 adr; /* Address Registers */
1da177e4	127	u8 xxx1[0xce];
50312ce9 DM	128	u8 pcg[0x100]; /* Pixel Clock Generator */
	129	u32 vbr; /* Frame Base Row */
	130	u32 vmcr; /* VBC Master Control */
	131	u32 vcr; /* VBC refresh */
	132	u32 vca; /* VBC Config */
1da177e4 LT	133	};
	134
	135	#define CG14_CCR_ENABLE 0x04
	136	#define CG14_CCR_SELECT 0x02 /* HW/Full screen */
	137
	138	struct cg14_cursor {
50312ce9 DM	139	u32 cpl0[32]; /* Enable plane 0 */
	140	u32 cpl1[32]; /* Color selection plane */
	141	u8 ccr; /* Cursor Control Reg */
1da177e4	142	u8 xxx0[3];
50312ce9 DM	143	u16 cursx; /* Cursor x,y position */
	144	u16 cursy; /* Cursor x,y position */
	145	u32 color0;
	146	u32 color1;
1da177e4	147	u32 xxx1[0x1bc];
50312ce9 DM	148	u32 cpl0i[32]; /* Enable plane 0 autoinc */
50312ce9 DM	149	u32 cpl1i[32]; /* Color selection autoinc */
1da177e4 LT	150	};
	151
	152	struct cg14_dac {
50312ce9	153	u8 addr; /* Address Register */
1da177e4	154	u8 xxx0[255];
50312ce9	155	u8 glut; /* Gamma table */
1da177e4	156	u8 xxx1[255];
50312ce9	157	u8 select; /* Register Select */
1da177e4	158	u8 xxx2[255];
50312ce9	159	u8 mode; /* Mode Register */
1da177e4 LT	160	};
	161
	162	struct cg14_xlut{
50312ce9 DM	163	u8 x_xlut [256];
50312ce9 DM	164	u8 x_xlutd [256];
1da177e4	165	u8 xxx0[0x600];
50312ce9 DM	166	u8 x_xlut_inc [256];
50312ce9 DM	167	u8 x_xlutd_inc [256];
1da177e4 LT	168	};
	169
	170	/* Color look up table (clut) */
	171	/* Each one of these arrays hold the color lookup table (for 256
	172	* colors) for each MDI page (I assume then there should be 4 MDI
	173	* pages, I still wonder what they are. I have seen NeXTStep split
	174	* the screen in four parts, while operating in 24 bits mode. Each
	175	* integer holds 4 values: alpha value (transparency channel, thanks
	176	* go to John Stone ([email protected]) from OpenBSD), red, green and blue
	177	*
	178	* I currently use the clut instead of the Xlut
	179	*/
	180	struct cg14_clut {
	181	u32 c_clut [256];
	182	u32 c_clutd [256]; /* i wonder what the 'd' is for */
	183	u32 c_clut_inc [256];
	184	u32 c_clutd_inc [256];
	185	};
	186
	187	#define CG14_MMAP_ENTRIES 16
	188
	189	struct cg14_par {
	190	spinlock_t lock;
	191	struct cg14_regs __iomem *regs;
	192	struct cg14_clut __iomem *clut;
	193	struct cg14_cursor __iomem *cursor;
	194
	195	u32 flags;
	196	#define CG14_FLAG_BLANKED 0x00000001
	197
1da177e4	198	unsigned long iospace;
1da177e4 LT	199
	200	struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
	201
	202	int mode;
	203	int ramsize;
1da177e4 LT	204	};
	205
	206	static void __cg14_reset(struct cg14_par *par)
	207	{
	208	struct cg14_regs __iomem *regs = par->regs;
	209	u8 val;
	210
	211	val = sbus_readb(&regs->mcr);
	212	val &= ~(CG14_MCR_PIXMODE_MASK);
	213	sbus_writeb(val, &regs->mcr);
	214	}
	215
	216	static int cg14_pan_display(struct fb_var_screeninfo var, struct fb_info info)
	217	{
	218	struct cg14_par par = (struct cg14_par ) info->par;
	219	unsigned long flags;
	220
	221	/* We just use this to catch switches out of
	222	* graphics mode.
	223	*/
	224	spin_lock_irqsave(&par->lock, flags);
	225	__cg14_reset(par);
	226	spin_unlock_irqrestore(&par->lock, flags);
	227
	228	if (var->xoffset \|\| var->yoffset \|\| var->vmode)
	229	return -EINVAL;
	230	return 0;
	231	}
	232
	233	/**
	234	* cg14_setcolreg - Optional function. Sets a color register.
	235	* @regno: boolean, 0 copy local, 1 get_user() function
	236	* @red: frame buffer colormap structure
	237	* @green: The green value which can be up to 16 bits wide
	238	* @blue: The blue value which can be up to 16 bits wide.
	239	* @transp: If supported the alpha value which can be up to 16 bits wide.
	240	* @info: frame buffer info structure
	241	*/
	242	static int cg14_setcolreg(unsigned regno,
	243	unsigned red, unsigned green, unsigned blue,
	244	unsigned transp, struct fb_info *info)
	245	{
	246	struct cg14_par par = (struct cg14_par ) info->par;
	247	struct cg14_clut __iomem *clut = par->clut;
	248	unsigned long flags;
	249	u32 val;
	250
	251	if (regno >= 256)
	252	return 1;
	253
	254	red >>= 8;
	255	green >>= 8;
	256	blue >>= 8;
	257	val = (red \| (green << 8) \| (blue << 16));
	258
	259	spin_lock_irqsave(&par->lock, flags);
	260	sbus_writel(val, &clut->c_clut[regno]);
	261	spin_unlock_irqrestore(&par->lock, flags);
	262
	263	return 0;
	264	}
	265
216d526c	266	static int cg14_mmap(struct fb_info info, struct vm_area_struct vma)
1da177e4 LT	267	{
	268	struct cg14_par par = (struct cg14_par ) info->par;
	269
	270	return sbusfb_mmap_helper(par->mmap_map,
de4dc48e	271	info->fix.smem_start, info->fix.smem_len,
1da177e4 LT	272	par->iospace, vma);
	273	}
	274
67a6680d	275	static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
1da177e4 LT	276	{
	277	struct cg14_par par = (struct cg14_par ) info->par;
	278	struct cg14_regs __iomem *regs = par->regs;
	279	struct mdi_cfginfo kmdi, __user *mdii;
	280	unsigned long flags;
	281	int cur_mode, mode, ret = 0;
	282
	283	switch (cmd) {
	284	case MDI_RESET:
	285	spin_lock_irqsave(&par->lock, flags);
	286	__cg14_reset(par);
	287	spin_unlock_irqrestore(&par->lock, flags);
	288	break;
	289
	290	case MDI_GET_CFGINFO:
	291	memset(&kmdi, 0, sizeof(kmdi));
	292
	293	spin_lock_irqsave(&par->lock, flags);
	294	kmdi.mdi_type = FBTYPE_MDICOLOR;
	295	kmdi.mdi_height = info->var.yres;
	296	kmdi.mdi_width = info->var.xres;
	297	kmdi.mdi_mode = par->mode;
	298	kmdi.mdi_pixfreq = 72; /* FIXME */
	299	kmdi.mdi_size = par->ramsize;
	300	spin_unlock_irqrestore(&par->lock, flags);
	301
	302	mdii = (struct mdi_cfginfo __user *) arg;
	303	if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
	304	ret = -EFAULT;
	305	break;
	306
	307	case MDI_SET_PIXELMODE:
	308	if (get_user(mode, (int __user *) arg)) {
	309	ret = -EFAULT;
	310	break;
	311	}
	312
	313	spin_lock_irqsave(&par->lock, flags);
	314	cur_mode = sbus_readb(&regs->mcr);
	315	cur_mode &= ~CG14_MCR_PIXMODE_MASK;
	316	switch(mode) {
	317	case MDI_32_PIX:
	318	cur_mode \|= (CG14_MCR_PIXMODE_32 <<
	319	CG14_MCR_PIXMODE_SHIFT);
	320	break;
	321
	322	case MDI_16_PIX:
	323	cur_mode \|= (CG14_MCR_PIXMODE_16 <<
	324	CG14_MCR_PIXMODE_SHIFT);
	325	break;
	326
	327	case MDI_8_PIX:
	328	break;
	329
	330	default:
	331	ret = -ENOSYS;
	332	break;
	333	};
	334	if (!ret) {
	335	sbus_writeb(cur_mode, &regs->mcr);
	336	par->mode = mode;
	337	}
	338	spin_unlock_irqrestore(&par->lock, flags);
	339	break;
340
341	default:
342	ret = sbusfb_ioctl_helper(cmd, arg, info,
de4dc48e KH	343	FBTYPE_MDICOLOR, 8,
de4dc48e KH	344	info->fix.smem_len);
1da177e4 LT	345	break;
	346	};
	347
	348	return ret;
	349	}
	350
	351	/*
	352	* Initialisation
	353	*/
	354
48c68c4f GKH	355	static void cg14_init_fix(struct fb_info *info, int linebytes,
48c68c4f GKH	356	struct device_node *dp)
1da177e4	357	{
50312ce9	358	const char *name = dp->name;
1da177e4 LT	359
	360	strlcpy(info->fix.id, name, sizeof(info->fix.id));
	361
	362	info->fix.type = FB_TYPE_PACKED_PIXELS;
	363	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
	364
	365	info->fix.line_length = linebytes;
	366
	367	info->fix.accel = FB_ACCEL_SUN_CG14;
	368	}
	369
48c68c4f	370	static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
1da177e4 LT	371	{
	372	.voff = CG14_REGS,
	373	.poff = 0x80000000,
	374	.size = 0x1000
	375	},
	376	{
	377	.voff = CG14_XLUT,
	378	.poff = 0x80003000,
	379	.size = 0x1000
	380	},
	381	{
	382	.voff = CG14_CLUT1,
	383	.poff = 0x80004000,
	384	.size = 0x1000
	385	},
	386	{
	387	.voff = CG14_CLUT2,
	388	.poff = 0x80005000,
	389	.size = 0x1000
	390	},
	391	{
	392	.voff = CG14_CLUT3,
	393	.poff = 0x80006000,
	394	.size = 0x1000
	395	},
	396	{
	397	.voff = CG3_MMAP_OFFSET - 0x7000,
	398	.poff = 0x80000000,
	399	.size = 0x7000
	400	},
	401	{
	402	.voff = CG3_MMAP_OFFSET,
	403	.poff = 0x00000000,
	404	.size = SBUS_MMAP_FBSIZE(1)
	405	},
	406	{
	407	.voff = MDI_CURSOR_MAP,
	408	.poff = 0x80001000,
	409	.size = 0x1000
	410	},
	411	{
	412	.voff = MDI_CHUNKY_BGR_MAP,
	413	.poff = 0x01000000,
	414	.size = 0x400000
	415	},
	416	{
	417	.voff = MDI_PLANAR_X16_MAP,
	418	.poff = 0x02000000,
	419	.size = 0x200000
	420	},
	421	{
	422	.voff = MDI_PLANAR_C16_MAP,
	423	.poff = 0x02800000,
	424	.size = 0x200000
	425	},
	426	{
	427	.voff = MDI_PLANAR_X32_MAP,
	428	.poff = 0x03000000,
	429	.size = 0x100000
	430	},
	431	{
	432	.voff = MDI_PLANAR_B32_MAP,
	433	.poff = 0x03400000,
	434	.size = 0x100000
435	},
436	{
437	.voff = MDI_PLANAR_G32_MAP,
438	.poff = 0x03800000,
439	.size = 0x100000
440	},
441	{
442	.voff = MDI_PLANAR_R32_MAP,
443	.poff = 0x03c00000,
444	.size = 0x100000
445	},
446	{ .size = 0 }
447	};
448
2dc11581	449	static void cg14_unmap_regs(struct platform_device op, struct fb_info info,
c7f439b9	450	struct cg14_par *par)
1da177e4	451	{
c7f439b9	452	if (par->regs)
e3a411a3	453	of_iounmap(&op->resource[0],
c7f439b9 DM	454	par->regs, sizeof(struct cg14_regs));
c7f439b9 DM	455	if (par->clut)
e3a411a3	456	of_iounmap(&op->resource[0],
c7f439b9 DM	457	par->clut, sizeof(struct cg14_clut));
c7f439b9 DM	458	if (par->cursor)
e3a411a3	459	of_iounmap(&op->resource[0],
c7f439b9 DM	460	par->cursor, sizeof(struct cg14_cursor));
c7f439b9 DM	461	if (info->screen_base)
e3a411a3	462	of_iounmap(&op->resource[1],
de4dc48e	463	info->screen_base, info->fix.smem_len);
50312ce9	464	}
1da177e4	465
48c68c4f	466	static int cg14_probe(struct platform_device *op)
50312ce9	467	{
d4b8b2c2	468	struct device_node *dp = op->dev.of_node;
c7f439b9 DM	469	struct fb_info *info;
c7f439b9 DM	470	struct cg14_par *par;
50312ce9	471	int is_8mb, linebytes, i, err;
1da177e4	472
c7f439b9 DM	473	info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
	474
	475	err = -ENOMEM;
	476	if (!info)
	477	goto out_err;
	478	par = info->par;
1da177e4	479
c7f439b9	480	spin_lock_init(&par->lock);
1da177e4	481
6cd5a86b	482	sbusfb_fill_var(&info->var, dp, 8);
c7f439b9 DM	483	info->var.red.length = 8;
	484	info->var.green.length = 8;
	485	info->var.blue.length = 8;
1da177e4	486
50312ce9	487	linebytes = of_getintprop_default(dp, "linebytes",
c7f439b9	488	info->var.xres);
de4dc48e	489	info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
1da177e4	490
50312ce9 DM	491	if (!strcmp(dp->parent->name, "sbus") \|\|
50312ce9 DM	492	!strcmp(dp->parent->name, "sbi")) {
de4dc48e	493	info->fix.smem_start = op->resource[0].start;
c7f439b9	494	par->iospace = op->resource[0].flags & IORESOURCE_BITS;
1da177e4	495	} else {
de4dc48e	496	info->fix.smem_start = op->resource[1].start;
c7f439b9	497	par->iospace = op->resource[0].flags & IORESOURCE_BITS;
1da177e4 LT	498	}
1da177e4 LT	499
c7f439b9 DM	500	par->regs = of_ioremap(&op->resource[0], 0,
	501	sizeof(struct cg14_regs), "cg14 regs");
	502	par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
	503	sizeof(struct cg14_clut), "cg14 clut");
	504	par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
	505	sizeof(struct cg14_cursor), "cg14 cursor");
1da177e4	506
c7f439b9	507	info->screen_base = of_ioremap(&op->resource[1], 0,
de4dc48e	508	info->fix.smem_len, "cg14 ram");
1da177e4	509
c7f439b9 DM	510	if (!par->regs \|\| !par->clut \|\| !par->cursor \|\| !info->screen_base)
c7f439b9 DM	511	goto out_unmap_regs;
50312ce9 DM	512
	513	is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
	514	(8 * 1024 * 1024));
	515
c7f439b9	516	BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
1da177e4	517
c7f439b9	518	memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
50312ce9	519
1da177e4	520	for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
c7f439b9	521	struct sbus_mmap_map *map = &par->mmap_map[i];
1da177e4 LT	522
	523	if (!map->size)
	524	break;
	525	if (map->poff & 0x80000000)
50312ce9 DM	526	map->poff = (map->poff & 0x7fffffff) +
	527	(op->resource[0].start -
	528	op->resource[1].start);
1da177e4 LT	529	if (is_8mb &&
	530	map->size >= 0x100000 &&
	531	map->size <= 0x400000)
	532	map->size *= 2;
	533	}
	534
c7f439b9 DM	535	par->mode = MDI_8_PIX;
c7f439b9 DM	536	par->ramsize = (is_8mb ? 0x800000 : 0x400000);
1da177e4	537
c7f439b9 DM	538	info->flags = FBINFO_DEFAULT \| FBINFO_HWACCEL_YPAN;
c7f439b9 DM	539	info->fbops = &cg14_ops;
1da177e4	540
c7f439b9	541	__cg14_reset(par);
1da177e4	542
c7f439b9 DM	543	if (fb_alloc_cmap(&info->cmap, 256, 0))
c7f439b9 DM	544	goto out_unmap_regs;
1da177e4	545
c7f439b9	546	fb_set_cmap(&info->cmap, info);
1da177e4	547
c7f439b9 DM	548	cg14_init_fix(info, linebytes, dp);
	549
	550	err = register_framebuffer(info);
	551	if (err < 0)
	552	goto out_dealloc_cmap;
1da177e4	553
c7f439b9	554	dev_set_drvdata(&op->dev, info);
1da177e4	555
194f1a68	556	printk(KERN_INFO "%s: cgfourteen at %lx:%lx, %dMB\n",
50312ce9	557	dp->full_name,
de4dc48e	558	par->iospace, info->fix.smem_start,
c7f439b9	559	par->ramsize >> 20);
1da177e4	560
50312ce9	561	return 0;
1da177e4	562
c7f439b9 DM	563	out_dealloc_cmap:
	564	fb_dealloc_cmap(&info->cmap);
	565
	566	out_unmap_regs:
	567	cg14_unmap_regs(op, info, par);
6359691d	568	framebuffer_release(info);
1da177e4	569
c7f439b9 DM	570	out_err:
c7f439b9 DM	571	return err;
50312ce9	572	}
1da177e4	573
48c68c4f	574	static int cg14_remove(struct platform_device *op)
50312ce9	575	{
c7f439b9 DM	576	struct fb_info *info = dev_get_drvdata(&op->dev);
c7f439b9 DM	577	struct cg14_par *par = info->par;
50312ce9	578
c7f439b9 DM	579	unregister_framebuffer(info);
c7f439b9 DM	580	fb_dealloc_cmap(&info->cmap);
50312ce9	581
c7f439b9	582	cg14_unmap_regs(op, info, par);
50312ce9	583
c7f439b9	584	framebuffer_release(info);
50312ce9	585
e3a411a3	586	dev_set_drvdata(&op->dev, NULL);
1da177e4 LT	587
	588	return 0;
	589	}
	590
fd098316	591	static const struct of_device_id cg14_match[] = {
50312ce9 DM	592	{
	593	.name = "cgfourteen",
	594	},
	595	{},
	596	};
	597	MODULE_DEVICE_TABLE(of, cg14_match);
1da177e4	598
28541d0f	599	static struct platform_driver cg14_driver = {
4018294b GL	600	.driver = {
	601	.name = "cg14",
	602	.owner = THIS_MODULE,
	603	.of_match_table = cg14_match,
	604	},
50312ce9	605	.probe = cg14_probe,
48c68c4f	606	.remove = cg14_remove,
50312ce9	607	};
1da177e4	608
54433000	609	static int __init cg14_init(void)
50312ce9 DM	610	{
	611	if (fb_get_options("cg14fb", NULL))
	612	return -ENODEV;
	613
28541d0f	614	return platform_driver_register(&cg14_driver);
1da177e4 LT	615	}
1da177e4 LT	616
54433000	617	static void __exit cg14_exit(void)
1da177e4	618	{
28541d0f	619	platform_driver_unregister(&cg14_driver);
1da177e4 LT	620	}
	621
	622	module_init(cg14_init);
1da177e4	623	module_exit(cg14_exit);
1da177e4 LT	624
1da177e4 LT	625	MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
50312ce9 DM	626	MODULE_AUTHOR("David S. Miller <[email protected]>");
50312ce9 DM	627	MODULE_VERSION("2.0");
1da177e4	628	MODULE_LICENSE("GPL");