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can: kvaser_pciefd: Remove useless write to interrupt register
[linux.git] / drivers / net / can / kvaser_pciefd.c
CommitLineData
26ad340e
HC		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2/* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved.
3 * Parts of this driver are based on the following:
4 * - Kvaser linux pciefd driver (version 5.25)
5 * - PEAK linux canfd driver
6 * - Altera Avalon EPCS flash controller driver
7 */
8
9#include <linux/kernel.h>
26ad340e
HC		 10#include <linux/module.h>
11#include <linux/device.h>
fa5cc7e1 12#include <linux/ethtool.h>
26ad340e
HC		 13#include <linux/pci.h>
14#include <linux/can/dev.h>
15#include <linux/timer.h>
16#include <linux/netdevice.h>
17#include <linux/crc32.h>
18#include <linux/iopoll.h>
19
20MODULE_LICENSE("Dual BSD/GPL");
21MODULE_AUTHOR("Kvaser AB <[email protected]>");
22MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
23
24#define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd"
25
26#define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
27#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
28#define KVASER_PCIEFD_MAX_ERR_REP 256
29#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17
30#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4
31#define KVASER_PCIEFD_DMA_COUNT 2
32
33#define KVASER_PCIEFD_DMA_SIZE (4 * 1024)
34#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
35
36#define KVASER_PCIEFD_VENDOR 0x1a07
37#define KVASER_PCIEFD_4HS_ID 0x0d
38#define KVASER_PCIEFD_2HS_ID 0x0e
39#define KVASER_PCIEFD_HS_ID 0x0f
40#define KVASER_PCIEFD_MINIPCIE_HS_ID 0x10
41#define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x11
42
43/* PCIe IRQ registers */
44#define KVASER_PCIEFD_IRQ_REG 0x40
45#define KVASER_PCIEFD_IEN_REG 0x50
46/* DMA map */
47#define KVASER_PCIEFD_DMA_MAP_BASE 0x1000
48/* Kvaser KCAN CAN controller registers */
49#define KVASER_PCIEFD_KCAN0_BASE 0x10000
50#define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
51#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
52#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
53#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
54#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
55#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
56#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
57#define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414
58#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
59#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
60#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
7c6e6bce 61#define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
26ad340e
HC		 62#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
63#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
64/* Loopback control register */
65#define KVASER_PCIEFD_LOOP_REG 0x1f000
66/* System identification and information registers */
67#define KVASER_PCIEFD_SYSID_BASE 0x1f020
68#define KVASER_PCIEFD_SYSID_VERSION_REG (KVASER_PCIEFD_SYSID_BASE + 0x8)
69#define KVASER_PCIEFD_SYSID_CANFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0xc)
ec44dd57 70#define KVASER_PCIEFD_SYSID_BUSFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0x10)
26ad340e
HC		 71#define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14)
72/* Shared receive buffer registers */
73#define KVASER_PCIEFD_SRB_BASE 0x1f200
c589557d 74#define KVASER_PCIEFD_SRB_FIFO_LAST_REG (KVASER_PCIEFD_SRB_BASE + 0x1f4)
26ad340e
HC		 75#define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200)
76#define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204)
77#define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c)
78#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
c589557d 79#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)
26ad340e
HC		 80#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
81/* EPCS flash controller registers */
82#define KVASER_PCIEFD_SPI_BASE 0x1fc00
83#define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE
84#define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4)
85#define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8)
86#define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc)
87#define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14)
88
89#define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f
90#define KVASER_PCIEFD_IRQ_SRB BIT(4)
91
92#define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24
93#define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16
94#define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1
95
96/* Reset DMA buffer 0, 1 and FIFO offset */
97#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
98#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
99#define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
100
101/* DMA packet done, buffer 0 and 1 */
102#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
103#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
104/* DMA overflow, buffer 0 and 1 */
105#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
106#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
107/* DMA underflow, buffer 0 and 1 */
108#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
109#define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
110
111/* DMA idle */
112#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
113/* DMA support */
114#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
115
c589557d
JA		 116/* SRB current packet level */
117#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff
118
26ad340e
HC		 119/* DMA Enable */
120#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
121
122/* EPCS flash controller definitions */
123#define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024)
124#define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L)
125#define KVASER_PCIEFD_CFG_MAX_PARAMS 256
126#define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d
127#define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24
128#define KVASER_PCIEFD_CFG_SYS_VER 1
129#define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130
130#define KVASER_PCIEFD_SPI_TMT BIT(5)
131#define KVASER_PCIEFD_SPI_TRDY BIT(6)
132#define KVASER_PCIEFD_SPI_RRDY BIT(7)
133#define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14
134/* Commands for controlling the onboard flash */
135#define KVASER_PCIEFD_FLASH_RES_CMD 0xab
136#define KVASER_PCIEFD_FLASH_READ_CMD 0x3
137#define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5
138
139/* Kvaser KCAN definitions */
140#define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29)
141#define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29)
142
143#define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16
144/* Request status packet */
145#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
146/* Abort, flush and reset */
147#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
148
149/* Tx FIFO unaligned read */
150#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
151/* Tx FIFO unaligned end */
152#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
153/* Bus parameter protection error */
154#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
155/* FDF bit when controller is in classic mode */
156#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
157/* Rx FIFO overflow */
158#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
159/* Abort done */
160#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
161/* Tx buffer flush done */
162#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
163/* Tx FIFO overflow */
164#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
165/* Tx FIFO empty */
166#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
167/* Transmitter unaligned */
168#define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
169
170#define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16
171
172#define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24
173/* Abort request */
174#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
175/* Idle state. Controller in reset mode and no abort or flush pending */
176#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
177/* Bus off */
178#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
179/* Reset mode request */
180#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
181/* Controller in reset mode */
182#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
183/* Controller got one-shot capability */
184#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
185/* Controller got CAN FD capability */
186#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
187#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR | \
188 KVASER_PCIEFD_KCAN_STAT_BOFF | KVASER_PCIEFD_KCAN_STAT_RMR | \
189 KVASER_PCIEFD_KCAN_STAT_IRM)
190
191/* Reset mode */
192#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
193/* Listen only mode */
194#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
195/* Error packet enable */
196#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
197/* CAN FD non-ISO */
198#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
199/* Acknowledgment packet type */
200#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
201/* Active error flag enable. Clear to force error passive */
202#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
203/* Classic CAN mode */
204#define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
205
206#define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13
207#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17
208#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26
209
210#define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16
211
212/* Kvaser KCAN packet types */
213#define KVASER_PCIEFD_PACK_TYPE_DATA 0
214#define KVASER_PCIEFD_PACK_TYPE_ACK 1
215#define KVASER_PCIEFD_PACK_TYPE_TXRQ 2
216#define KVASER_PCIEFD_PACK_TYPE_ERROR 3
217#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4
218#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5
219#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6
220#define KVASER_PCIEFD_PACK_TYPE_STATUS 8
221#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9
222
223/* Kvaser KCAN packet common definitions */
224#define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff
225#define KVASER_PCIEFD_PACKET_CHID_SHIFT 25
226#define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28
227
228/* Kvaser KCAN TDATA and RDATA first word */
229#define KVASER_PCIEFD_RPACKET_IDE BIT(30)
230#define KVASER_PCIEFD_RPACKET_RTR BIT(29)
231/* Kvaser KCAN TDATA and RDATA second word */
232#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
233#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
234#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
235#define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8
236/* Kvaser KCAN TDATA second word */
237#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
238#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
239
240/* Kvaser KCAN APACKET */
241#define KVASER_PCIEFD_APACKET_FLU BIT(8)
242#define KVASER_PCIEFD_APACKET_CT BIT(9)
243#define KVASER_PCIEFD_APACKET_ABL BIT(10)
244#define KVASER_PCIEFD_APACKET_NACK BIT(11)
245
246/* Kvaser KCAN SPACK first word */
247#define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8
248#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
249#define KVASER_PCIEFD_SPACK_IDET BIT(20)
250#define KVASER_PCIEFD_SPACK_IRM BIT(21)
251#define KVASER_PCIEFD_SPACK_RMCD BIT(22)
252/* Kvaser KCAN SPACK second word */
253#define KVASER_PCIEFD_SPACK_AUTO BIT(21)
254#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
255#define KVASER_PCIEFD_SPACK_EPLR BIT(24)
256
36aea60f
JA		 257/* Kvaser KCAN_EPACK second word */
258#define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
259
26ad340e
HC		 260struct kvaser_pciefd;
261
262struct kvaser_pciefd_can {
263 struct can_priv can;
264 struct kvaser_pciefd *kv_pcie;
265 void __iomem *reg_base;
266 struct can_berr_counter bec;
267 u8 cmd_seq;
268 int err_rep_cnt;
269 int echo_idx;
270 spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */
271 spinlock_t echo_lock; /* Locks the message echo buffer */
272 struct timer_list bec_poll_timer;
273 struct completion start_comp, flush_comp;
274};
275
276struct kvaser_pciefd {
277 struct pci_dev *pci;
278 void __iomem *reg_base;
279 struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS];
280 void *dma_data[KVASER_PCIEFD_DMA_COUNT];
281 u8 nr_channels;
ec44dd57 282 u32 bus_freq;
26ad340e
HC		 283 u32 freq;
284 u32 freq_to_ticks_div;
285};
286
287struct kvaser_pciefd_rx_packet {
288 u32 header[2];
289 u64 timestamp;
290};
291
292struct kvaser_pciefd_tx_packet {
293 u32 header[2];
294 u8 data[64];
295};
296
297static const struct can_bittiming_const kvaser_pciefd_bittiming_const = {
298 .name = KVASER_PCIEFD_DRV_NAME,
299 .tseg1_min = 1,
470e14c0 300 .tseg1_max = 512,
26ad340e
HC		 301 .tseg2_min = 1,
302 .tseg2_max = 32,
303 .sjw_max = 16,
304 .brp_min = 1,
470e14c0 305 .brp_max = 8192,
26ad340e
HC		 306 .brp_inc = 1,
307};
308
309struct kvaser_pciefd_cfg_param {
310 __le32 magic;
311 __le32 nr;
312 __le32 len;
313 u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ];
314};
315
316struct kvaser_pciefd_cfg_img {
317 __le32 version;
318 __le32 magic;
319 __le32 crc;
320 struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS];
321};
322
323static struct pci_device_id kvaser_pciefd_id_table[] = {
324 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), },
325 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), },
326 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), },
327 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), },
328 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), },
329 { 0,},
330};
331MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
332
333/* Onboard flash memory functions */
334static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk)
335{
336 u32 res;
26ad340e 337
7912fc99
JC		 338 return readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
339 res, res & msk, 0, 10);
26ad340e
HC		 340}
341
342static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx,
343 u32 tx_len, u8 *rx, u32 rx_len)
344{
345 int c;
346
347 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
348 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
349 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
350
351 c = tx_len;
352 while (c--) {
353 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
354 return -EIO;
355
356 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
357
358 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
359 return -EIO;
360
361 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
362 }
363
364 c = rx_len;
365 while (c-- > 0) {
366 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
367 return -EIO;
368
369 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
370
371 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
372 return -EIO;
373
374 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
375 }
376
377 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT))
378 return -EIO;
379
380 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
381
382 if (c != -1) {
383 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n");
384 return -EIO;
385 }
386
387 return 0;
388}
389
390static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie,
391 struct kvaser_pciefd_cfg_img *img)
392{
393 int offset = KVASER_PCIEFD_CFG_IMG_OFFSET;
394 int res, crc;
395 u8 *crc_buff;
396
397 u8 cmd[] = {
398 KVASER_PCIEFD_FLASH_READ_CMD,
399 (u8)((offset >> 16) & 0xff),
400 (u8)((offset >> 8) & 0xff),
401 (u8)(offset & 0xff)
402 };
403
404 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img,
405 KVASER_PCIEFD_CFG_IMG_SZ);
406 if (res)
407 return res;
408
409 crc_buff = (u8 *)img->params;
410
411 if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) {
412 dev_err(&pcie->pci->dev,
413 "Config flash corrupted, version number is wrong\n");
414 return -ENODEV;
415 }
416
417 if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) {
418 dev_err(&pcie->pci->dev,
419 "Config flash corrupted, magic number is wrong\n");
420 return -ENODEV;
421 }
422
423 crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params));
424 if (le32_to_cpu(img->crc) != crc) {
425 dev_err(&pcie->pci->dev,
426 "Stored CRC does not match flash image contents\n");
427 return -EIO;
428 }
429
430 return 0;
431}
432
433static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie,
434 struct kvaser_pciefd_cfg_img *img)
435{
436 struct kvaser_pciefd_cfg_param *param;
437
438 param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN];
439 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len));
440}
441
442static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie)
443{
444 int res;
445 struct kvaser_pciefd_cfg_img *img;
446
447 /* Read electronic signature */
448 u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0};
449
450 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1);
451 if (res)
452 return -EIO;
453
454 img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL);
455 if (!img)
456 return -ENOMEM;
457
458 if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) {
459 dev_err(&pcie->pci->dev,
460 "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n",
461 cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16);
462
463 res = -ENODEV;
464 goto image_free;
465 }
466
467 cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD;
468 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1);
469 if (res) {
470 goto image_free;
471 } else if (cmd[0] & 1) {
472 res = -EIO;
473 /* No write is ever done, the WIP should never be set */
474 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n");
475 goto image_free;
476 }
477
478 res = kvaser_pciefd_cfg_read_and_verify(pcie, img);
479 if (res) {
480 res = -EIO;
481 goto image_free;
482 }
483
484 kvaser_pciefd_cfg_read_params(pcie, img);
485
486image_free:
487 kfree(img);
488 return res;
489}
490
491static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
492{
493 u32 cmd;
494
495 cmd = KVASER_PCIEFD_KCAN_CMD_SRQ;
496 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
497 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
498}
499
500static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
501{
502 u32 mode;
503 unsigned long irq;
504
505 spin_lock_irqsave(&can->lock, irq);
506 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
507 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) {
508 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
509 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
510 }
511 spin_unlock_irqrestore(&can->lock, irq);
512}
513
514static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can)
515{
516 u32 mode;
517 unsigned long irq;
518
519 spin_lock_irqsave(&can->lock, irq);
520 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
521 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN;
522 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
523 spin_unlock_irqrestore(&can->lock, irq);
524}
525
526static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
527{
528 u32 msk;
529
530 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF |
531 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |
532 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |
533 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |
262d7a52 534 KVASER_PCIEFD_KCAN_IRQ_TAR;
26ad340e
HC		 535
536 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
537
538 return 0;
539}
540
541static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
542{
543 u32 mode;
544 unsigned long irq;
545
546 spin_lock_irqsave(&can->lock, irq);
547
548 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
549 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
550 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
551 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
552 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN;
553 else
554 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
555 } else {
556 mode |= KVASER_PCIEFD_KCAN_MODE_CCM;
557 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
558 }
559
560 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
561 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;
bf7ac55e
JA		 562 else
563 mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;
26ad340e
HC		 564
565 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;
566 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
567 /* Use ACK packet type */
568 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT;
569 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
570 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
571
572 spin_unlock_irqrestore(&can->lock, irq);
573}
574
575static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
576{
577 u32 status;
578 unsigned long irq;
579
580 spin_lock_irqsave(&can->lock, irq);
581 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
262d7a52 582 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
26ad340e
HC		 583 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
584
585 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
586 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
587 u32 cmd;
588
589 /* If controller is already idle, run abort, flush and reset */
590 cmd = KVASER_PCIEFD_KCAN_CMD_AT;
591 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
592 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
593 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
594 u32 mode;
595
596 /* Put controller in reset mode */
597 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
598 mode |= KVASER_PCIEFD_KCAN_MODE_RM;
599 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
600 }
601
602 spin_unlock_irqrestore(&can->lock, irq);
603}
604
605static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can)
606{
607 u32 mode;
608 unsigned long irq;
609
610 del_timer(&can->bec_poll_timer);
611
612 if (!completion_done(&can->flush_comp))
613 kvaser_pciefd_start_controller_flush(can);
614
615 if (!wait_for_completion_timeout(&can->flush_comp,
616 KVASER_PCIEFD_WAIT_TIMEOUT)) {
617 netdev_err(can->can.dev, "Timeout during bus on flush\n");
618 return -ETIMEDOUT;
619 }
620
621 spin_lock_irqsave(&can->lock, irq);
622 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
623 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
624
262d7a52 625 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
26ad340e
HC		 626 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
627
628 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
629 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
630 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
631 spin_unlock_irqrestore(&can->lock, irq);
632
633 if (!wait_for_completion_timeout(&can->start_comp,
634 KVASER_PCIEFD_WAIT_TIMEOUT)) {
635 netdev_err(can->can.dev, "Timeout during bus on reset\n");
636 return -ETIMEDOUT;
637 }
638 /* Reset interrupt handling */
639 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
640 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
641
642 kvaser_pciefd_set_tx_irq(can);
643 kvaser_pciefd_setup_controller(can);
644
645 can->can.state = CAN_STATE_ERROR_ACTIVE;
646 netif_wake_queue(can->can.dev);
647 can->bec.txerr = 0;
648 can->bec.rxerr = 0;
649 can->err_rep_cnt = 0;
650
651 return 0;
652}
653
654static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)
655{
1910cd88 656 u8 top;
26ad340e
HC		 657 u32 pwm_ctrl;
658 unsigned long irq;
659
660 spin_lock_irqsave(&can->lock, irq);
661 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
662 top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;
663
1910cd88
CB		 664 /* Set duty cycle to zero */
665 pwm_ctrl |= top;
26ad340e
HC		 666 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
667 spin_unlock_irqrestore(&can->lock, irq);
668}
669
670static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can)
671{
672 int top, trigger;
673 u32 pwm_ctrl;
674 unsigned long irq;
675
676 kvaser_pciefd_pwm_stop(can);
677 spin_lock_irqsave(&can->lock, irq);
678
679 /* Set frequency to 500 KHz*/
ec44dd57 680 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
26ad340e
HC		 681
682 pwm_ctrl = top & 0xff;
683 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
684 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
685
686 /* Set duty cycle to 95 */
687 trigger = (100 * top - 95 * (top + 1) + 50) / 100;
688 pwm_ctrl = trigger & 0xff;
689 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
690 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
691 spin_unlock_irqrestore(&can->lock, irq);
692}
693
694static int kvaser_pciefd_open(struct net_device *netdev)
695{
696 int err;
697 struct kvaser_pciefd_can *can = netdev_priv(netdev);
698
699 err = open_candev(netdev);
700 if (err)
701 return err;
702
703 err = kvaser_pciefd_bus_on(can);
13a84cf3
ZQ		 704 if (err) {
705 close_candev(netdev);
26ad340e 706 return err;
13a84cf3 707 }
26ad340e
HC		 708
709 return 0;
710}
711
712static int kvaser_pciefd_stop(struct net_device *netdev)
713{
714 struct kvaser_pciefd_can *can = netdev_priv(netdev);
715 int ret = 0;
716
717 /* Don't interrupt ongoing flush */
718 if (!completion_done(&can->flush_comp))
719 kvaser_pciefd_start_controller_flush(can);
720
721 if (!wait_for_completion_timeout(&can->flush_comp,
722 KVASER_PCIEFD_WAIT_TIMEOUT)) {
723 netdev_err(can->can.dev, "Timeout during stop\n");
724 ret = -ETIMEDOUT;
725 } else {
726 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
727 del_timer(&can->bec_poll_timer);
728 }
aed0e6ca 729 can->can.state = CAN_STATE_STOPPED;
26ad340e
HC		 730 close_candev(netdev);
731
732 return ret;
733}
734
735static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
736 struct kvaser_pciefd_can *can,
737 struct sk_buff *skb)
738{
739 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
740 int packet_size;
741 int seq = can->echo_idx;
742
743 memset(p, 0, sizeof(*p));
744
745 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
746 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;
747
748 if (cf->can_id & CAN_RTR_FLAG)
749 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR;
750
751 if (cf->can_id & CAN_EFF_FLAG)
752 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
753
754 p->header[0] |= cf->can_id & CAN_EFF_MASK;
3ab4ce0d 755 p->header[1] |= can_fd_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT;
26ad340e
HC		 756 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
757
758 if (can_is_canfd_skb(skb)) {
759 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;
760 if (cf->flags & CANFD_BRS)
761 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;
762 if (cf->flags & CANFD_ESI)
763 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
764 }
765
766 p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK;
767
768 packet_size = cf->len;
769 memcpy(p->data, cf->data, packet_size);
770
771 return DIV_ROUND_UP(packet_size, 4);
772}
773
774static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb,
775 struct net_device *netdev)
776{
777 struct kvaser_pciefd_can *can = netdev_priv(netdev);
778 unsigned long irq_flags;
779 struct kvaser_pciefd_tx_packet packet;
780 int nwords;
781 u8 count;
782
ae64438b 783 if (can_dev_dropped_skb(netdev, skb))
26ad340e
HC		 784 return NETDEV_TX_OK;
785
786 nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
787
788 spin_lock_irqsave(&can->echo_lock, irq_flags);
789
790 /* Prepare and save echo skb in internal slot */
1dcb6e57 791 can_put_echo_skb(skb, netdev, can->echo_idx, 0);
26ad340e
HC		 792
793 /* Move echo index to the next slot */
794 can->echo_idx = (can->echo_idx + 1) % can->can.echo_skb_max;
795
796 /* Write header to fifo */
797 iowrite32(packet.header[0],
798 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
799 iowrite32(packet.header[1],
800 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
801
802 if (nwords) {
803 u32 data_last = ((u32 *)packet.data)[nwords - 1];
804
805 /* Write data to fifo, except last word */
806 iowrite32_rep(can->reg_base +
807 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
808 nwords - 1);
809 /* Write last word to end of fifo */
810 __raw_writel(data_last, can->reg_base +
811 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
812 } else {
813 /* Complete write to fifo */
814 __raw_writel(0, can->reg_base +
815 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
816 }
817
818 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
819 /* No room for a new message, stop the queue until at least one
820 * successful transmit
821 */
822 if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT ||
823 can->can.echo_skb[can->echo_idx])
824 netif_stop_queue(netdev);
825
826 spin_unlock_irqrestore(&can->echo_lock, irq_flags);
827
828 return NETDEV_TX_OK;
829}
830
831static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data)
832{
833 u32 mode, test, btrn;
834 unsigned long irq_flags;
835 int ret;
836 struct can_bittiming *bt;
837
838 if (data)
839 bt = &can->can.data_bittiming;
840 else
841 bt = &can->can.bittiming;
842
843 btrn = ((bt->phase_seg2 - 1) & 0x1f) <<
844 KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT |
845 (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) <<
846 KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT |
847 ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT |
848 ((bt->brp - 1) & 0x1fff);
849
850 spin_lock_irqsave(&can->lock, irq_flags);
851 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
852
853 /* Put the circuit in reset mode */
854 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,
855 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
856
857 /* Can only set bittiming if in reset mode */
858 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
859 test, test & KVASER_PCIEFD_KCAN_MODE_RM,
860 0, 10);
861
862 if (ret) {
863 spin_unlock_irqrestore(&can->lock, irq_flags);
864 return -EBUSY;
865 }
866
867 if (data)
868 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
869 else
870 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
871
872 /* Restore previous reset mode status */
873 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
874
875 spin_unlock_irqrestore(&can->lock, irq_flags);
876 return 0;
877}
878
879static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev)
880{
881 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false);
882}
883
884static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev)
885{
886 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true);
887}
888
889static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode)
890{
891 struct kvaser_pciefd_can *can = netdev_priv(ndev);
892 int ret = 0;
893
894 switch (mode) {
895 case CAN_MODE_START:
896 if (!can->can.restart_ms)
897 ret = kvaser_pciefd_bus_on(can);
898 break;
899 default:
900 return -EOPNOTSUPP;
901 }
902
903 return ret;
904}
905
906static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev,
907 struct can_berr_counter *bec)
908{
909 struct kvaser_pciefd_can *can = netdev_priv(ndev);
910
911 bec->rxerr = can->bec.rxerr;
912 bec->txerr = can->bec.txerr;
913 return 0;
914}
915
916static void kvaser_pciefd_bec_poll_timer(struct timer_list *data)
917{
918 struct kvaser_pciefd_can *can = from_timer(can, data, bec_poll_timer);
919
920 kvaser_pciefd_enable_err_gen(can);
921 kvaser_pciefd_request_status(can);
922 can->err_rep_cnt = 0;
923}
924
925static const struct net_device_ops kvaser_pciefd_netdev_ops = {
926 .ndo_open = kvaser_pciefd_open,
927 .ndo_stop = kvaser_pciefd_stop,
fa5cc7e1 928 .ndo_eth_ioctl = can_eth_ioctl_hwts,
26ad340e
HC		 929 .ndo_start_xmit = kvaser_pciefd_start_xmit,
930 .ndo_change_mtu = can_change_mtu,
931};
932
fa5cc7e1
VM		 933static const struct ethtool_ops kvaser_pciefd_ethtool_ops = {
934 .get_ts_info = can_ethtool_op_get_ts_info_hwts,
935};
936
26ad340e
HC		 937static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
938{
939 int i;
940
941 for (i = 0; i < pcie->nr_channels; i++) {
942 struct net_device *netdev;
943 struct kvaser_pciefd_can *can;
944 u32 status, tx_npackets;
945
946 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
947 KVASER_PCIEFD_CAN_TX_MAX_COUNT);
948 if (!netdev)
949 return -ENOMEM;
950
951 can = netdev_priv(netdev);
952 netdev->netdev_ops = &kvaser_pciefd_netdev_ops;
fa5cc7e1 953 netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops;
26ad340e
HC		 954 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
955 i * KVASER_PCIEFD_KCAN_BASE_OFFSET;
956
957 can->kv_pcie = pcie;
958 can->cmd_seq = 0;
959 can->err_rep_cnt = 0;
960 can->bec.txerr = 0;
961 can->bec.rxerr = 0;
962
963 init_completion(&can->start_comp);
964 init_completion(&can->flush_comp);
965 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer,
966 0);
967
7c6e6bce
JA		 968 /* Disable Bus load reporting */
969 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
970
26ad340e
HC		 971 tx_npackets = ioread32(can->reg_base +
972 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
973 if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) &
974 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
975 dev_err(&pcie->pci->dev,
976 "Max Tx count is smaller than expected\n");
977
978 free_candev(netdev);
979 return -ENODEV;
980 }
981
982 can->can.clock.freq = pcie->freq;
983 can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT;
984 can->echo_idx = 0;
985 spin_lock_init(&can->echo_lock);
986 spin_lock_init(&can->lock);
987 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
988 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;
989
990 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
991 can->can.do_set_data_bittiming =
992 kvaser_pciefd_set_data_bittiming;
993
994 can->can.do_set_mode = kvaser_pciefd_set_mode;
995 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
996
997 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
998 CAN_CTRLMODE_FD |
999 CAN_CTRLMODE_FD_NON_ISO;
1000
1001 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1002 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
1003 dev_err(&pcie->pci->dev,
1004 "CAN FD not supported as expected %d\n", i);
1005
1006 free_candev(netdev);
1007 return -ENODEV;
1008 }
1009
1010 if (status & KVASER_PCIEFD_KCAN_STAT_CAP)
1011 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
1012
1013 netdev->flags |= IFF_ECHO;
1014
1015 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
1016
1017 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
262d7a52 1018 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
26ad340e
HC		 1019 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1020
1021 pcie->can[i] = can;
1022 kvaser_pciefd_pwm_start(can);
1023 }
1024
1025 return 0;
1026}
1027
1028static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie)
1029{
1030 int i;
1031
1032 for (i = 0; i < pcie->nr_channels; i++) {
1033 int err = register_candev(pcie->can[i]->can.dev);
1034
1035 if (err) {
1036 int j;
1037
1038 /* Unregister all successfully registered devices. */
1039 for (j = 0; j < i; j++)
1040 unregister_candev(pcie->can[j]->can.dev);
1041 return err;
1042 }
1043 }
1044
1045 return 0;
1046}
1047
1048static void kvaser_pciefd_write_dma_map(struct kvaser_pciefd *pcie,
1049 dma_addr_t addr, int offset)
1050{
1051 u32 word1, word2;
1052
1053#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1054 word1 = addr | KVASER_PCIEFD_64BIT_DMA_BIT;
1055 word2 = addr >> 32;
1056#else
1057 word1 = addr;
1058 word2 = 0;
1059#endif
1060 iowrite32(word1, pcie->reg_base + offset);
1061 iowrite32(word2, pcie->reg_base + offset + 4);
1062}
1063
1064static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
1065{
1066 int i;
1067 u32 srb_status;
c589557d 1068 u32 srb_packet_count;
26ad340e
HC		 1069 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT];
1070
1071 /* Disable the DMA */
1072 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1073 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1074 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i;
1075
1076 pcie->dma_data[i] =
1077 dmam_alloc_coherent(&pcie->pci->dev,
1078 KVASER_PCIEFD_DMA_SIZE,
1079 &dma_addr[i],
1080 GFP_KERNEL);
1081
1082 if (!pcie->dma_data[i] || !dma_addr[i]) {
1083 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1084 KVASER_PCIEFD_DMA_SIZE);
1085 return -ENOMEM;
1086 }
1087
1088 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);
1089 }
1090
1091 /* Reset Rx FIFO, and both DMA buffers */
1092 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |
1093 KVASER_PCIEFD_SRB_CMD_RDB1,
1094 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1095
c589557d
JA		 1096 /* Empty Rx FIFO */
1097 srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &
1098 KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK;
1099 while (srb_packet_count) {
1100 /* Drop current packet in FIFO */
1101 ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
1102 srb_packet_count--;
1103 }
1104
26ad340e
HC		 1105 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1106 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) {
1107 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
1108 return -EIO;
1109 }
1110
1111 /* Enable the DMA */
1112 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE,
1113 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1114
1115 return 0;
1116}
1117
1118static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1119{
1120 u32 sysid, srb_status, build;
1121 u8 sysid_nr_chan;
1122 int ret;
1123
1124 ret = kvaser_pciefd_read_cfg(pcie);
1125 if (ret)
1126 return ret;
1127
1128 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1129 sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff;
1130 if (pcie->nr_channels != sysid_nr_chan) {
1131 dev_err(&pcie->pci->dev,
1132 "Number of channels does not match: %u vs %u\n",
1133 pcie->nr_channels,
1134 sysid_nr_chan);
1135 return -ENODEV;
1136 }
1137
1138 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS)
1139 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS;
1140
1141 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1142 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",
1143 (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff,
1144 sysid & 0xff,
1145 (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff);
1146
1147 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1148 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1149 dev_err(&pcie->pci->dev,
1150 "Hardware without DMA is not supported\n");
1151 return -ENODEV;
1152 }
1153
ec44dd57
CB		 1154 pcie->bus_freq = ioread32(pcie->reg_base +
1155 KVASER_PCIEFD_SYSID_BUSFREQ_REG);
26ad340e
HC		 1156 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1157 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1158 if (pcie->freq_to_ticks_div == 0)
1159 pcie->freq_to_ticks_div = 1;
1160
1161 /* Turn off all loopback functionality */
1162 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1163 return ret;
1164}
1165
1166static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
1167 struct kvaser_pciefd_rx_packet *p,
1168 __le32 *data)
1169{
1170 struct sk_buff *skb;
1171 struct canfd_frame *cf;
1172 struct can_priv *priv;
1173 struct net_device_stats *stats;
1174 struct skb_shared_hwtstamps *shhwtstamps;
1175 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1176
1177 if (ch_id >= pcie->nr_channels)
1178 return -EIO;
1179
1180 priv = &pcie->can[ch_id]->can;
1181 stats = &priv->dev->stats;
1182
1183 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1184 skb = alloc_canfd_skb(priv->dev, &cf);
1185 if (!skb) {
1186 stats->rx_dropped++;
1187 return -ENOMEM;
1188 }
1189
1190 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1191 cf->flags |= CANFD_BRS;
1192
1193 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1194 cf->flags |= CANFD_ESI;
1195 } else {
1196 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1197 if (!skb) {
1198 stats->rx_dropped++;
1199 return -ENOMEM;
1200 }
1201 }
1202
1203 cf->can_id = p->header[0] & CAN_EFF_MASK;
1204 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1205 cf->can_id |= CAN_EFF_FLAG;
1206
3ab4ce0d 1207 cf->len = can_fd_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT);
26ad340e 1208
8e674ca7 1209 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {
26ad340e 1210 cf->can_id |= CAN_RTR_FLAG;
8e674ca7 1211 } else {
26ad340e
HC		 1212 memcpy(cf->data, data, cf->len);
1213
8e674ca7
VM		 1214 stats->rx_bytes += cf->len;
1215 }
1216 stats->rx_packets++;
1217
26ad340e
HC		 1218 shhwtstamps = skb_hwtstamps(skb);
1219
1220 shhwtstamps->hwtstamp =
1221 ns_to_ktime(div_u64(p->timestamp * 1000,
1222 pcie->freq_to_ticks_div));
1223
26ad340e
HC		 1224 return netif_rx(skb);
1225}
1226
1227static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can,
1228 struct can_frame *cf,
1229 enum can_state new_state,
1230 enum can_state tx_state,
1231 enum can_state rx_state)
1232{
1233 can_change_state(can->can.dev, cf, tx_state, rx_state);
1234
1235 if (new_state == CAN_STATE_BUS_OFF) {
1236 struct net_device *ndev = can->can.dev;
1237 unsigned long irq_flags;
1238
1239 spin_lock_irqsave(&can->lock, irq_flags);
1240 netif_stop_queue(can->can.dev);
1241 spin_unlock_irqrestore(&can->lock, irq_flags);
1242
1243 /* Prevent CAN controller from auto recover from bus off */
1244 if (!can->can.restart_ms) {
1245 kvaser_pciefd_start_controller_flush(can);
1246 can_bus_off(ndev);
1247 }
1248 }
1249}
1250
1251static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p,
1252 struct can_berr_counter *bec,
1253 enum can_state *new_state,
1254 enum can_state *tx_state,
1255 enum can_state *rx_state)
1256{
1257 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||
1258 p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1259 *new_state = CAN_STATE_BUS_OFF;
1260 else if (bec->txerr >= 255 || bec->rxerr >= 255)
1261 *new_state = CAN_STATE_BUS_OFF;
1262 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1263 *new_state = CAN_STATE_ERROR_PASSIVE;
1264 else if (bec->txerr >= 128 || bec->rxerr >= 128)
1265 *new_state = CAN_STATE_ERROR_PASSIVE;
1266 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR)
1267 *new_state = CAN_STATE_ERROR_WARNING;
1268 else if (bec->txerr >= 96 || bec->rxerr >= 96)
1269 *new_state = CAN_STATE_ERROR_WARNING;
1270 else
1271 *new_state = CAN_STATE_ERROR_ACTIVE;
1272
1273 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0;
1274 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;
1275}
1276
1277static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can,
1278 struct kvaser_pciefd_rx_packet *p)
1279{
1280 struct can_berr_counter bec;
1281 enum can_state old_state, new_state, tx_state, rx_state;
1282 struct net_device *ndev = can->can.dev;
1283 struct sk_buff *skb;
1284 struct can_frame *cf = NULL;
1285 struct skb_shared_hwtstamps *shhwtstamps;
1286 struct net_device_stats *stats = &ndev->stats;
1287
1288 old_state = can->can.state;
1289
1290 bec.txerr = p->header[0] & 0xff;
1291 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1292
1293 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1294 &rx_state);
1295
1296 skb = alloc_can_err_skb(ndev, &cf);
1297
1298 if (new_state != old_state) {
1299 kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1300 rx_state);
1301
1302 if (old_state == CAN_STATE_BUS_OFF &&
1303 new_state == CAN_STATE_ERROR_ACTIVE &&
1304 can->can.restart_ms) {
1305 can->can.can_stats.restarts++;
1306 if (skb)
1307 cf->can_id |= CAN_ERR_RESTARTED;
1308 }
1309 }
1310
1311 can->err_rep_cnt++;
1312 can->can.can_stats.bus_error++;
36aea60f
JA		 1313 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)
1314 stats->tx_errors++;
1315 else
1316 stats->rx_errors++;
26ad340e
HC		 1317
1318 can->bec.txerr = bec.txerr;
1319 can->bec.rxerr = bec.rxerr;
1320
1321 if (!skb) {
1322 stats->rx_dropped++;
1323 return -ENOMEM;
1324 }
1325
1326 shhwtstamps = skb_hwtstamps(skb);
1327 shhwtstamps->hwtstamp =
1328 ns_to_ktime(div_u64(p->timestamp * 1000,
1329 can->kv_pcie->freq_to_ticks_div));
3e5c291c 1330 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_CNT;
26ad340e
HC		 1331
1332 cf->data[6] = bec.txerr;
1333 cf->data[7] = bec.rxerr;
1334
26ad340e
HC		 1335 netif_rx(skb);
1336 return 0;
1337}
1338
1339static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
1340 struct kvaser_pciefd_rx_packet *p)
1341{
1342 struct kvaser_pciefd_can *can;
1343 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1344
1345 if (ch_id >= pcie->nr_channels)
1346 return -EIO;
1347
1348 can = pcie->can[ch_id];
1349
1350 kvaser_pciefd_rx_error_frame(can, p);
1351 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1352 /* Do not report more errors, until bec_poll_timer expires */
1353 kvaser_pciefd_disable_err_gen(can);
1354 /* Start polling the error counters */
1355 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1356 return 0;
1357}
1358
1359static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can,
1360 struct kvaser_pciefd_rx_packet *p)
1361{
1362 struct can_berr_counter bec;
1363 enum can_state old_state, new_state, tx_state, rx_state;
1364
1365 old_state = can->can.state;
1366
1367 bec.txerr = p->header[0] & 0xff;
1368 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1369
1370 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1371 &rx_state);
1372
1373 if (new_state != old_state) {
1374 struct net_device *ndev = can->can.dev;
1375 struct sk_buff *skb;
1376 struct can_frame *cf;
1377 struct skb_shared_hwtstamps *shhwtstamps;
1378
1379 skb = alloc_can_err_skb(ndev, &cf);
1380 if (!skb) {
1381 struct net_device_stats *stats = &ndev->stats;
1382
1383 stats->rx_dropped++;
1384 return -ENOMEM;
1385 }
1386
1387 kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1388 rx_state);
1389
1390 if (old_state == CAN_STATE_BUS_OFF &&
1391 new_state == CAN_STATE_ERROR_ACTIVE &&
1392 can->can.restart_ms) {
1393 can->can.can_stats.restarts++;
1394 cf->can_id |= CAN_ERR_RESTARTED;
1395 }
1396
1397 shhwtstamps = skb_hwtstamps(skb);
1398 shhwtstamps->hwtstamp =
1399 ns_to_ktime(div_u64(p->timestamp * 1000,
1400 can->kv_pcie->freq_to_ticks_div));
1401
1402 cf->data[6] = bec.txerr;
1403 cf->data[7] = bec.rxerr;
1404
1405 netif_rx(skb);
1406 }
1407 can->bec.txerr = bec.txerr;
1408 can->bec.rxerr = bec.rxerr;
1409 /* Check if we need to poll the error counters */
1410 if (bec.txerr || bec.rxerr)
1411 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1412
1413 return 0;
1414}
1415
1416static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
1417 struct kvaser_pciefd_rx_packet *p)
1418{
1419 struct kvaser_pciefd_can *can;
1420 u8 cmdseq;
1421 u32 status;
1422 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1423
1424 if (ch_id >= pcie->nr_channels)
1425 return -EIO;
1426
1427 can = pcie->can[ch_id];
1428
1429 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1430 cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff;
1431
1432 /* Reset done, start abort and flush */
1433 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1434 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1435 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1436 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
1437 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1438 u32 cmd;
1439
1440 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1441 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1442 cmd = KVASER_PCIEFD_KCAN_CMD_AT;
1443 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
1444 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
26ad340e
HC		 1445 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1446 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1447 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
1448 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1449 /* Reset detected, send end of flush if no packet are in FIFO */
1450 u8 count = ioread32(can->reg_base +
1451 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1452
1453 if (!count)
1454 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1455 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1456 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1457 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) {
1458 /* Response to status request received */
1459 kvaser_pciefd_handle_status_resp(can, p);
1460 if (can->can.state != CAN_STATE_BUS_OFF &&
1461 can->can.state != CAN_STATE_ERROR_ACTIVE) {
1462 mod_timer(&can->bec_poll_timer,
1463 KVASER_PCIEFD_BEC_POLL_FREQ);
1464 }
1465 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1466 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) {
1467 /* Reset to bus on detected */
1468 if (!completion_done(&can->start_comp))
1469 complete(&can->start_comp);
1470 }
1471
1472 return 0;
1473}
1474
1475static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie,
1476 struct kvaser_pciefd_rx_packet *p)
1477{
1478 struct kvaser_pciefd_can *can;
1479 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1480
1481 if (ch_id >= pcie->nr_channels)
1482 return -EIO;
1483
1484 can = pcie->can[ch_id];
1485
1486 /* If this is the last flushed packet, send end of flush */
1487 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1488 u8 count = ioread32(can->reg_base +
1489 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1490
1491 if (count == 0)
1492 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1493 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1494 } else {
1495 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
9420e1d4 1496 int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);
26ad340e
HC		 1497 struct net_device_stats *stats = &can->can.dev->stats;
1498
1499 stats->tx_bytes += dlc;
1500 stats->tx_packets++;
1501
1502 if (netif_queue_stopped(can->can.dev))
1503 netif_wake_queue(can->can.dev);
1504 }
1505
1506 return 0;
1507}
1508
1509static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1510 struct kvaser_pciefd_rx_packet *p)
1511{
1512 struct sk_buff *skb;
1513 struct net_device_stats *stats = &can->can.dev->stats;
1514 struct can_frame *cf;
1515
1516 skb = alloc_can_err_skb(can->can.dev, &cf);
1517
1518 stats->tx_errors++;
1519 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1520 if (skb)
1521 cf->can_id |= CAN_ERR_LOSTARB;
1522 can->can.can_stats.arbitration_lost++;
1523 } else if (skb) {
1524 cf->can_id |= CAN_ERR_ACK;
1525 }
1526
1527 if (skb) {
1528 cf->can_id |= CAN_ERR_BUSERROR;
26ad340e
HC		 1529 netif_rx(skb);
1530 } else {
1531 stats->rx_dropped++;
1532 netdev_warn(can->can.dev, "No memory left for err_skb\n");
1533 }
1534}
1535
1536static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
1537 struct kvaser_pciefd_rx_packet *p)
1538{
1539 struct kvaser_pciefd_can *can;
1540 bool one_shot_fail = false;
1541 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1542
1543 if (ch_id >= pcie->nr_channels)
1544 return -EIO;
1545
1546 can = pcie->can[ch_id];
1547 /* Ignore control packet ACK */
1548 if (p->header[0] & KVASER_PCIEFD_APACKET_CT)
1549 return 0;
1550
1551 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) {
1552 kvaser_pciefd_handle_nack_packet(can, p);
1553 one_shot_fail = true;
1554 }
1555
1556 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1557 netdev_dbg(can->can.dev, "Packet was flushed\n");
1558 } else {
1559 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
9420e1d4 1560 int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);
26ad340e
HC		 1561 u8 count = ioread32(can->reg_base +
1562 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1563
1564 if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT &&
1565 netif_queue_stopped(can->can.dev))
1566 netif_wake_queue(can->can.dev);
1567
1568 if (!one_shot_fail) {
1569 struct net_device_stats *stats = &can->can.dev->stats;
1570
1571 stats->tx_bytes += dlc;
1572 stats->tx_packets++;
1573 }
1574 }
1575
1576 return 0;
1577}
1578
1579static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
1580 struct kvaser_pciefd_rx_packet *p)
1581{
1582 struct kvaser_pciefd_can *can;
1583 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1584
1585 if (ch_id >= pcie->nr_channels)
1586 return -EIO;
1587
1588 can = pcie->can[ch_id];
1589
1590 if (!completion_done(&can->flush_comp))
1591 complete(&can->flush_comp);
1592
1593 return 0;
1594}
1595
1596static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
1597 int dma_buf)
1598{
1599 __le32 *buffer = pcie->dma_data[dma_buf];
1600 __le64 timestamp;
1601 struct kvaser_pciefd_rx_packet packet;
1602 struct kvaser_pciefd_rx_packet *p = &packet;
1603 u8 type;
1604 int pos = *start_pos;
1605 int size;
1606 int ret = 0;
1607
1608 size = le32_to_cpu(buffer[pos++]);
1609 if (!size) {
1610 *start_pos = 0;
1611 return 0;
1612 }
1613
1614 p->header[0] = le32_to_cpu(buffer[pos++]);
1615 p->header[1] = le32_to_cpu(buffer[pos++]);
1616
1617 /* Read 64-bit timestamp */
1618 memcpy(&timestamp, &buffer[pos], sizeof(__le64));
1619 pos += 2;
1620 p->timestamp = le64_to_cpu(timestamp);
1621
1622 type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf;
1623 switch (type) {
1624 case KVASER_PCIEFD_PACK_TYPE_DATA:
1625 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1626 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1627 u8 data_len;
1628
3ab4ce0d 1629 data_len = can_fd_dlc2len(p->header[1] >>
26ad340e
HC		 1630 KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1631 pos += DIV_ROUND_UP(data_len, 4);
1632 }
1633 break;
1634
1635 case KVASER_PCIEFD_PACK_TYPE_ACK:
1636 ret = kvaser_pciefd_handle_ack_packet(pcie, p);
1637 break;
1638
1639 case KVASER_PCIEFD_PACK_TYPE_STATUS:
1640 ret = kvaser_pciefd_handle_status_packet(pcie, p);
1641 break;
1642
1643 case KVASER_PCIEFD_PACK_TYPE_ERROR:
1644 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1645 break;
1646
1647 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1648 ret = kvaser_pciefd_handle_eack_packet(pcie, p);
1649 break;
1650
1651 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1652 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1653 break;
1654
1655 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1656 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
1657 case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1658 dev_info(&pcie->pci->dev,
1659 "Received unexpected packet type 0x%08X\n", type);
1660 break;
1661
1662 default:
1663 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);
1664 ret = -EIO;
1665 break;
1666 }
1667
1668 if (ret)
1669 return ret;
1670
1671 /* Position does not point to the end of the package,
1672 * corrupted packet size?
1673 */
1674 if ((*start_pos + size) != pos)
1675 return -EIO;
1676
1677 /* Point to the next packet header, if any */
1678 *start_pos = pos;
1679
1680 return ret;
1681}
1682
1683static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf)
1684{
1685 int pos = 0;
1686 int res = 0;
1687
1688 do {
1689 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf);
1690 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE);
1691
1692 return res;
1693}
1694
1695static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1696{
1697 u32 irq;
1698
1699 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1700 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) {
1701 kvaser_pciefd_read_buffer(pcie, 0);
1702 /* Reset DMA buffer 0 */
1703 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1704 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1705 }
1706
1707 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) {
1708 kvaser_pciefd_read_buffer(pcie, 1);
1709 /* Reset DMA buffer 1 */
1710 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1711 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1712 }
1713
1714 if (irq & KVASER_PCIEFD_SRB_IRQ_DOF0 ||
1715 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 ||
1716 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 ||
1717 irq & KVASER_PCIEFD_SRB_IRQ_DUF1)
1718 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1719
1720 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1721 return 0;
1722}
1723
1724static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1725{
1726 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1727
1728 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF)
1729 netdev_err(can->can.dev, "Tx FIFO overflow\n");
1730
26ad340e
HC		 1731 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP)
1732 netdev_err(can->can.dev,
1733 "Fail to change bittiming, when not in reset mode\n");
1734
1735 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC)
1736 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n");
1737
1738 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF)
1739 netdev_err(can->can.dev, "Rx FIFO overflow\n");
1740
1741 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1742 return 0;
1743}
1744
1745static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
1746{
1747 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev;
1748 u32 board_irq;
1749 int i;
1750
1751 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1752
1753 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK))
1754 return IRQ_NONE;
1755
1756 if (board_irq & KVASER_PCIEFD_IRQ_SRB)
1757 kvaser_pciefd_receive_irq(pcie);
1758
1759 for (i = 0; i < pcie->nr_channels; i++) {
1760 if (!pcie->can[i]) {
1761 dev_err(&pcie->pci->dev,
1762 "IRQ mask points to unallocated controller\n");
1763 break;
1764 }
1765
1766 /* Check that mask matches channel (i) IRQ mask */
1767 if (board_irq & (1 << i))
1768 kvaser_pciefd_transmit_irq(pcie->can[i]);
1769 }
1770
26ad340e
HC		 1771 return IRQ_HANDLED;
1772}
1773
1774static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1775{
1776 int i;
1777 struct kvaser_pciefd_can *can;
1778
1779 for (i = 0; i < pcie->nr_channels; i++) {
1780 can = pcie->can[i];
1781 if (can) {
1782 iowrite32(0,
1783 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1784 kvaser_pciefd_pwm_stop(can);
1785 free_candev(can->can.dev);
1786 }
1787 }
1788}
1789
1790static int kvaser_pciefd_probe(struct pci_dev *pdev,
1791 const struct pci_device_id *id)
1792{
1793 int err;
1794 struct kvaser_pciefd *pcie;
1795
1796 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1797 if (!pcie)
1798 return -ENOMEM;
1799
1800 pci_set_drvdata(pdev, pcie);
1801 pcie->pci = pdev;
1802
1803 err = pci_enable_device(pdev);
1804 if (err)
1805 return err;
1806
1807 err = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME);
1808 if (err)
1809 goto err_disable_pci;
1810
1811 pcie->reg_base = pci_iomap(pdev, 0, 0);
1812 if (!pcie->reg_base) {
1813 err = -ENOMEM;
1814 goto err_release_regions;
1815 }
1816
1817 err = kvaser_pciefd_setup_board(pcie);
1818 if (err)
1819 goto err_pci_iounmap;
1820
1821 err = kvaser_pciefd_setup_dma(pcie);
1822 if (err)
1823 goto err_pci_iounmap;
1824
1825 pci_set_master(pdev);
1826
1827 err = kvaser_pciefd_setup_can_ctrls(pcie);
1828 if (err)
1829 goto err_teardown_can_ctrls;
1830
84762d8d
JA		 1831 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,
1832 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);
1833 if (err)
1834 goto err_teardown_can_ctrls;
1835
26ad340e
HC		 1836 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1,
1837 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1838
1839 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 |
1840 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 |
1841 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,
1842 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1843
7c921556 1844 /* Enable PCI interrupts */
26ad340e
HC		 1845 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1846 pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1847
1848 /* Ready the DMA buffers */
1849 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1850 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1851 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1852 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1853
26ad340e
HC		 1854 err = kvaser_pciefd_reg_candev(pcie);
1855 if (err)
1856 goto err_free_irq;
1857
1858 return 0;
1859
1860err_free_irq:
11164bc3
JA		 1861 /* Disable PCI interrupts */
1862 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
26ad340e
HC		 1863 free_irq(pcie->pci->irq, pcie);
1864
1865err_teardown_can_ctrls:
1866 kvaser_pciefd_teardown_can_ctrls(pcie);
1867 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1868 pci_clear_master(pdev);
1869
1870err_pci_iounmap:
1871 pci_iounmap(pdev, pcie->reg_base);
1872
1873err_release_regions:
1874 pci_release_regions(pdev);
1875
1876err_disable_pci:
1877 pci_disable_device(pdev);
1878
1879 return err;
1880}
1881
1882static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1883{
1884 struct kvaser_pciefd_can *can;
1885 int i;
1886
1887 for (i = 0; i < pcie->nr_channels; i++) {
1888 can = pcie->can[i];
1889 if (can) {
1890 iowrite32(0,
1891 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1892 unregister_candev(can->can.dev);
1893 del_timer(&can->bec_poll_timer);
1894 kvaser_pciefd_pwm_stop(can);
1895 free_candev(can->can.dev);
1896 }
1897 }
1898}
1899
1900static void kvaser_pciefd_remove(struct pci_dev *pdev)
1901{
1902 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev);
1903
1904 kvaser_pciefd_remove_all_ctrls(pcie);
1905
7c921556 1906 /* Disable interrupts */
26ad340e 1907 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
26ad340e
HC		 1908 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1909
1910 free_irq(pcie->pci->irq, pcie);
1911
26ad340e
HC		 1912 pci_iounmap(pdev, pcie->reg_base);
1913 pci_release_regions(pdev);
1914 pci_disable_device(pdev);
1915}
1916
1917static struct pci_driver kvaser_pciefd = {
1918 .name = KVASER_PCIEFD_DRV_NAME,
1919 .id_table = kvaser_pciefd_id_table,
1920 .probe = kvaser_pciefd_probe,
1921 .remove = kvaser_pciefd_remove,
1922};
1923
1924module_pci_driver(kvaser_pciefd)
Empty description
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